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Merge branch 'fix/spi_buslock_multi_dev_acq_release_issue_v6.0' into 'release/v6.0'

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fix(esp_hw_support): fixed spi buslock multi dev acq/release logic issue (v6.0)

See merge request espressif/esp-idf!49168
This commit is contained in:
morris
2026-07-07 14:53:55 +08:00
parent 2c62bd65b0 c19e3df6c9
commit db3825c799
15 changed files with 277 additions and 201 deletions
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1
components/esp_driver_spi/include/driver/spi_slave_hd.h
View File

@@ -65,6 +65,7 @@ typedef struct {
#define SPI_SLAVE_HD_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first
#define SPI_SLAVE_HD_BIT_LSBFIRST (SPI_SLAVE_HD_TXBIT_LSBFIRST|SPI_SLAVE_HD_RXBIT_LSBFIRST) ///< Transmit and receive LSB first
#define SPI_SLAVE_HD_APPEND_MODE (1<<2) ///< Adopt DMA append mode for transactions. In this mode, users can load(append) DMA descriptors without stopping the DMA
#define SPI_SLAVE_HD_3WIRE_MODE (1<<3) ///< Use MOSI (=spid) for both sending and receiving data, and the master should only use the 1-bit mask for SPI Slave HD commands
/// Configuration structure for the SPI Slave HD driver
typedef struct {

2
components/esp_driver_spi/include/esp_private/spi_common_internal.h
View File

@@ -23,6 +23,8 @@ extern "C"
{
#endif
#define SPI_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
//NOTE!! If both A and B are not defined, '#if (A==B)' is true, because GCC use 0 stand for undefined symbol
#if SOC_GPSPI_SUPPORTED && defined(SOC_GDMA_BUS_AXI) && (SOC_GDMA_TRIG_PERIPH_SPI2_BUS == SOC_GDMA_BUS_AXI)
#define DMA_DESC_MEM_ALIGN_SIZE 8

12
components/esp_driver_spi/src/gpspi/spi_common.c
View File

@@ -357,6 +357,14 @@ esp_err_t spicommon_dma_desc_alloc(spi_host_device_t host_id, int cfg_max_sz, in
}
return ESP_ERR_NO_MEM;
}
// cache sync using align_up length thanks to heap alloc already consider the cache alignment requirement
uint8_t aligned_len = SPI_ALIGN_UP(sizeof(spi_dma_desc_t) * dma_desc_ct, bus_ctx[host_id]->bus_attr.cache_align_int);
// write back and then invalidate the cache, because later we will read/write the link list items by non-cached address
esp_err_t ret = esp_cache_msync(dma_ctx->dmadesc_tx, aligned_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
ESP_RETURN_ON_FALSE_ISR((ret == ESP_OK) || (ret == ESP_ERR_NOT_SUPPORTED), ESP_ERR_INVALID_ARG, SPI_TAG, "dma desc sync failed");
ret = esp_cache_msync(dma_ctx->dmadesc_rx, aligned_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE);
ESP_RETURN_ON_FALSE_ISR((ret == ESP_OK) || (ret == ESP_ERR_NOT_SUPPORTED), ESP_ERR_INVALID_ARG, SPI_TAG, "dma desc sync failed");
dma_ctx->dma_desc_num = dma_desc_ct;
*actual_max_sz = dma_desc_ct * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
return ESP_OK;
@@ -751,8 +759,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
} else {
//Use GPIO matrix
if (bus_config->mosi_io_num >= 0) {
int in_sig = spi_periph_signal[host].spid_in; // always connect input in case sio mode device is used
int out_sig = ((flags & SPICOMMON_BUSFLAG_MASTER) || (temp_flag & SPICOMMON_BUSFLAG_DUAL)) ? spi_periph_signal[host].spid_out : -1;
int in_sig = spi_periph_signal[host].spid_in; // always connect input in case sio master is used
int out_sig = spi_periph_signal[host].spid_out;// always connect output in case sio slave is used, output capability is checked in slave hd driver
s_spi_common_bus_via_gpio(bus_config->mosi_io_num, in_sig, out_sig, &gpio_reserv);
}
if (bus_config->miso_io_num >= 0) {

7
components/esp_driver_spi/src/gpspi/spi_slave_hd.c
View File

@@ -99,6 +99,7 @@ static esp_err_t s_spi_create_sleep_retention_cb(void *arg)
esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config, const spi_slave_hd_slot_config_t *config)
{
bool append_mode = (config->flags & SPI_SLAVE_HD_APPEND_MODE);
bool three_wire_mode = (config->flags & SPI_SLAVE_HD_3WIRE_MODE);
esp_err_t ret = ESP_OK;
SPIHD_CHECK(VALID_HOST(host_id), "invalid host", ESP_ERR_INVALID_ARG);
@@ -111,6 +112,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
#ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM
SPIHD_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG);
#endif
SPIHD_CHECK(!three_wire_mode || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num), "mosi pin must be output capable in 3-wire mode", ESP_ERR_INVALID_ARG);
SPIHD_CHECK(ESP_OK == spicommon_bus_alloc(host_id, "slave_hd"), "host already in use", ESP_ERR_INVALID_STATE);
// spi_slave_hd_slot_t contains atomic variable, memory must be allocated from internal memory
@@ -170,9 +172,10 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
.host_id = host_id,
.dma_enabled = true,
.append_mode = append_mode,
.three_wire_mode = three_wire_mode,
.mode = config->mode,
.tx_lsbfirst = (config->flags & SPI_SLAVE_HD_RXBIT_LSBFIRST),
.rx_lsbfirst = (config->flags & SPI_SLAVE_HD_TXBIT_LSBFIRST),
.tx_lsbfirst = (config->flags & SPI_SLAVE_HD_TXBIT_LSBFIRST),
.rx_lsbfirst = (config->flags & SPI_SLAVE_HD_RXBIT_LSBFIRST),
};
//Init the hal according to the hal_config set above

2
components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
View File

@@ -55,7 +55,7 @@
#elif CONFIG_IDF_TARGET_ESP32C6
#define IDF_TARGET_MAX_SPI_CLK_FREQ 26666*1000
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 35 //TODO: IDF-9551, check perform
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 37 //TODO: IDF-9551, check perform
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 19
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 32
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15

1
components/esp_driver_spi/test_apps/master/main/idf_component.yml
View File

@@ -5,3 +5,4 @@ dependencies:
path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils
spi_bench_mark:
path: ${IDF_PATH}/components/esp_driver_spi/test_apps/components/spi_bench_mark
espressif/esp_serial_slave_link: "^1.1.0"

60
components/esp_driver_spi/test_apps/master/main/test_spi_bus_lock.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -347,3 +347,61 @@ TEST_CASE("spi master can be used on SPI1", "[spi]")
//TODO: add a case when a non-polling transaction happened in the bus-acquiring time and then release the bus then queue a new trans
#endif //!(CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32)
#define TEST_LARGE_TRANS_LEN 2048
static void dev2_polling_task(void *arg)
{
task_context_t *ctx = (task_context_t *)arg;
spi_transaction_t t = {
.flags = SPI_TRANS_USE_TXDATA,
.length = 32,
};
while (!ctx->finished) {
TEST_ESP_OK(spi_device_polling_transmit(ctx->handle, &t));
vTaskDelay(pdMS_TO_TICKS(1));
}
vTaskDelete(NULL);
}
TEST_CASE("release_bus during flying is safe to other device acquiring", "[spi]")
{
spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
spi_device_interface_config_t devcfg_p = SPI_DEVICE_TEST_DEFAULT_CONFIG();
spi_device_interface_config_t devcfg_q = SPI_DEVICE_TEST_DEFAULT_CONFIG();
devcfg_q.spics_io_num = -1;
devcfg_q.queue_size = 3;
devcfg_q.clock_speed_hz = 500 * 1000;
spi_device_handle_t dev_q;
task_context_t ctx = {};
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg_p, &ctx.handle));
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg_q, &dev_q));
// polling task with higher priority than the interrupt task
xTaskCreate(dev2_polling_task, "spi17860_p", 4096, &ctx, 6, NULL);
uint8_t *q_txb = heap_caps_malloc(TEST_LARGE_TRANS_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
spi_transaction_t *ret_trans, trans = {
.length = TEST_LARGE_TRANS_LEN * 8,
.tx_buffer = q_txb,
};
for (int i = 0; i < 30; i++) {
TEST_ESP_OK(spi_device_acquire_bus(dev_q, portMAX_DELAY));
TEST_ESP_OK(spi_device_queue_trans(dev_q, &trans, portMAX_DELAY));
esp_rom_printf("queue trans %d\n", i);
spi_device_release_bus(dev_q);
}
ctx.finished = true;
vTaskDelay(pdMS_TO_TICKS(100)); // wait for all trans finished
for (int i = 0; i < devcfg_q.queue_size; i++) {
spi_device_get_trans_result(dev_q, &ret_trans, 0);
}
free(q_txb);
TEST_ESP_OK(spi_bus_remove_device(ctx.handle));
TEST_ESP_OK(spi_bus_remove_device(dev_q));
TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
}

250
components/esp_driver_spi/test_apps/master/main/test_spi_sio.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,12 +22,16 @@
#include "driver/spi_slave.h"
#include "esp_heap_caps.h"
#include "esp_log.h"
#include "soc/soc_caps.h"
#include "soc/spi_periph.h"
#include "soc/gpio_struct.h"
#include "test_utils.h"
#include "test_spi_utils.h"
#include "test_dualboard_utils.h"
#include "hal/spi_ll.h"
#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
#include "driver/spi_slave_hd.h"
#include "esp_serial_slave_link/essl_spi.h"
#endif
#if (TEST_SPI_PERIPH_NUM >= 2)
//These will be only enabled on chips with 2 or more SPI peripherals
@@ -35,27 +39,6 @@
/********************************************************************************
* Test SIO
********************************************************************************/
#if CONFIG_IDF_TARGET_ESP32
#define MASTER_DIN_SIGNAL HSPID_IN_IDX
#elif CONFIG_IDF_TARGET_ESP32P4
#define MASTER_DIN_SIGNAL SPI2_D_PAD_IN_IDX
#else
#define MASTER_DIN_SIGNAL FSPID_IN_IDX
#endif
static void inner_connect(spi_bus_config_t bus)
{
//Master MOSI(spid_out) output to `mosi_num`
spitest_gpio_output_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
//Slave MOSI(spid_in) input to `mosi_num`
spitest_gpio_input_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spid_in);
//Master MOSI input(spid_in) to `miso_num`, due to SIO mode, we use Master's `spid_in` to receive data
spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in);
//Slave MISO output(spiq_out)
spitest_gpio_output_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out);
//Force this signal goes through gpio matrix
GPIO.func_in_sel_cfg[MASTER_DIN_SIGNAL].sig_in_sel = 1;
}
TEST_CASE("SPI Single Board Test SIO", "[spi]")
{
@@ -76,7 +59,8 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]")
TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_DISABLED));
same_pin_func_sel(TEST_SPI_HOST, TEST_SLAVE_HOST, bus_cfg, dev_cfg.spics_io_num);
inner_connect(bus_cfg);
// fix sio internal connection
spitest_gpio_input_sel(bus_cfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in);
WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320];
WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320];
@@ -141,185 +125,103 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]")
#endif //#if (TEST_SPI_PERIPH_NUM >= 2)
/********************************************************************************
* Test SIO Master
* SIO Slave is not supported, and one unit test is limited to one feature, so,,,
* sio master test can be split to signal-input and single-output
*
* for single-output: master slave
* cs-----cs ------------- cs
* clk----clk ------------- clk
* d------mosi------------- mosi
* q miso------------- miso
* master can get input on mosi pin after output finish in sio mode, but in this
* case, master can get no data from slave, so check assert on the slave.
*
* ------------------------------------------------------------------------------
* for single-input: master slave
* cs-----cs ------------- cs
* clk----clk ------------- clk
* d-\ mosi------------- mosi
* q \\--miso------------- miso
* In this case, master can get input data from slave after output finish, but
* slave can get no data from master due to internal broke, besides output data
* from both master and slave on miso line will get conflict in master's output
* frame.
* Test SIO Master + SIO Slave HD
********************************************************************************/
#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
#define TRANS_LEN 1024
#define MAX_TRANS_BUFF 64
#define TEST_NUM 8
WORD_ALIGNED_ATTR uint8_t sio_master_rx_buff[TRANS_LEN];
WORD_ALIGNED_ATTR uint8_t sio_slave_rx_buff [TRANS_LEN];
void test_sio_master_trans(bool sio_master_in)
void test_sio_master_trans(void)
{
spi_device_handle_t dev_0;
uint8_t *master_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA);
TEST_ASSERT_NOT_NULL_MESSAGE(master_tx_max, "malloc failed, exit.\n");
// write something to a long buffer for test long transmission
for (uint16_t i = 0; i < TRANS_LEN; i++) {
master_tx_max[i] = i;
master_tx_max[TRANS_LEN * 2 - i - 1] = i;
}
spi_device_handle_t dev;
uint8_t *master_tx = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
uint8_t *master_rx = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
uint8_t *rx_exp = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
TEST_ASSERT_TRUE_MESSAGE(master_tx && master_rx && rx_exp, "malloc failed, exit.\n");
test_fill_random_to_buffers_dualboard(1, master_tx, rx_exp, TRANS_LEN);
spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
if (sio_master_in) {
// normally, spi read data from port Q and write data to port D
// test master input from port D (output default.), so link port D (normally named mosi) to miso pin.
bus_cfg.mosi_io_num = bus_cfg.miso_io_num;
printf("\n====================Test sio master input====================\n");
} else {
printf("\n============Test sio master output, data checked by slave.=============\n");
}
bus_cfg.miso_io_num = -1;
TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO));
spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE;
dev_cfg.clock_speed_hz = 1 * 1000 * 1000;
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &dev_0));
printf("CS:CLK:MO:MI: %d\t%d\t%d\t%d\n", dev_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num, bus_cfg.miso_io_num);
dev_cfg.command_bits = 8;
dev_cfg.address_bits = 8;
dev_cfg.dummy_bits = 8;
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &dev));
printf("CS:CLK:SIO: %d\t%d\t%d\n", dev_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num);
unity_send_signal("Master ready");
for (int i = 0; i < TEST_NUM; i ++) {
spi_transaction_t trans = {};
if (sio_master_in) {
// master input only section
trans.rxlength = (i + 1) * 8 * 8;
// test a huge data for last transmission
if (i >= TEST_NUM - 1) {
trans.rxlength = TRANS_LEN * 8;
}
trans.rx_buffer = sio_master_rx_buff;
trans.length = 0;
trans.tx_buffer = NULL;
memset(sio_master_rx_buff, 0, sizeof(sio_master_rx_buff));
} else {
// master output only section
trans.length = MAX_TRANS_BUFF / (i + 1) * 8;
// test a huge data for last transmission
if (i >= TEST_NUM - 1) {
trans.length = TRANS_LEN * 8;
}
trans.tx_buffer = master_tx_max;
trans.rxlength = 0;
trans.rx_buffer = NULL;
// use some different data
trans.tx_buffer += (i % 2) ? TRANS_LEN : 0;
}
for (int i = TEST_NUM; i > 0; i --) {
size_t trans_len = TRANS_LEN >> i;
//get signal
unity_wait_for_signal("Slave ready");
TEST_ESP_OK(essl_spi_wrdma(dev, master_tx, trans_len, -1, 0));
ESP_LOG_BUFFER_HEXDUMP("master tx", master_tx, trans_len, ESP_LOG_INFO);
TEST_ESP_OK(spi_device_transmit(dev_0, &trans));
if (sio_master_in) {
ESP_LOG_BUFFER_HEXDUMP("master rx", trans.rx_buffer, trans.rxlength / 8, ESP_LOG_INFO);
TEST_ASSERT_EQUAL_HEX8_ARRAY(master_tx_max + i, trans.rx_buffer, trans.rxlength / 8);
} else {
printf("%d master output\n", trans.length / 8);
ESP_LOG_BUFFER_HEXDUMP("master tx", trans.tx_buffer, trans.length / 8, ESP_LOG_INFO);
}
memset(master_rx, 0, trans_len);
TEST_ESP_OK(essl_spi_rddma(dev, master_rx, trans_len, -1, 0));
ESP_LOG_BUFFER_HEXDUMP("master rx", master_rx, trans_len, ESP_LOG_INFO);
TEST_ASSERT_EQUAL_HEX8_ARRAY(rx_exp, master_rx, trans_len);
}
free(master_tx_max);
master_free_device_bus(dev_0);
free(master_tx);
free(master_rx);
free(rx_exp);
master_free_device_bus(dev);
}
void test_sio_slave_emulate(bool sio_master_in)
void test_sio_slave_trans(void)
{
uint8_t *slave_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA);
TEST_ASSERT_NOT_NULL_MESSAGE(slave_tx_max, "malloc failed, exit.\n");
// write something to a long buffer for test long transmission
for (uint16_t i = 0; i < TRANS_LEN; i++) {
slave_tx_max[i] = i;
slave_tx_max[TRANS_LEN * 2 - i - 1] = i;
}
if (sio_master_in) {
printf("\n==================Test sio master input.================\n");
} else {
printf("\n==================Test sio master output.=================\n");
}
spi_slave_hd_data_t *ret_trans;
uint8_t *slave_tx = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
uint8_t *slave_rx = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
uint8_t *rx_exp = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
TEST_ASSERT_TRUE_MESSAGE(slave_tx && slave_rx && rx_exp, "malloc failed, exit.\n");
test_fill_random_to_buffers_dualboard(1, rx_exp, slave_tx, TRANS_LEN);
spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_CH_AUTO));
printf("CS:CLK:MO:MI: %d\t%d\t%d\t%d\n", slv_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num, bus_cfg.miso_io_num);
bus_cfg.miso_io_num = -1;
bus_cfg.max_transfer_sz = TRANS_LEN;
spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG();
slave_hd_cfg.flags = SPI_SLAVE_HD_3WIRE_MODE;
printf("CS:CLK:SIO: %d\t%d\t%d\n", (int)slave_hd_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num);
unity_wait_for_signal("Master ready");
for (int i = 0; i < TEST_NUM; i++) {
spi_slave_transaction_t trans = { .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, };
if (sio_master_in) {
// slave output only section
trans.length = (i + 1) * 8 * 8;
// test a huge data for last transmission
if (i >= TEST_NUM - 1) {
trans.length = TRANS_LEN * 8;
}
trans.tx_buffer = slave_tx_max + i;
trans.rx_buffer = NULL;
} else {
// slave input only section
trans.length = MAX_TRANS_BUFF / (i + 1) * 8;
// test a huge data for last transmission
if (i >= TEST_NUM - 1) {
trans.length = TRANS_LEN * 8;
}
trans.tx_buffer = NULL;
trans.rx_buffer = sio_slave_rx_buff;
memset(sio_slave_rx_buff, 0, sizeof(sio_slave_rx_buff));
}
TEST_ESP_OK(spi_slave_hd_init(TEST_SLAVE_HOST, &bus_cfg, &slave_hd_cfg));
TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &trans, portMAX_DELAY));
for (int i = TEST_NUM; i > 0; i --) {
size_t trans_len = TRANS_LEN >> i;
spi_slave_hd_data_t rx_trans = {
.data = slave_rx,
.len = trans_len,
.flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO,
};
spi_slave_hd_data_t tx_trans = {
.data = slave_tx,
.len = trans_len,
};
memset(slave_rx, 0, trans_len);
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &rx_trans, portMAX_DELAY));
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &tx_trans, portMAX_DELAY));
unity_send_signal("Slave ready");
TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
TEST_ASSERT_EQUAL(&rx_trans, ret_trans);
ESP_LOG_BUFFER_HEXDUMP("Slave rx", rx_trans.data, trans_len, ESP_LOG_INFO);
TEST_ASSERT_EQUAL_HEX8_ARRAY(rx_exp, rx_trans.data, trans_len);
spi_slave_transaction_t *p_slave_ret;
TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &p_slave_ret, portMAX_DELAY));
if (sio_master_in) {
ESP_LOG_BUFFER_HEXDUMP("Slave tx", trans.tx_buffer, trans.length / 8, ESP_LOG_INFO);
} else {
ESP_LOG_BUFFER_HEXDUMP("Slave rx", trans.rx_buffer, trans.length / 8, ESP_LOG_INFO);
TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_tx_max + TRANS_LEN * (i % 2), trans.rx_buffer, trans.length / 8);
}
TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));
TEST_ASSERT_EQUAL(&tx_trans, ret_trans);
ESP_LOG_BUFFER_HEXDUMP("Slave tx", tx_trans.data, trans_len, ESP_LOG_INFO);
}
free(slave_tx_max);
spi_slave_free(TEST_SLAVE_HOST);
free(slave_tx);
free(slave_rx);
free(rx_exp);
spi_slave_hd_deinit(TEST_SLAVE_HOST);
}
void test_master_run(void)
{
test_sio_master_trans(false);
test_sio_master_trans(true);
}
void test_slave_run(void)
{
test_sio_slave_emulate(false);
test_sio_slave_emulate(true);
}
TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test_SIO_Mode_Multi_Board", "[spi_ms][test_env=generic_multi_device]", test_master_run, test_slave_run);
TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test_SIO_Mode_Multi_Board", "[spi_ms][test_env=generic_multi_device]", test_sio_master_trans, test_sio_slave_trans);
#endif // SOC_SPI_SUPPORT_SLAVE_HD_VER2

1
components/esp_hal_gpspi/include/hal/spi_slave_hd_hal.h
View File

@@ -84,6 +84,7 @@ typedef struct {
uint32_t host_id; ///< Host ID of the spi peripheral
bool dma_enabled; ///< DMA enabled or not
bool append_mode; ///< True for DMA append mode, false for segment mode
bool three_wire_mode; ///< True for 3-wire mode, false for 4-wire mode
uint32_t spics_io_num; ///< CS GPIO pin for this device
uint8_t mode; ///< SPI mode (0-3)
uint32_t command_bits; ///< command field bits, multiples of 8 and at least 8.

1
components/esp_hal_gpspi/spi_slave_hd_hal.c
View File

@@ -33,6 +33,7 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h
spi_ll_set_dummy(hw, hal_config->dummy_bits);
spi_ll_set_rx_lsbfirst(hw, hal_config->rx_lsbfirst);
spi_ll_set_tx_lsbfirst(hw, hal_config->tx_lsbfirst);
spi_ll_set_sio_mode(hw, hal_config->three_wire_mode);
spi_ll_slave_set_mode(hw, hal_config->mode, (hal_config->dma_enabled));
spi_ll_disable_intr(hw, UINT32_MAX);

2
components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h
View File

@@ -29,7 +29,7 @@ extern "C" {
#if BUS_LOCK_DEBUG
#define BUS_LOCK_DEBUG_EXECUTE_CHECK(x) assert(x)
#else
#define BUS_LOCK_DEBUG_EXECUTE_CHECK(x)
#define BUS_LOCK_DEBUG_EXECUTE_CHECK(x) (void)(x)
#endif
#define CHECK_IOMUX_PIN(HOST, PIN_NAME) if (GPIO.func_in_sel_cfg[spi_periph_signal[(HOST)].PIN_NAME##_in].sig_in_sel) return false

74
components/esp_hw_support/spi_bus_lock.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -88,12 +88,14 @@
* -> STATE_ACQ: by `acquire_core`
*
* - STATE_BG:
* * No acquiring device, the ISR is the acquiring processor, there is BG bits active, but no LOCK
* bits
* * No acquiring device, the ISR is the acquiring processor, and there are BG bits active. There
* may also be LOCK bits pending for another device, but the lock owner must wait until BG is
* fully finished.
* * The BG operation should be enabled while turning into this state.
*
* -> STATE_IDLE: by `bg_exit_core` after `clear_pend_core` for all BG bits
* -> STATE_BG_ACQ: by `schedule_core`, when there is new LOCK bit set (by `acquire_core`)
* -> STATE_BG_ACQ: by `schedule_core`, when there is a new LOCK bit set (by `acquire_core`) and
* BG is active for the same device
*
* - STATE_BG_ACQ:
* * There is acquiring device, the ISR is the acquiring processor, there may be BG bits active for
@@ -116,9 +118,11 @@
*
* -> STATE_BG_ACQ: by `req_core`
* -> STATE_BG_ACQ (other device): by `acquire_end_core`, when there is LOCK bit for another
* device, and the new acquiring device has active BG bits.
* -> STATE_ACQ (other device): by `acquire_end_core`, when there is LOCK bit for another devices,
* but the new acquiring device has no active BG bits.
* device, and BG is active for the new acquiring device.
* -> STATE_ACQ (other device): by `acquire_end_core`, when there is LOCK bit for another device,
* and no BG bits are active.
* -> STATE_BG: by `acquire_end_core`, when there is LOCK bit for another device, but BG is still
* active for a different device.
* -> STATE_BG: by `acquire_end_core` when there is no LOCK bit active, but there are active BG
* bits.
* -> STATE_IDLE: by `acquire_end_core` when there is no LOCK bit, nor BG bit active.
@@ -389,19 +393,22 @@ SPI_BUS_LOCK_ISR_ATTR static inline bool acquire_core(spi_bus_lock_dev_t *dev_ha
/**
* Find the next acquiring processor according to the status. Will directly change
* the acquiring device if new one found.
* the acquiring device if the BG can yield to the lock owner, or if BG is active for the
* lock owner.
*
* Cases:
* - BG should still be the acquiring processor (Return false):
* 1. Acquiring device has active BG bits: out_desired_dev = new acquiring device
* 2. No acquiring device, but BG active: out_desired_dev = randomly pick one device with active BG bits
* 2. A new acquiring device exists, but BG is still active for another device:
* out_desired_dev = that BG-active device
* 3. No acquiring device, but BG active: out_desired_dev = randomly pick one device with active BG bits
* - BG should yield to the task (Return true):
* 3. Acquiring device has no active BG bits: out_desired_dev = new acquiring device
* 4. No acquiring device while no active BG bits: out_desired_dev=NULL
* 4. Acquiring device has no active BG bits: out_desired_dev = new acquiring device
* 5. No acquiring device while no active BG bits: out_desired_dev=NULL
*
* Acquiring device task need to be resumed only when case 3.
* Acquiring device task needs to be resumed only when case 4.
*
* This scheduling can happen in either task or ISR, so `in_isr` or `bg_active` not touched.
* This scheduling can happen in either task or ISR, so `in_isr` is not touched.
*
* @param lock
* @param status Current status
@@ -420,12 +427,26 @@ schedule_core(spi_bus_lock_t *lock, uint32_t status, spi_bus_lock_dev_t **out_de
bool bg_yield;
if (lock_bits) {
int dev_id = mask_get_id(lock_bits);
desired_dev = (spi_bus_lock_dev_t *)atomic_load(&lock->dev[dev_id]);
BUS_LOCK_DEBUG_EXECUTE_CHECK(desired_dev);
spi_bus_lock_dev_t *lock_dev = (spi_bus_lock_dev_t *)atomic_load(&lock->dev[dev_id]);
BUS_LOCK_DEBUG_EXECUTE_CHECK(lock_dev);
lock->acquiring_dev = desired_dev;
bg_yield = ((bg_bits & desired_dev->mask) == 0);
lock->acq_dev_bg_active = !bg_yield;
if (bg_bits && ((bg_bits & lock_dev->mask) == 0)) {
int bg_dev_id = mask_get_id(bg_bits);
desired_dev = (spi_bus_lock_dev_t *)atomic_load(&lock->dev[bg_dev_id]);
BUS_LOCK_DEBUG_EXECUTE_CHECK(desired_dev);
// Keep ISR/BG owning the bus until the previous device's in-flight
// interrupt transactions are fully finished. The new lock owner will
// be resumed by a later schedule once BG bits are cleared.
lock->acquiring_dev = NULL;
lock->acq_dev_bg_active = false;
bg_yield = false;
} else {
desired_dev = lock_dev;
lock->acquiring_dev = desired_dev;
bg_yield = ((bg_bits & desired_dev->mask) == 0);
lock->acq_dev_bg_active = !bg_yield;
}
} else {
lock->acq_dev_bg_active = false;
if (bg_bits) {
@@ -533,7 +554,7 @@ SPI_BUS_LOCK_ISR_ATTR static inline bool bg_entry_core(spi_bus_lock_t *lock)
// Handle the conditions of status and interrupt, avoiding the ISR being disabled when there is any new coming BG requests.
// When called with `wip=true`, means the ISR is performing some operations. Will enable the interrupt again and exit unconditionally.
// When called with `wip=false`, will only return `true` when there is no coming BG request. If return value is `false`, the ISR should try again.
// Will not change acquiring device.
// May change acquiring device when BG has finished and there is a pending LOCK bit.
SPI_BUS_LOCK_ISR_ATTR static inline bool bg_exit_core(spi_bus_lock_t *lock, bool wip, BaseType_t *do_yield)
{
//See comments in `bg_entry_core`, re-enable interrupt disabled in entry if we do need the interrupt
@@ -557,7 +578,20 @@ SPI_BUS_LOCK_ISR_ATTR static inline bool bg_exit_core(spi_bus_lock_t *lock, bool
}
} else {
BUS_LOCK_DEBUG_EXECUTE_CHECK(!lock->acq_dev_bg_active);
ret = !(status & BG_MASK);
if (status & BG_MASK) {
ret = false;
} else if (status & LOCK_MASK) {
spi_bus_lock_dev_t *desired_dev = NULL;
bool bg_yield = schedule_core(lock, status, &desired_dev);
// A waiting lock owner must be selected once BG is fully finished.
BUS_LOCK_DEBUG_EXECUTE_CHECK(bg_yield);
BUS_LOCK_DEBUG_EXECUTE_CHECK(desired_dev);
BUS_LOCK_DEBUG_EXECUTE_CHECK(lock->acquiring_dev == desired_dev);
resume_dev_in_isr(lock->acquiring_dev, do_yield);
ret = true;
} else {
ret = true;
}
}
if (ret) {
//when successfully exit, but no transaction done, mark BG as inactive

61
components/esp_lcd/test_apps/spi_lcd/main/test_spi_lcd_panel.c
View File

@@ -297,3 +297,64 @@ TEST_CASE("spi_lcd_send_colors_to_fixed_region", "[lcd]")
TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST_ID));
free(color_data);
}
#define TEST_SPI_LCD_CONCURRENT_COLOR_LEN (120 * 120)
typedef struct {
spi_device_handle_t spi_dev;
TaskHandle_t done_task;
volatile bool stop;
uint32_t trans_count;
} spi_lcd_concurrent_polling_ctx_t;
static void spi_lcd_concurrent_polling_task(void *arg)
{
spi_lcd_concurrent_polling_ctx_t *ctx = arg;
spi_transaction_t trans = {
.length = 4 * 8,
.flags = SPI_TRANS_USE_TXDATA,
};
while (!ctx->stop) {
vTaskDelay(pdMS_TO_TICKS(50));
TEST_ESP_OK(spi_device_polling_transmit(ctx->spi_dev, &trans));
ctx->trans_count++;
}
xTaskNotifyGive(ctx->done_task);
vTaskDelete(NULL);
}
TEST_CASE("spi_lcd_safe_with_another_device_polling_on_same_bus", "[lcd]")
{
void *color_data = malloc(TEST_SPI_LCD_CONCURRENT_COLOR_LEN);
TEST_ASSERT_NOT_NULL(color_data);
esp_lcd_panel_io_handle_t io_handle = NULL;
test_spi_lcd_common_initialize(&io_handle, NULL, NULL, 8, 8, false);
spi_lcd_concurrent_polling_ctx_t polling_ctx = { .done_task = xTaskGetCurrentTaskHandle() };
spi_device_interface_config_t other_dev_config = {
.clock_speed_hz = TEST_LCD_PIXEL_CLOCK_HZ,
.spics_io_num = -1,
.queue_size = 1,
};
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST_ID, &other_dev_config, &polling_ctx.spi_dev));
// polling task with higher priority than the interrupt task
xTaskCreate(spi_lcd_concurrent_polling_task, "spi_polling", 4096, &polling_ctx, 10, NULL);
for (int i = 0; i < 30; i++) {
printf("panel_io_tx_color %d\r\n", i);
TEST_ESP_OK(esp_lcd_panel_io_tx_color(io_handle, -1, color_data, TEST_SPI_LCD_CONCURRENT_COLOR_LEN));
}
polling_ctx.stop = true;
vTaskDelay(pdMS_TO_TICKS(100)); // wait for polling task to stop
TEST_ASSERT_GREATER_THAN(0, (int)ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(5000)));
TEST_ASSERT_GREATER_THAN_UINT32(0, polling_ctx.trans_count);
TEST_ESP_OK(esp_lcd_panel_io_del(io_handle));
TEST_ESP_OK(spi_bus_remove_device(polling_ctx.spi_dev));
TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST_ID));
TEST_ESP_OK(gpio_reset_pin(TEST_LCD_BK_LIGHT_GPIO));
free(color_data);
}

2
docs/en/api-reference/peripherals/spi_slave_hd.rst
View File

@@ -48,6 +48,8 @@ Call :cpp:func:`spi_slave_hd_init` to initialize the SPI bus as well as the peri
The :cpp:type:`spi_bus_config_t` specifies how the bus should be initialized, while :cpp:type:`spi_slave_hd_slot_config_t` specifies how the SPI Slave driver should work.
To use 3-wire mode, also known as single I/O (SIO) mode, set :c:macro:`SPI_SLAVE_HD_3WIRE_MODE` in :cpp:member:`spi_slave_hd_slot_config_t::flags`. In this mode, MOSI is used for both input and output data, so :cpp:member:`spi_bus_config_t::mosi_io_num` must be set to an output-capable GPIO. The MISO line is not used and :cpp:member:`spi_bus_config_t::miso_io_num` can be set to ``-1``. The master should use the 1-bit SPI Slave HD commands in this mode. Commands with DIO/QIO masks will select 2-line or 4-line data phases in hardware and are not compatible with 3-wire mode, resulting in data errors.
Enable/Disable Driver (Optional)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

2
docs/zh_CN/api-reference/peripherals/spi_slave_hd.rst
View File

@@ -48,6 +48,8 @@ SPI 从机半双工模式
结构体 :cpp:type:`spi_bus_config_t` 指定了总线的初始化方式，结构体 :cpp:type:`spi_slave_hd_slot_config_t` 指定了 SPI 从机驱动程序的运行方式。
如需使用 3-wire 模式，也称 single I/O (SIO) 模式，请在 :cpp:member:`spi_slave_hd_slot_config_t::flags` 中设置 :c:macro:`SPI_SLAVE_HD_3WIRE_MODE`。该模式下，MOSI 同时用于输入和输出数据，因此 :cpp:member:`spi_bus_config_t::mosi_io_num` 必须设置为支持输出的 GPIO。MISO 信号线不会使用，:cpp:member:`spi_bus_config_t::miso_io_num` 可以设置为 ``-1``。在该模式下，主设备应使用 1-bit SPI Slave HD 命令。带有 DIO/QIO 等 mask 的命令会使硬件选择 2 线或 4 线数据阶段，与 3-wire 模式不兼容，导致数据出错。
启用/禁用从机驱动（可选）
^^^^^^^^^^^^^^^^^^^^^^^^^