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Merge branch 'fix/esp32s31_missing_file' into 'master'

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fix(esp32s31): Add some missing rom file for esp32s31

See merge request espressif/esp-idf!46246
This commit is contained in:
C.S.M
2026-03-04 13:59:19 +08:00
parent efbe83bd21 587986c84b
commit da4584f913
5 changed files with 1015 additions and 0 deletions
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components/esp_rom/esp32s31/include/esp32s31/rom/tjpgd.h
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*----------------------------------------------------------------------------/
/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012
/----------------------------------------------------------------------------*/
#ifndef _TJPGDEC
#define _TJPGDEC
/*---------------------------------------------------------------------------*/
/* System Configurations */
#define JD_SZBUF 512 /* Size of stream input buffer */
#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
#define JD_USE_SCALE 1 /* Use descaling feature for output */
#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
/*---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
/* These types must be 16-bit, 32-bit or larger integer */
typedef int INT;
typedef unsigned int UINT;
/* These types must be 8-bit integer */
typedef char CHAR;
typedef unsigned char UCHAR;
typedef unsigned char BYTE;
/* These types must be 16-bit integer */
typedef short SHORT;
typedef unsigned short USHORT;
typedef unsigned short WORD;
typedef unsigned short WCHAR;
/* These types must be 32-bit integer */
typedef long LONG;
typedef unsigned long ULONG;
typedef unsigned long DWORD;
/* Error code */
typedef enum {
JDR_OK = 0, /* 0: Succeeded */
JDR_INTR, /* 1: Interrupted by output function */
JDR_INP, /* 2: Device error or wrong termination of input stream */
JDR_MEM1, /* 3: Insufficient memory pool for the image */
JDR_MEM2, /* 4: Insufficient stream input buffer */
JDR_PAR, /* 5: Parameter error */
JDR_FMT1, /* 6: Data format error (may be damaged data) */
JDR_FMT2, /* 7: Right format but not supported */
JDR_FMT3 /* 8: Not supported JPEG standard */
} JRESULT;
/* Rectangular structure */
typedef struct {
WORD left, right, top, bottom;
} JRECT;
/* Decompressor object structure */
typedef struct JDEC JDEC;
struct JDEC {
UINT dctr; /* Number of bytes available in the input buffer */
BYTE *dptr; /* Current data read ptr */
BYTE *inbuf; /* Bit stream input buffer */
BYTE dmsk; /* Current bit in the current read byte */
BYTE scale; /* Output scaling ratio */
BYTE msx, msy; /* MCU size in unit of block (width, height) */
BYTE qtid[3]; /* Quantization table ID of each component */
SHORT dcv[3]; /* Previous DC element of each component */
WORD nrst; /* Restart interval */
UINT width, height; /* Size of the input image (pixel) */
BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */
WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */
BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */
LONG *qttbl[4]; /* Dequaitizer tables [id] */
void *workbuf; /* Working buffer for IDCT and RGB output */
BYTE *mcubuf; /* Working buffer for the MCU */
void *pool; /* Pointer to available memory pool */
UINT sz_pool; /* Size of memory pool (bytes available) */
UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */
void *device; /* Pointer to I/O device identifier for the session */
};
/* TJpgDec API functions */
JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *);
JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE);
#ifdef __cplusplus
}
#endif
#endif /* _TJPGDEC */
components/esp_rom/esp32s31/ld/esp32s31.rom.coexist.ld
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32s31.rom.coexist.ld for esp32s31
*
*
* Generated from ../../rom/target/esp32s31/interface-esp32s31.yml md5sum 0cb775308c66eebf0757e406021ad5be
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group rom_coexist
***************************************/
/* Functions */
esp_coex_rom_version_get = 0x2f800bf0;
coex_bt_release = 0x2f800bf4;
coex_bt_request = 0x2f800bf8;
coex_core_ble_conn_dyn_prio_get = 0x2f800bfc;
coex_core_event_duration_get = 0x2f800c00;
coex_core_pti_get = 0x2f800c04;
coex_core_release = 0x2f800c08;
coex_core_request = 0x2f800c0c;
coex_core_status_get = 0x2f800c10;
coex_core_timer_idx_get = 0x2f800c14;
coex_event_duration_get = 0x2f800c18;
coex_hw_timer_disable = 0x2f800c1c;
coex_hw_timer_enable = 0x2f800c20;
coex_hw_timer_set = 0x2f800c24;
coex_schm_interval_set = 0x2f800c28;
coex_schm_lock = 0x2f800c2c;
coex_schm_unlock = 0x2f800c30;
coex_status_get = 0x2f800c34;
coex_wifi_release = 0x2f800c38;
esp_coex_ble_conn_dynamic_prio_get = 0x2f800c3c;
/* Data (.data, .bss, .rodata) */
coex_env_ptr = 0x2f07ffa8;
coex_pti_tab_ptr = 0x2f07ffa4;
coex_schm_env_ptr = 0x2f07ffa0;
coexist_funcs = 0x2f07ff9c;
g_coa_funcs_p = 0x2f07ff98;
g_coex_param_ptr = 0x2f07ff94;
components/esp_rom/esp32s31/ld/esp32s31.rom.net80211.ld
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32s31.rom.net80211.ld for esp32s31
*
*
* Generated from ../../rom/target/esp32s31/interface-esp32s31.yml md5sum 0cb775308c66eebf0757e406021ad5be
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group rom_net80211
***************************************/
/* Functions */
esp_net80211_rom_version_get = 0x2f800c40;
esp_wifi_internal_tx = 0x2f800c44;
ampdu_dispatch = 0x2f800c48;
ampdu_dispatch_all = 0x2f800c4c;
ampdu_dispatch_as_many_as_possible = 0x2f800c50;
ampdu_dispatch_movement = 0x2f800c54;
ampdu_dispatch_upto = 0x2f800c58;
chm_is_at_home_channel = 0x2f800c5c;
cnx_node_is_existing = 0x2f800c60;
cnx_node_search = 0x2f800c64;
ic_ebuf_recycle_rx = 0x2f800c68;
ic_ebuf_recycle_tx = 0x2f800c6c;
ic_reset_rx_ba = 0x2f800c70;
ic_ebuf_alloc = 0x2f800c74;
ic_reset_extra_softap_rx_ba = 0x2f800c78;
ieee80211_align_eb = 0x2f800c7c;
ieee80211_ampdu_reorder = 0x2f800c80;
ieee80211_ampdu_start_age_timer = 0x2f800c84;
ieee80211_encap_esfbuf = 0x2f800c88;
ieee80211_is_tx_allowed = 0x2f800c8c;
ieee80211_output_pending_eb = 0x2f800c90;
ieee80211_output_process = 0x2f800c94;
ieee80211_set_tx_desc = 0x2f800c98;
ieee80211_classify = 0x2f800c9c;
ieee80211_copy_eb_header = 0x2f800ca0;
ieee80211_recycle_cache_eb = 0x2f800ca4;
ieee80211_search_node = 0x2f800ca8;
ieee80211_crypto_encap = 0x2f800cac;
ieee80211_crypto_decap = 0x2f800cb0;
ieee80211_decap = 0x2f800cb4;
ieee80211_set_tx_pti = 0x2f800cb8;
ieee80211_gettid = 0x2f800cbc;
ieee80211_post_hmac_tx = 0x2f800cc0;
ieee80211_alloc_tx_buf = 0x2f800cc4;
ieee80211_output_do = 0x2f800cc8;
ieee80211_find_elem_match = 0x2f800ccc;
ieee80211_find_ie_match = 0x2f800cd0;
ieee80211_find_elem = 0x2f800cd4;
ieee80211_find_ext_elem = 0x2f800cd8;
ieee80211_find_ie = 0x2f800cdc;
ieee80211_find_ext_ie = 0x2f800ce0;
ieee80211_merge_mbssid_profile = 0x2f800ce4;
ieee80211_encap_esfbuf_htc = 0x2f800ce8;
wifi_get_macaddr = 0x2f800cec;
wifi_rf_phy_disable = 0x2f800cf0;
wifi_rf_phy_enable = 0x2f800cf4;
wifi_is_started = 0x2f800cf8;
sta_input = 0x2f800cfc;
sta_rx_eapol = 0x2f800d00;
sta_reset_beacon_timeout = 0x2f800d04;
sta_get_beacon_timeout = 0x2f800d08;
ampdu_process_multicast_address_qos_frame = 0x2f800d0c;
/* Data (.data, .bss, .rodata) */
net80211_funcs = 0x2f07ff90;
g_scan = 0x2f07ff8c;
g_chm = 0x2f07ff88;
g_ic_ptr = 0x2f07ff84;
g_hmac_cnt_ptr = 0x2f07ff80;
g_tx_cacheq_ptr = 0x2f07ff7c;
s_netstack_free = 0x2f07ff78;
s_encap_amsdu_func = 0x2f07ff74;
mesh_rxcb = 0x2f07ff70;
sta_rxcb = 0x2f07ff6c;
s_netstack_ref = 0x2f07ff68;
g_sta_connected_flag = 0x2f07ff65;
g_itwt_fid = 0x2f07ff64;
g_misc_nvs = 0x2f07ff60;
esp_test_dump_htc = 0x2f07ff5c;
components/esp_rom/esp32s31/ld/esp32s31.rom.phy.ld
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32s31.rom.phy.ld for esp32s31
*
*
* Generated from ../../rom/target/esp32s31/interface-esp32s31.yml md5sum 0cb775308c66eebf0757e406021ad5be
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group rom_phy
***************************************/
/* Functions */
chip764_phyrom_version = 0x2f8011f0;
chip764_phyrom_version_num = 0x2f8011f4;
phy_param_addr = 0x2f8011f8;
phy_get_romfuncs = 0x2f8011fc;
phy_rate_to_index = 0x2f801200;
phy_get_target_pwr = 0x2f801204;
phy_get_max_pwr = 0x2f801208;
phy_get_pwr_index = 0x2f80120c;
phy_get_rc_dout = 0x2f801210;
phy_rc_cal = 0x2f801214;
phy_abs_temp = 0x2f801218;
phy_get_data_sat = 0x2f80121c;
phy_byte_to_word = 0x2f801220;
phy_bb_bss_cbw40 = 0x2f801224;
phy_set_chan_reg = 0x2f801228;
phy_i2c_master_reset = 0x2f80122c;
phy_chan14_mic_enable = 0x2f801230;
phy_chan14_mic_cfg = 0x2f801234;
phy_set_most_tpw = 0x2f801238;
phy_get_most_tpw = 0x2f80123c;
phy_tx_state_out = 0x2f801240;
phy_ant_dft_cfg = 0x2f801244;
phy_ant_wifitx_cfg = 0x2f801248;
phy_ant_wifirx_cfg = 0x2f80124c;
phy_ant_bttx_cfg = 0x2f801250;
phy_ant_btrx_cfg = 0x2f801254;
phy_chan_dump_cfg = 0x2f801258;
phy_enable_low_rate = 0x2f80125c;
phy_disable_low_rate = 0x2f801260;
phy_is_low_rate_enabled = 0x2f801264;
phy_dig_reg_backup = 0x2f801268;
phy_chan_filt_set = 0x2f80126c;
phy_rx11blr_cfg = 0x2f801270;
phy_set_cca = 0x2f801274;
phy_set_rx_sense = 0x2f801278;
phy_freq_module_resetn = 0x2f80127c;
phy_freq_chan_en_sw = 0x2f801280;
phy_write_chan_freq = 0x2f801284;
phy_get_freq_mem_param = 0x2f801288;
phy_get_freq_mem_addr = 0x2f80128c;
phy_read_rf_freq_mem = 0x2f801290;
phy_freq_i2c_mem_write = 0x2f801294;
phy_freq_num_get_data = 0x2f801298;
phy_freq_i2c_num_addr = 0x2f80129c;
phy_freq_i2c_write_set = 0x2f8012a0;
phy_pll_cap_mem_update = 0x2f8012a4;
phy_en_hw_set_freq = 0x2f8012a8;
phy_dis_hw_set_freq = 0x2f8012ac;
phy_wait_freq_set_busy = 0x2f8012b0;
phy_i2c_enter_critical_ = 0x2f8012b4;
phy_i2c_exit_critical_ = 0x2f8012b8;
phy_i2c_clk_sel = 0x2f8012bc;
phy_get_i2c_read_mask_ = 0x2f8012c0;
phy_get_i2c_mst0_mask = 0x2f8012c4;
phy_get_i2c_hostid_ = 0x2f8012c8;
phy_chip_i2c_readReg_org = 0x2f8012cc;
phy_chip_i2c_readReg = 0x2f8012d0;
phy_i2c_paral_set_mst0 = 0x2f8012d4;
phy_i2c_paral_set_read = 0x2f8012d8;
phy_i2c_paral_read = 0x2f8012dc;
phy_i2c_paral_write = 0x2f8012e0;
phy_i2c_paral_write_num = 0x2f8012e4;
phy_i2c_paral_write_mask = 0x2f8012e8;
phy_i2c_readReg = 0x2f8012ec;
phy_chip_i2c_writeReg = 0x2f8012f0;
phy_i2c_writeReg = 0x2f8012f4;
phy_i2c_readReg_Mask = 0x2f8012f8;
phy_set_txcap_reg = 0x2f8012fc;
phy_i2c_sar2_init_code = 0x2f801300;
phy_filter_dcap_set = 0x2f801304;
phy_i2c_rc_cal_set = 0x2f801308;
phy_adc_rate_set = 0x2f80130c;
phy_dac_rate_set = 0x2f801310;
phy_encode_i2c_master = 0x2f801314;
phy_i2c_master_fill = 0x2f801318;
phy_open_fe_bb_clk = 0x2f80131c;
phy_get_mac_addr = 0x2f801320;
phy_set_mac_data = 0x2f801324;
phy_rfcal_data_sub = 0x2f801328;
phy_rf_cal_data_recovery = 0x2f80132c;
phy_rf_cal_data_backup = 0x2f801330;
phy_rfcal_data_check = 0x2f801334;
phy_pbus_force_mode = 0x2f801338;
phy_pbus_force_test = 0x2f80133c;
phy_pbus_rd = 0x2f801340;
phy_pbus_debugmode = 0x2f801344;
phy_pbus_workmode = 0x2f801348;
phy_pbus_clear_reg = 0x2f80134c;
phy_pbus_set_rxgain = 0x2f801350;
phy_pbus_set_dco = 0x2f801354;
phy_set_loopback_gain = 0x2f801358;
phy_txcal_debuge_mode_ = 0x2f80135c;
phy_txcal_work_mode = 0x2f801360;
phy_write_pbus_mem = 0x2f801364;
phy_set_pbus_mem = 0x2f801368;
phy_pwdet_reg_init = 0x2f80136c;
phy_pwdet_sar2_init = 0x2f801370;
phy_en_pwdet = 0x2f801374;
phy_get_sar_sig_ref = 0x2f801378;
phy_pwdet_tone_start = 0x2f80137c;
phy_get_fm_sar_dout = 0x2f801380;
phy_txtone_linear_pwr = 0x2f801384;
phy_linear_to_db = 0x2f801388;
phy_get_power_db = 0x2f80138c;
phy_meas_tone_pwr_db = 0x2f801390;
phy_pwdet_wait_idle = 0x2f801394;
phy_pkdet_vol_start = 0x2f801398;
phy_read_sar_dout = 0x2f80139c;
phy_read_sar2_code = 0x2f8013a0;
phy_get_sar2_vol = 0x2f8013a4;
phy_disable_agc = 0x2f8013a8;
phy_enable_agc = 0x2f8013ac;
phy_disable_cca = 0x2f8013b0;
phy_enable_cca = 0x2f8013b4;
phy_write_gain_mem = 0x2f8013b8;
phy_bb_bss_cbw40_dig = 0x2f8013bc;
phy_tx_paon_set = 0x2f8013c0;
phy_i2cmst_reg_init = 0x2f8013c4;
phy_bt_gain_offset = 0x2f8013c8;
phy_fe_reg_init = 0x2f8013cc;
phy_mac_enable_bb = 0x2f8013d0;
phy_bb_wdg_cfg = 0x2f8013d4;
phy_fe_txrx_reset = 0x2f8013d8;
phy_set_rx_comp_ = 0x2f8013dc;
phy_agc_reg_init = 0x2f8013e0;
phy_bb_reg_init = 0x2f8013e4;
phy_open_i2c_xpd = 0x2f8013e8;
phy_force_txrx_off = 0x2f8013ec;
phy_txiq_set_reg = 0x2f8013f0;
phy_rxiq_set_reg = 0x2f8013f4;
phy_rx_gain_force = 0x2f8013f8;
phy_set_txclk_en = 0x2f8013fc;
phy_set_rxclk_en = 0x2f801400;
phy_start_tx_tone_step = 0x2f801404;
phy_stop_tx_tone = 0x2f801408;
phy_bb_wdg_test_en = 0x2f80140c;
phy_noise_floor_auto_set = 0x2f801410;
phy_read_hw_noisefloor = 0x2f801414;
phy_iq_corr_enable = 0x2f801418;
phy_wifi_agc_sat_gain = 0x2f80141c;
phy_bbpll_cal = 0x2f801420;
phy_ant_init = 0x2f801424;
phy_wifi_fbw_sel = 0x2f801428;
phy_bt_filter_reg = 0x2f80142c;
phy_rx_sense_set = 0x2f801430;
phy_tx_state_set = 0x2f801434;
phy_close_pa = 0x2f801438;
phy_freq_correct = 0x2f80143c;
phy_set_pbus_reg = 0x2f801440;
phy_wifi_rifs_mode_en = 0x2f801444;
phy_nrx_freq_set = 0x2f801448;
phy_fe_adc_on = 0x2f80144c;
phy_force_pwr_index = 0x2f801450;
phy_fft_scale_force = 0x2f801454;
phy_force_rx_gain = 0x2f801458;
phy_wifi_enable_set = 0x2f80145c;
phy_bb_cbw_chan_cfg = 0x2f801460;
phy_vht_support = 0x2f801464;
phy_csidump_force_lltf_cfg = 0x2f801468;
phy_hemu_ru26_good_res = 0x2f80146c;
phy_bb_cfo_cfg = 0x2f801470;
phy_freq_band_reg_set = 0x2f801474;
phy_set_bb_wdg = 0x2f801478;
phy_sifs_reg_init = 0x2f80147c;
phy_bbtx_outfilter = 0x2f801480;
phy_bb_wdt_rst_enable = 0x2f801484;
phy_bb_wdt_int_enable = 0x2f801488;
phy_bb_wdt_timeout_clear = 0x2f80148c;
phy_bb_wdt_get_status = 0x2f801490;
phy_chan_to_freq = 0x2f801494;
phy_iq_est_enable = 0x2f801498;
phy_iq_est_disable = 0x2f80149c;
phy_dc_iq_est = 0x2f8014a0;
phy_set_cal_rxdc = 0x2f8014a4;
phy_rxiq_get_mis = 0x2f8014a8;
phy_rxiq_cover_mg_mp = 0x2f8014ac;
phy_rfcal_rxiq = 0x2f8014b0;
phy_get_rfcal_rxiq_data = 0x2f8014b4;
phy_get_dco_comp = 0x2f8014b8;
phy_pbus_rx_dco_cal = 0x2f8014bc;
phy_rxdc_est_min = 0x2f8014c0;
phy_set_lb_txiq = 0x2f8014c4;
phy_set_rx_gain_cal_iq = 0x2f8014c8;
phy_set_rx_gain_cal_dc = 0x2f8014cc;
phy_spur_cal = 0x2f8014d0;
phy_spur_coef_cfg = 0x2f8014d4;
phy_bb_gain_index = 0x2f8014d8;
phy_rfrx_gain_index = 0x2f8014dc;
phy_gen_rx_gain_table = 0x2f8014e0;
phy_get_rxbb_dc = 0x2f8014e4;
phy_wr_rx_gain_mem = 0x2f8014e8;
phy_set_tsens_power_ = 0x2f8014ec;
phy_get_tsens_value_ = 0x2f8014f0;
phy_code_to_temp = 0x2f8014f4;
phy_tsens_dac_to_index = 0x2f8014f8;
phy_tsens_dac_cal = 0x2f8014fc;
phy_tsens_code_read = 0x2f801500;
phy_tsens_temp_read = 0x2f801504;
phy_tsens_temp_read_local = 0x2f801508;
phy_bt_txdc_cal = 0x2f80150c;
phy_bt_txiq_cal = 0x2f801510;
phy_txdc_cal = 0x2f801514;
phy_txdc_cal_pwdet = 0x2f801518;
phy_txiq_get_mis_pwr = 0x2f80151c;
phy_txiq_cover = 0x2f801520;
phy_rfcal_txiq = 0x2f801524;
phy_get_power_atten = 0x2f801528;
phy_pwdet_ref_code = 0x2f80152c;
phy_pwdet_code_cal = 0x2f801530;
phy_rfcal_txcap = 0x2f801534;
phy_rfcal_pwrctrl = 0x2f801538;
phy_tx_pwctrl_init_cal = 0x2f80153c;
phy_txbbgain_to_index = 0x2f801540;
phy_index_to_txbbgain = 0x2f801544;
phy_bt_get_tx_gain = 0x2f801548;
phy_dig_gain_check = 0x2f80154c;
phy_wifi_get_tx_gain = 0x2f801550;
phy_wifi_11g_rate_chg = 0x2f801554;
phy_set_tx_gain_mem = 0x2f801558;
phy_get_rate_fcc_index = 0x2f80155c;
phy_get_chan_target_power = 0x2f801560;
phy_get_tx_gain_value = 0x2f801564;
phy_wifi_get_target_power = 0x2f801568;
phy_wifi_get_tx_tab_ = 0x2f80156c;
phy_wifi_set_tx_gain = 0x2f801570;
phy_bt_get_tx_tab_ = 0x2f801574;
phy_bt_set_tx_gain = 0x2f801578;
phy_bb_agc_reg_update = 0x2f80157c;
phy_bb_dcmem_clr = 0x2f801580;
phy_bbpll_recal = 0x2f801584;
phy_bt_bb_to_index = 0x2f801588;
phy_bt_index_to_bb = 0x2f80158c;
phy_bt_track_tx_power = 0x2f801590;
phy_btbb_wifi_bb_cfg2 = 0x2f801594;
phy_chip_set_chan_ana = 0x2f801598;
phy_chip_set_chan_misc = 0x2f80159c;
phy_dac_scale_set = 0x2f8015a0;
phy_dcode_cal_init = 0x2f8015a4;
phy_fe_reg_update = 0x2f8015a8;
phy_force_rx_gain_trig = 0x2f8015ac;
phy_freq_reg_init = 0x2f8015b0;
phy_freq_set_reg = 0x2f8015b4;
phy_get_cca = 0x2f8015b8;
phy_get_cca_cnt = 0x2f8015bc;
phy_get_dreg1p6 = 0x2f8015c0;
phy_get_iq_value = 0x2f8015c4;
phy_get_noise_floor = 0x2f8015c8;
phy_get_oc_dr1 = 0x2f8015cc;
phy_get_pll_vol = 0x2f8015d0;
phy_get_rssi = 0x2f8015d4;
phy_get_rx_sig_pwr = 0x2f8015d8;
phy_get_tone_sar_dout_ = 0x2f8015dc;
phy_get_txiq_set = 0x2f8015e0;
phy_i2c_bbpll_set = 0x2f8015e4;
phy_i2c_master_mem_txcap = 0x2f8015e8;
phy_i2c_txrate_init = 0x2f8015ec;
phy_i2c_writeReg_Mask = 0x2f8015f0;
phy_lltf_mask_en = 0x2f8015f4;
phy_loopback_mode_en = 0x2f8015f8;
phy_mac_tx_chan_offset = 0x2f8015fc;
phy_mhz2ieee = 0x2f801600;
phy_pbus_rd_addr = 0x2f801604;
phy_pbus_rd_shift = 0x2f801608;
phy_pbus_rx_dco_cal_1step = 0x2f80160c;
phy_pbus_xpd_rx_off = 0x2f801610;
phy_pbus_xpd_rx_on = 0x2f801614;
phy_pbus_xpd_tx_off = 0x2f801618;
phy_pbus_xpd_tx_on = 0x2f80161c;
phy_pll_dac_mem_update = 0x2f801620;
phy_read_pll_cap = 0x2f801624;
phy_reg_init = 0x2f801628;
phy_reset_ckgen = 0x2f80162c;
phy_restart_cal = 0x2f801630;
phy_rfpll_cap_correct = 0x2f801634;
phy_rfpll_cap_init_cal = 0x2f801638;
phy_rfpll_cap_track = 0x2f80163c;
phy_rfpll_chgp_cal = 0x2f801640;
phy_rfpll_set_freq = 0x2f801644;
phy_rfrx_sat_rst = 0x2f801648;
phy_rx_11b_opt = 0x2f80164c;
phy_rx_filter_mode = 0x2f801650;
phy_save_pbus_reg = 0x2f801654;
phy_set_cca_cnt = 0x2f801658;
phy_set_chan_cal_interp = 0x2f80165c;
phy_set_chan_freq_sw_start = 0x2f801660;
phy_set_channel_dcode = 0x2f801664;
phy_set_channel_rfpll_freq = 0x2f801668;
phy_set_ext_dcode = 0x2f80166c;
phy_set_freq = 0x2f801670;
phy_set_rf_freq_offset = 0x2f801674;
phy_set_rfpll_freq = 0x2f801678;
phy_set_tsens_range_ = 0x2f80167c;
phy_set_txcap_reset = 0x2f801680;
phy_spur_reg_write_one_tone = 0x2f801684;
phy_temp_to_power = 0x2f801688;
phy_tx_pwctrl_bg_init = 0x2f80168c;
phy_txgain_comp_pacfg_ = 0x2f801690;
phy_txpwr_cal_track = 0x2f801694;
phy_txpwr_correct = 0x2f801698;
phy_txpwr_track_slow = 0x2f80169c;
phy_wait_i2c_sdm_stable = 0x2f8016a0;
phy_wait_rfpll_cal_end = 0x2f8016a4;
phy_wifi_track_tx_power = 0x2f8016a8;
phy_wr_rf_freq_mem = 0x2f8016ac;
phy_write_pll_cap = 0x2f8016b0;
phy_write_rfpll_sdm = 0x2f8016b4;
phy_xpd_rf = 0x2f8016b8;
/* Data (.data, .bss, .rodata) */
rom_phyFuns = 0x2f07fc3c;
phy_param_rom = 0x2f07fc40;
components/esp_rom/esp32s31/ld/esp32s31.rom.pp.ld
+448
View File
@@ -0,0 +1,448 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32s31.rom.pp.ld for esp32s31
*
*
* Generated from ../../rom/target/esp32s31/interface-esp32s31.yml md5sum 0cb775308c66eebf0757e406021ad5be
*
* Compatible with ROM where ECO version equal or greater to 0.
*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*/
/***************************************
Group rom_pp
***************************************/
/* Functions */
esp_pp_rom_version_get = 0x2f800d10;
RC_GetBlockAckTime = 0x2f800d14;
ebuf_list_remove = 0x2f800d18;
esf_buf_alloc = 0x2f800d1c;
esf_buf_alloc_dynamic = 0x2f800d20;
esf_buf_recycle = 0x2f800d24;
GetAccess = 0x2f800d28;
hal_mac_is_low_rate_enabled = 0x2f800d2c;
hal_mac_tx_get_blockack = 0x2f800d30;
hal_mac_tx_set_ppdu = 0x2f800d34;
hal_mac_tx_clr_mplen = 0x2f800d38;
hal_mac_get_txq_state = 0x2f800d3c;
hal_mac_clr_txq_state = 0x2f800d40;
hal_mac_get_txq_complete = 0x2f800d44;
hal_mac_deinit_twt_tx = 0x2f800d48;
hal_mac_is_dma_enable = 0x2f800d4c;
hal_he_get_bss_color = 0x2f800d50;
hal_he_set_ersu = 0x2f800d54;
hal_he_get_mplen_addr_start = 0x2f800d58;
hal_he_get_mplen_addr_end = 0x2f800d5c;
hal_he_set_bf_report_rate = 0x2f800d60;
hal_he_set_ersu_ack_rate = 0x2f800d64;
hal_he_get_aid = 0x2f800d68;
hal_random = 0x2f800d6c;
hal_enable_tx_statistics = 0x2f800d70;
hal_enable_rx_statistics = 0x2f800d74;
hal_enable_tsf_timer = 0x2f800d78;
hal_wdev_timer_target_enable = 0x2f800d7c;
hal_wdev_timer_set_target = 0x2f800d80;
hal_tsf_timer_set_target = 0x2f800d84;
hal_tsf_clear_soc_wakeup_request = 0x2f800d88;
hal_get_tsf_time = 0x2f800d8c;
hal_get_sta_tsf = 0x2f800d90;
ic_get_trc = 0x2f800d94;
ic_mac_deinit = 0x2f800d98;
ic_mac_init = 0x2f800d9c;
ic_interface_enabled = 0x2f800da0;
is_lmac_idle = 0x2f800da4;
ic_get_he_rts_threshold_bytes = 0x2f800da8;
lmacAdjustTimestamp = 0x2f800dac;
lmacDiscardAgedMSDU = 0x2f800db0;
lmacDiscardMSDU = 0x2f800db4;
lmacEndFrameExchangeSequence = 0x2f800db8;
lmacIsIdle = 0x2f800dbc;
lmacIsLongFrame = 0x2f800dc0;
lmacMSDUAged = 0x2f800dc4;
lmacPostTxComplete = 0x2f800dc8;
lmacProcessAllTxTimeout = 0x2f800dcc;
lmacProcessCollisions = 0x2f800dd0;
lmacProcessRxSucData = 0x2f800dd4;
lmacReachLongLimit = 0x2f800dd8;
lmacReachShortLimit = 0x2f800ddc;
lmacRecycleMPDU = 0x2f800de0;
lmacRxDone = 0x2f800de4;
lmacSetTxFrame = 0x2f800de8;
lmacTxDone = 0x2f800dec;
lmacTxFrame = 0x2f800df0;
lmacDisableTransmit = 0x2f800df4;
lmacDiscardFrameExchangeSequence = 0x2f800df8;
lmacProcessCollision = 0x2f800dfc;
lmacProcessAckTimeout = 0x2f800e00;
lmacProcessShortRetryFail = 0x2f800e04;
lmacProcessCollisions_task = 0x2f800e08;
lmacProcessTxRtsError = 0x2f800e0c;
lmacProcessTxError = 0x2f800e10;
lmacProcessCtsTimeout = 0x2f800e14;
lmacProcessLongRetryFail = 0x2f800e18;
lmacRetryTxFrame = 0x2f800e1c;
lmacEndRetryAMPDUFail = 0x2f800e20;
lmacProcessTxSuccess = 0x2f800e24;
lmacProcessTxComplete = 0x2f800e28;
lmacProcessLongFrameSuccess = 0x2f800e2c;
lmacProcessShortFrameSuccess = 0x2f800e30;
lmacProcessModemStateRxBeacon = 0x2f800e34;
mac_tx_set_duration = 0x2f800e38;
mac_tx_set_plcp0 = 0x2f800e3c;
mac_tx_set_plcp1 = 0x2f800e40;
mac_tx_set_plcp2 = 0x2f800e44;
mac_tx_set_len = 0x2f800e48;
mac_tx_set_htsig = 0x2f800e4c;
mac_tx_set_hesig = 0x2f800e50;
mac_tx_set_tb = 0x2f800e54;
mac_tx_set_mplen = 0x2f800e58;
mac_tx_set_txop_q = 0x2f800e5c;
mac_tx_set_pti = 0x2f800e60;
pm_check_state = 0x2f800e64;
pm_disable_dream_timer = 0x2f800e68;
pm_disable_sleep_delay_timer = 0x2f800e6c;
pm_dream = 0x2f800e70;
pm_mac_wakeup = 0x2f800e74;
pm_mac_sleep = 0x2f800e78;
pm_enable_active_timer = 0x2f800e7c;
pm_enable_sleep_delay_timer = 0x2f800e80;
pm_local_tsf_process = 0x2f800e84;
pm_set_beacon_filter = 0x2f800e88;
pm_is_in_wifi_slice_threshold = 0x2f800e8c;
pm_is_waked = 0x2f800e90;
pm_keep_alive = 0x2f800e94;
pm_on_beacon_rx = 0x2f800e98;
pm_on_data_rx = 0x2f800e9c;
pm_on_data_tx = 0x2f800ea0;
pm_on_tbtt = 0x2f800ea4;
pm_on_isr_sleep = 0x2f800ea8;
pm_on_isr = 0x2f800eac;
pm_on_isr_set_twt_target = 0x2f800eb0;
pm_on_isr_twt_wake = 0x2f800eb4;
pm_on_tsf_timer = 0x2f800eb8;
pm_on_twt_force_tx = 0x2f800ebc;
pm_parse_beacon = 0x2f800ec0;
pm_process_tim = 0x2f800ec4;
pm_rx_beacon_process = 0x2f800ec8;
pm_rx_data_process = 0x2f800ecc;
pm_sleep = 0x2f800ed0;
pm_sleep_for = 0x2f800ed4;
pm_tbtt_process = 0x2f800ed8;
pm_tx_data_done_process = 0x2f800edc;
pm_allow_tx = 0x2f800ee0;
pm_extend_tbtt_adaptive_servo = 0x2f800ee4;
pm_scale_listen_interval = 0x2f800ee8;
pm_parse_mbssid_element = 0x2f800eec;
pm_disconnected_wake = 0x2f800ef0;
pm_tx_data_process = 0x2f800ef4;
pm_is_twt_awake = 0x2f800ef8;
pm_enable_twt_keep_alive = 0x2f800efc;
pm_twt_on_tsf_timer = 0x2f800f00;
pm_twt_process = 0x2f800f04;
pm_is_twt_start = 0x2f800f08;
pm_twt_set_target_wdev_time = 0x2f800f0c;
pm_twt_set_target_tsf = 0x2f800f10;
pm_enable_twt_keep_alive_timer = 0x2f800f14;
pm_mac_try_enable_modem_state = 0x2f800f18;
pm_beacon_monitor_tbtt_timeout_process = 0x2f800f1c;
pm_update_next_tbtt = 0x2f800f20;
pm_twt_disallow_tx = 0x2f800f24;
pm_clear_wakeup_signal = 0x2f800f28;
pm_mac_disable_tsf_tbtt_soc_wakeup = 0x2f800f2c;
pm_mac_disable_tsf_tbtt_modem_wakeup = 0x2f800f30;
pm_mac_enable_tsf_tbtt_soc_wakeup = 0x2f800f34;
pm_mac_enable_tsf_tbtt_modem_wakeup = 0x2f800f38;
pm_mac_modem_params_rt_update = 0x2f800f3c;
pm_update_at_next_beacon = 0x2f800f40;
tbtt_adaptive_setup = 0x2f800f44;
tbtt_adaptive_servo = 0x2f800f48;
ppAMPDU2Normal = 0x2f800f4c;
ppHEAMPDU2Normal = 0x2f800f50;
ppAssembleAMPDU = 0x2f800f54;
ppCalFrameTimes = 0x2f800f58;
ppCalSubFrameLength = 0x2f800f5c;
ppCalTxAMPDULength = 0x2f800f60;
ppCheckTxAMPDUlength = 0x2f800f64;
ppDequeueRxq_Locked = 0x2f800f68;
ppDequeueTxQ = 0x2f800f6c;
ppEmptyDelimiterLength = 0x2f800f70;
ppEnqueueRxq = 0x2f800f74;
ppEnqueueTxDone = 0x2f800f78;
ppGetTxframe = 0x2f800f7c;
ppMapTxQueue = 0x2f800f80;
ppProcTxSecFrame = 0x2f800f84;
ppProcessRxPktHdr = 0x2f800f88;
ppProcessTxQ = 0x2f800f8c;
ppRecordBarRRC = 0x2f800f90;
ppRecycleAmpdu = 0x2f800f94;
ppRecycleRxPkt = 0x2f800f98;
ppResortTxAMPDU = 0x2f800f9c;
ppResumeTxAMPDU = 0x2f800fa0;
ppRxFragmentProc = 0x2f800fa4;
ppRxPkt = 0x2f800fa8;
ppRxProtoProc = 0x2f800fac;
ppSearchTxQueue = 0x2f800fb0;
ppSearchTxframe = 0x2f800fb4;
ppSelectNextQueue = 0x2f800fb8;
ppSubFromAMPDU = 0x2f800fbc;
ppTask = 0x2f800fc0;
ppTxPkt = 0x2f800fc4;
ppTxProtoProc = 0x2f800fc8;
ppTxqUpdateBitmap = 0x2f800fcc;
pp_coex_tx_request = 0x2f800fd0;
pp_hdrsize = 0x2f800fd4;
pp_post = 0x2f800fd8;
pp_process_hmac_waiting_txq = 0x2f800fdc;
ppDequeueTxDone_Locked = 0x2f800fe0;
ppProcTxDone = 0x2f800fe4;
ppMapWaitTxq = 0x2f800fe8;
ppProcessWaitingQueue = 0x2f800fec;
ppDisableQueue = 0x2f800ff0;
ppCheckTxRTS = 0x2f800ff4;
ppProcessLifeTime = 0x2f800ff8;
ppProcTxCallback = 0x2f800ffc;
ppCalPreFecPaddingFactor = 0x2f801000;
ppCalDeliNum = 0x2f801004;
ppRemoveHTC = 0x2f801008;
ppCheckTxHEAMPDUlength = 0x2f80100c;
ppCertSetRate = 0x2f801010;
ppSelectTxFormat = 0x2f801014;
ppCalTxHEAMPDULength = 0x2f801018;
pp_coex_tx_release = 0x2f80101c;
ppAdd2AMPDUTail = 0x2f801020;
ppDirectRecycleAmpdu = 0x2f801024;
ppRegressAmpdu = 0x2f801028;
pp_timer_do_process = 0x2f80102c;
rcGetAmpduSched = 0x2f801030;
rcUpdateRxDone = 0x2f801034;
rc_get_trc = 0x2f801038;
rc_get_trc_by_index = 0x2f80103c;
rcAmpduLowerRate = 0x2f801040;
rcampduuprate = 0x2f801044;
rcClearCurAMPDUSched = 0x2f801048;
rcClearCurSched = 0x2f80104c;
rcClearCurStat = 0x2f801050;
rcGetSched = 0x2f801054;
rcLowerSched = 0x2f801058;
rcSetTxAmpduLimit = 0x2f80105c;
rcTxUpdatePer = 0x2f801060;
rcUpdateAckSnr = 0x2f801064;
rcUpdateRate = 0x2f801068;
rcUpdateTxDone = 0x2f80106c;
rcUpdateTxDoneAmpdu2 = 0x2f801070;
rcUpSched = 0x2f801074;
rcReachRetryLimit = 0x2f801078;
rcGetDCMMaxRate = 0x2f80107c;
rcGetSMPDURate = 0x2f801080;
rcGetRate = 0x2f801084;
rx11AXRate2AMPDULimit = 0x2f801088;
rx11NRate2AMPDULimit = 0x2f80108c;
rssi_margin = 0x2f801090;
TRC_AMPDU_PER_DOWN_THRESHOLD = 0x2f801094;
TRC_AMPDU_PER_UP_THRESHOLD = 0x2f801098;
TRC_PER_IS_GOOD = 0x2f80109c;
trc_calc_duration = 0x2f8010a0;
trc_isTxAmpduOperational = 0x2f8010a4;
trc_onAmpduOp = 0x2f8010a8;
trc_SetTxAmpduState = 0x2f8010ac;
trc_tid_isTxAmpduOperational = 0x2f8010b0;
trcAmpduSetState = 0x2f8010b4;
trc_set_bf_report_rate = 0x2f8010b8;
trc_onPPTxDone = 0x2f8010bc;
wDevCheckBlockError = 0x2f8010c0;
wDev_AppendRxBlocks = 0x2f8010c4;
wDev_DiscardFrame = 0x2f8010c8;
wDev_GetNoiseFloor = 0x2f8010cc;
wDev_IndicateAmpdu = 0x2f8010d0;
wDev_IndicateFrame = 0x2f8010d4;
wdev_mac_reg_load = 0x2f8010d8;
wdev_mac_reg_store = 0x2f8010dc;
wdev_mac_special_reg_load = 0x2f8010e0;
wdev_mac_special_reg_store = 0x2f8010e4;
wdev_mac_wakeup = 0x2f8010e8;
wdev_mac_sleep = 0x2f8010ec;
wDev_ProcessFiq = 0x2f8010f0;
wDev_ProcessRxSucData = 0x2f8010f4;
wdevProcessRxSucDataAll = 0x2f8010f8;
wdev_csi_len_align = 0x2f8010fc;
wDev_IndicateBeaconMemoryFrame = 0x2f801100;
wDev_ProcessBeaconMemoryRxSuc = 0x2f801104;
wdevProcessModemStateRxBeacon = 0x2f801108;
wdev_is_data_in_rxlist = 0x2f80110c;
wdev_process_tbtt = 0x2f801110;
wdev_process_tsf_timer = 0x2f801114;
wdev_process_beacon_filter = 0x2f801118;
wdev_process_mac_modem_beacon_miss = 0x2f80111c;
config_is_cache_tx_buf_enabled = 0x2f801120;
esp_test_disable_tx_statistics = 0x2f801124;
esp_test_enable_tx_statistics = 0x2f801128;
esp_test_clr_tx_statistics = 0x2f80112c;
esp_test_get_tx_statistics = 0x2f801130;
esp_test_clr_tx_tb_statistics = 0x2f801134;
esp_test_get_tx_tb_statistics = 0x2f801138;
esp_test_tx_process_complete = 0x2f80113c;
esp_test_tx_process_txq_state = 0x2f801140;
esp_test_tx_enab_statistics = 0x2f801144;
esp_test_tx_tb_complete = 0x2f801148;
esp_test_tx_count_retry = 0x2f80114c;
esp_test_tx_count_collision = 0x2f801150;
esp_test_tx_count_timeout = 0x2f801154;
esp_test_rx_process_complete = 0x2f801158;
esp_test_clr_rx_statistics = 0x2f80115c;
esp_test_get_rx_statistics = 0x2f801160;
esp_test_set_rx_error_occurs = 0x2f801164;
esp_test_get_rx_error_occurs = 0x2f801168;
esp_test_clr_rx_error_occurs = 0x2f80116c;
esp_test_disable_rx_statistics = 0x2f801170;
esp_test_enable_rx_statistics = 0x2f801174;
esp_test_rx_parse_mu = 0x2f801178;
esp_test_get_rx_mu_statistics = 0x2f80117c;
esp_test_clr_rx_mu_statistics = 0x2f801180;
esp_test_enable_rx_mu_statistics = 0x2f801184;
esp_test_disable_rx_mu_statistics = 0x2f801188;
test_tx_fail_statistics = 0x2f80118c;
test_tx_succ_statistics = 0x2f801190;
test_rx_process_complete_noeb = 0x2f801194;
test_rx_process_complete_retry = 0x2f801198;
test_mumimo_get_heltf_num = 0x2f80119c;
test_mimo_update_user_info = 0x2f8011a0;
test_parse_rx_mu_mimo = 0x2f8011a4;
test_nonmimo_update_user_info = 0x2f8011a8;
test_rx_parse_mumimo_complete_sigb = 0x2f8011ac;
test_get_nonmumimo_common = 0x2f8011b0;
test_rx_parse_nonmumimo_complete_sigb = 0x2f8011b4;
test_rx_parse_nonmumimo = 0x2f8011b8;
wifi_he_get_hetb_tid_bitmap = 0x2f8011bc;
wifi_he_get_hetb_tid_bawin = 0x2f8011c0;
ht_get_min_subframe_len = 0x2f8011c4;
he_get_min_subframe_len = 0x2f8011c8;
he_get_min_subframe_len_dcm = 0x2f8011cc;
is_ndpa_to_dut = 0x2f8011d0;
is_use_muedca = 0x2f8011d4;
pwr_hal_clear_mac_modem_state_wakeup_protect_signal = 0x2f8011d8;
get_estimated_batime = 0x2f8011dc;
get_sublen_offset = 0x2f8011e0;
pm_beacon_add_total_counter = 0x2f8011e4;
pm_coex_recalculate_wifi_time_slice = 0x2f8011e8;
pm_mac_modem_tsf_tbtt_auto_period_enable_update = 0x2f8011ec;
/* Data (.data, .bss, .rodata) */
our_instances_ptr = 0x2f84ffe0;
pTxRx = 0x2f07ff58;
lmacConfMib_ptr = 0x2f07ff54;
our_wait_eb = 0x2f07ff50;
our_tx_eb = 0x2f07ff4c;
pp_wdev_funcs = 0x2f07ff48;
g_osi_funcs_p = 0x2f07ff44;
wDevCtrl_ptr = 0x2f07ff40;
g_wdev_last_desc_reset_ptr = 0x2f84ffdc;
wDevMacSleep_ptr = 0x2f07ff3c;
g_lmac_cnt_ptr = 0x2f07ff38;
our_controls_ptr = 0x2f84ffd8;
pp_sig_cnt_ptr = 0x2f07ff34;
g_eb_list_desc_ptr = 0x2f07ff30;
s_fragment_ptr = 0x2f07ff2c;
if_ctrl_ptr = 0x2f07ff28;
g_intr_lock_mux = 0x2f07ff24;
g_wifi_global_lock = 0x2f07ff20;
s_wifi_queue = 0x2f07ff1c;
pp_task_hdl = 0x2f07ff18;
s_pp_task_create_sem = 0x2f07ff14;
s_pp_task_del_sem = 0x2f07ff10;
xphyQueue = 0x2f07ff0c;
ap_no_lr_ptr = 0x2f07ff08;
rc11BSchedTbl_ptr = 0x2f07ff04;
rc11NSchedTbl_ptr = 0x2f07ff00;
rcLoRaSchedTbl_ptr = 0x2f07fefc;
BasicOFDMSched_ptr = 0x2f07fef8;
trc_ctl_ptr = 0x2f07fef4;
g_wifi_menuconfig_ptr = 0x2f07fef0;
g_pm_cnt_ptr = 0x2f07feec;
g_pm_ptr = 0x2f07fee8;
g_pm_cfg_ptr = 0x2f07fee4;
g_pm_twt_ptr = 0x2f07fee0;
g_esp_mesh_quick_funcs_ptr = 0x2f07fedc;
g_txop_queue_status_ptr = 0x2f07fed8;
g_mac_sleep_en_ptr = 0x2f07fed4;
g_mesh_is_root_ptr = 0x2f07fed0;
g_mesh_topology_ptr = 0x2f07fecc;
g_mesh_init_ps_type_ptr = 0x2f07fec8;
g_mesh_is_started_ptr = 0x2f07fec4;
g_config_func = 0x2f07fec0;
g_net80211_tx_func = 0x2f07febc;
g_timer_func = 0x2f07feb8;
g_dbg_interp_tsf = 0x2f07feb4;
g_dbg_interp_tsf_end = 0x2f07feb0;
g_dbg_closrf_tsf = 0x2f07feac;
g_dbg_closrf_idx = 0x2f07fea8;
g_dbg_closrf_blk = 0x2f07fea4;
s_michael_mic_failure_cb = 0x2f07fea0;
wifi_sta_rx_probe_req = 0x2f07fe9c;
g_tx_done_cb_func = 0x2f07fe98;
g_per_conn_trc = 0x2f07fe40;
rx_beacon_count = 0x2f07fe3c;
rx_beacon_tim_count = 0x2f07fe38;
rx_beacon_tim_udata = 0x2f07fe34;
rx_beacon_tim_udata_bitmap = 0x2f07fe30;
rx_beacon_tim_bdata = 0x2f07fe2c;
rx_beacon_tim_bdata_bitmapctl = 0x2f07fe28;
rx_beacon_tim_bdata_bitmap_trans = 0x2f07fe24;
rx_beacon_tim_bdata_bitmap_mbssid_self = 0x2f07fe20;
rx_beacon_tim_bdata_bitmap_mbssid_other = 0x2f07fe1c;
rx_beacon_dtim_tim = 0x2f07fe18;
rx_beacon_dtim_tim_mcast = 0x2f07fe14;
ampdu_delay = 0x2f07fe10;
s_ht_ampdu_density_us = 0x2f07fc5a;
s_ht_ampdu_density = 0x2f07fc59;
s_running_phy_type = 0x2f07fc58;
complete_ena_tb_seqno = 0x2f07fe0c;
complete_ena_tb_final = 0x2f07fe08;
complete_ena_tb_count = 0x2f07fe04;
s_he_min_len_bytes = 0x2f07fdc8;
s_he_dcm_min_len_bytes = 0x2f07fda8;
g_wdev_dbg_rx_ptr = 0x2f07fda4;
s_mplen_txq_bitmap = 0x2f07fd94;
s_mplen_be_high_bitmap = 0x2f07fd90;
s_phy_get_max_pwr = 0x2f07fd38;
esp_wifi_cert_tx_mcs = 0x2f07fc54;
esp_wifi_cert_tx_bcc = 0x2f07fc50;
esp_wifi_cert_tx_ltf = 0x2f07fc4c;
esp_wifi_cert_tx_gi = 0x2f07fc48;
esp_wifi_cert_tx_nss = 0x2f07fc44;
esp_wifi_cert_tx_ersu = 0x2f07fd34;
g_mac_deinit_count = 0x2f07fd30;
g_mac_deinit_rxing = 0x2f07fd2d;
g_mac_deinit_txing = 0x2f07fd2c;
s_bars = 0x2f07fd1c;
esp_test_rx_statistics = 0x2f07fd14;
esp_test_rx_mu_statistics = 0x2f07fd10;
esp_test_tx_statistics_aci_bitmap = 0x2f07fd0c;
esp_test_tx_statistics = 0x2f07fcfc;
esp_test_tx_tb_statistics = 0x2f07fcec;
esp_test_tx_fail_statistics = 0x2f07fc8c;
esp_test_mu_print_ru_allocation = 0x2f07fc88;
sigb_ru_allocation_user_num = 0x2f84ffc8;
sigb_common_ru_allocation = 0x2f84ff38;
mu_mimo_special_cfg_user_num_2 = 0x2f84fee8;
mu_mimo_special_cfg_user_num_3 = 0x2f84fe80;
mu_mimo_special_cfg_user_num_4 = 0x2f84fe28;
mu_mimo_special_cfg_user_num_5 = 0x2f84fdf0;
mu_mimo_special_cfg_user_num_6 = 0x2f84fdd0;
mu_mimo_special_cfg_user_num_7 = 0x2f84fdc0;
mu_mimo_special_cfg_user_num_8 = 0x2f84fdb8;
esp_test_rx_error_occurs = 0x2f07fc84;
g_pp_tx_pkt_num = 0x2f07fc80;
he_max_apep_length = 0x2f84fd40;
g_pp_timer_info_ptr = 0x2f07fc7c;
g_rts_threshold_bytes_ptr = 0x2f07fc78;
g_he_max_apep_length_tab_ptr = 0x2f07fc74;
s_pm_beacon_offset_ptr = 0x2f07fc70;
s_pm_beacon_offset_config_ptr = 0x2f07fc6c;
s_tbttstart_ptr = 0x2f07fc68;
s_offchan_tx_progress_in_ptr = 0x2f07fc64;
g_offchan_packet_lifetime_ptr = 0x2f07fc60;
g_send_wake_null_timer_ptr = 0x2f07fc5c;