Merge branch 'fix/psram_dependency' into 'master'

fix(build_system): cleaned up esp_psram dependencies See merge request espressif/esp-idf!51934
2026-10-02 11:10:54 +03:00 · 2026-08-25 10:39:01 +08:00
parent 76ecf87829 532b433246
commit c931510149
20 changed files with 115 additions and 64 deletions
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize the MSPI memory barrier workaround
+ *
+ * On targets affected by the MSPI memory barrier hardware issue, this allocates the
+ * dummy cacheline used by @ref esp_psram_mspi_mb to force a cache writeback/fence. On
+ * other targets this is a no-op.
+ *
+ * @return ESP_OK on success, otherwise an error code
+ */
+esp_err_t esp_psram_mspi_mb_init(void);
+
+/**
+ * @brief MSPI memory barrier
+ *
+ * Some targets need this workaround after a DMA transfer into PSRAM to make sure the
+ * data is visible to the CPU. This is a no-op on targets that don't need the workaround.
+ */
+void esp_psram_mspi_mb(void);
+
+#ifdef __cplusplus
+}
+#endif
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_cache.h"
+#include "esp_heap_caps.h"
+#include "esp_private/mspi_mem_barrier.h"
+
+#define MSPI_MEM_BARRIER_WORKAROUND    ((CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101))
+
+__attribute__((unused)) ESP_LOG_ATTR_TAG_DRAM(TAG, "mspi_mem_barrier");
+
+#if MSPI_MEM_BARRIER_WORKAROUND
+static void *s_psram_mb_dummy_cacheline;  //dummy cacheline for cache memory barrier
+#endif
+
+esp_err_t esp_psram_mspi_mb_init(void)
+{
+#if MSPI_MEM_BARRIER_WORKAROUND
+    s_psram_mb_dummy_cacheline = heap_caps_calloc(1, CONFIG_CACHE_L1_CACHE_LINE_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_CACHE_ALIGNED);
+    if (!s_psram_mb_dummy_cacheline) {
+        ESP_EARLY_LOGE(TAG, "Failed to allocate dummy cacheline for PSRAM memory barrier!");
+    }
+#endif
+
+    return ESP_OK;
+}
+
+void IRAM_ATTR esp_psram_mspi_mb(void)
+{
+#if MSPI_MEM_BARRIER_WORKAROUND
+    if (s_psram_mb_dummy_cacheline) {
+        uint32_t *p = (uint32_t *)s_psram_mb_dummy_cacheline;
+        *p = (*p + 1) % UINT32_MAX;
+        __attribute__((unused)) esp_err_t ret = ESP_FAIL;
+        ret = esp_cache_msync(s_psram_mb_dummy_cacheline, sizeof(uint32_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); //malloc is aligned, no need to writeback all
+        assert(ret == ESP_OK);
+        asm volatile("fence");
+    }
+#endif
+}