mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'feat/esp32s31_adds_efuse_adc_calib_v6.1' into 'release/v6.1'
feat(efuse): Adds efuse ADC calibration support for ESP32S31 (v6.1) See merge request espressif/esp-idf!52467
This commit is contained in:
morris
File diff suppressed because it is too large
Load Diff
@@ -9,7 +9,7 @@
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# This file was generated by regtools.py based on the efuses.yaml file with the version: 2ec5c3c5bd07b0b4e073b91d75592d8f
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# This file was generated by regtools.py based on the efuses.yaml file with the version: 110663d2f1ee8db2a1864a227b304e57
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WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
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@@ -53,9 +53,9 @@ WR_DIS.ECDSA_DISABLE_SOFT_K, EFUSE_BLK0, 14, 1, [] wr_dis
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WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
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WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
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WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
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WR_DIS.RMA_NONCE_ENA, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_NONCE_ENA
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WR_DIS.RMA_CHIP_INFO_SOURCE, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_CHIP_INFO_SOURCE
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WR_DIS.RMA_DISABLE_FAST_VEF, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_DISABLE_FAST_VEF
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WR_DIS.SDC_NONCE_ENA, EFUSE_BLK0, 14, 1, [] wr_dis of SDC_NONCE_ENA
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WR_DIS.SDC_CHIP_INFO_SOURCE, EFUSE_BLK0, 14, 1, [] wr_dis of SDC_CHIP_INFO_SOURCE
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WR_DIS.SDC_DISABLE_FAST_VEF, EFUSE_BLK0, 14, 1, [] wr_dis of SDC_DISABLE_FAST_VEF
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WR_DIS.ENA_XTS_SHADOW, EFUSE_BLK0, 14, 1, [] wr_dis of ENA_XTS_SHADOW
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WR_DIS.ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_BLK0, 14, 1, [] wr_dis of ENA_SPI_BOOT_CRYPT_SCRAMBLER
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WR_DIS.RE_ENABLE_JTAG_SOURCE, EFUSE_BLK0, 14, 1, [] wr_dis of RE_ENABLE_JTAG_SOURCE
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@@ -86,8 +86,20 @@ WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis
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WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
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WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
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WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
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WR_DIS.OCODE, EFUSE_BLK0, 20, 1, [] wr_dis of OCODE
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WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS
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WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS
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WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG
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WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS
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WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG
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WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
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WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP
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WR_DIS.PVT_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_DBIAS
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WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
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WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
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WR_DIS.TEMP_CALIBRATION, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIBRATION
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WR_DIS.SPI_LDO_1V8_DREF, EFUSE_BLK0, 21, 1, [] wr_dis of SPI_LDO_1V8_DREF
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WR_DIS.SPI_LDO_1V8_MUL, EFUSE_BLK0, 21, 1, [] wr_dis of SPI_LDO_1V8_MUL
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WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
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WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
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WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
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@@ -96,14 +108,39 @@ WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.K
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WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
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WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
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WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 28, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
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WR_DIS.ADC1_DIFF_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_DIFF_K
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WR_DIS.ADC1_DIFF_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_DIFF_B
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WR_DIS.ADC1_P_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_P_K
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WR_DIS.ADC1_P_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_P_B
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WR_DIS.ADC1_N_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_N_K
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WR_DIS.ADC1_N_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_N_B
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WR_DIS.ADC2_DIFF_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_DIFF_K
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WR_DIS.ADC2_DIFF_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_DIFF_B
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WR_DIS.ADC2_P_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_P_K
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WR_DIS.ADC2_P_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_P_B
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WR_DIS.ADC2_N_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_N_K
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WR_DIS.ADC2_N_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_N_B
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WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 28, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS
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WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
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RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-9
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RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BLOCK4-9
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RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
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RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
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RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
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RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
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RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
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RD_DIS.ADC1_DIFF_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_DIFF_K
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RD_DIS.ADC1_DIFF_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_DIFF_B
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RD_DIS.ADC1_P_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_P_K
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RD_DIS.ADC1_P_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_P_B
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RD_DIS.ADC1_N_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_N_K
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RD_DIS.ADC1_N_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_N_B
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RD_DIS.ADC2_DIFF_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_DIFF_K
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RD_DIS.ADC2_DIFF_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_DIFF_B
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RD_DIS.ADC2_P_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_P_K
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RD_DIS.ADC2_P_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_P_B
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RD_DIS.ADC2_N_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_N_K
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RD_DIS.ADC2_N_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_N_B
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RD_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 37, 1, [] rd_dis of USB_DEVICE_EXCHG_PINS
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DIS_USB_JTAG, EFUSE_BLK0, 42, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled
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DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled
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SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled
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@@ -114,14 +151,14 @@ DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Repres
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DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled
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HUK_GEN_STATE, EFUSE_BLK0, 55, 5, [] Represents the control of validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
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KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 64, 1, [] Represents the control of key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
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KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 66, 5, [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & rma nonce; bit4: psram
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KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 71, 5, [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & rma nonce 4: psram
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KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 66, 5, [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & SDC nonce; bit4: psram
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KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 71, 5, [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & SDC nonce 4: psram
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FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 76, 5, [] Represents whether corresponding key must come from key manager. 1 is true; 0 is false. 0: ecsda 1: flash 2: reserved 3: reserved 4: psram
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FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 81, 1, [] Represents whether to disable software written init key; and force use efuse_init_key
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KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 82, 1, [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key
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WDT_DELAY_SEL, EFUSE_BLK0, 83, 1, [] Represents the threshold level of the RTC watchdog STG0 timeout.0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16
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KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 82, 1, [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key
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WDT_DELAY_SEL, EFUSE_BLK0, 83, 1, [] Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16
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DIS_SM_CRYPT, EFUSE_BLK0, 84, 1, [] Represents whether to disable all the SM crypto functions; including SM2; SM3. 1: disabled 0: enabled
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SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 85, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
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SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 85, 3, [] Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled Even number of 1: disabled {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
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SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 88, 1, [] Revoke 1st secure boot key
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SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 89, 1, [] Revoke 2nd secure boot key
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SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 90, 1, [] Revoke 3rd secure boot key
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@@ -130,10 +167,10 @@ KEY_PURPOSE_1, EFUSE_BLK0, 101, 5, [KEY1_PUR
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KEY_PURPOSE_2, EFUSE_BLK0, 106, 5, [KEY2_PURPOSE] Represents the purpose of Key2
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KEY_PURPOSE_3, EFUSE_BLK0, 111, 5, [KEY3_PURPOSE] Represents the purpose of Key3
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KEY_PURPOSE_4, EFUSE_BLK0, 116, 5, [KEY4_PURPOSE] Represents the purpose of Key4
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ECC_FORCE_CONST_TIME, EFUSE_BLK0, 121, 1, [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off
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ECC_FORCE_CONST_TIME, EFUSE_BLK0, 121, 1, [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off
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ECDSA_DISABLE_SOFT_K, EFUSE_BLK0, 122, 1, [] Represents whether permanently turn off ECDSA software set KEY. 1: turn off 0: turn on
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SEC_DPA_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the spa secure level by configuring the clock random divide mode
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XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 125, 1, [] Represents whether to enable xts clock anti-dpa attack function.0: Disabled. 1: Enabled
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XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 125, 1, [] Represents whether to enable xts clock anti-dpa attack function. 0: Disabled. 1: Enabled
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XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 128, 2, [] Represents the control of the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation
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SECURE_BOOT_EN, EFUSE_BLK0, 130, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled
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SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 131, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
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@@ -156,32 +193,32 @@ DIS_WDT, EFUSE_BLK0, 195, 1, [] Set th
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DIS_SWD, EFUSE_BLK0, 196, 1, [] Set this bit to disable super-watchdog
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SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 203, 1, [] Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable
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BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION, EFUSE_BLK0, 204, 4, [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader
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BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 208, 1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled
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BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 209, 1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable
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BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 208, 1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. 1: Enabled 0: Disabled
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BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 209, 1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader. 1: Enable 0: Disable
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RECOVERY_BOOTLOADER_FLASH_SECTOR, EFUSE_BLK0, 210, 12, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
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RMA_ENA, EFUSE_BLK0, 222, 2, [] Represents whether rma function is supported in download mode. 2'b01/2'b10: enabled2'b00/2'b11: disabled
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RMA_SESSION_COUNTER, EFUSE_BLK0, 224, 3, [] Represents the number of times the RMA session has been entered
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RMA_NONCE_ENA, EFUSE_BLK0, 227, 2, [] Represents whether random number NONCE is used in RMA and whether the KM module is used to generate the NONCE. 2'bx0: No NONCE 2'b1x: Use KM generate NONCE.
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RMA_CHIP_INFO_SOURCE, EFUSE_BLK0, 229, 1, [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA.1: use HUK_info 0: use UNIQ_id
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RMA_DISABLE_FAST_VEF, EFUSE_BLK0, 230, 1, [] Represents whether disable FAST_VEF in RMA session.1: disable0: enable
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PVT_0_GLITCH_EN, EFUSE_BLK0, 231, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable
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SDC_ENA, EFUSE_BLK0, 222, 2, [] Represents whether SDC function is supported in download mode. 2'b01/2'b10: enabled 2'b00/2'b11: disabled
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SDC_SESSION_COUNTER, EFUSE_BLK0, 224, 3, [] Represents the number of times the SDC session has been entered
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SDC_NONCE_ENA, EFUSE_BLK0, 227, 2, [] Represents whether random number NONCE is used in SDC and whether the KM module is used to generate the NONCE . 2'bx0: No NONCE 2'b1x: Use KM generate NONCE
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SDC_CHIP_INFO_SOURCE, EFUSE_BLK0, 229, 1, [] Represents whether HUK_info is selected as the source for calculating CHIP_info in SDC. 1: use HUK_info 0: use UNIQ_id
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SDC_DISABLE_FAST_VEF, EFUSE_BLK0, 230, 1, [] Represents whether disable FAST_VEF in SDC session. 1: disable 0: enable
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PVT_0_GLITCH_EN, EFUSE_BLK0, 231, 1, [] Represents whether to enable PVT power glitch monitor function. 1:Enable. 0:Disable
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PVT_0_GLITCH_MODE, EFUSE_BLK0, 232, 2, [] Use to configure glitch mode
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PVT_1_GLITCH_EN, EFUSE_BLK0, 234, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable
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PVT_1_GLITCH_EN, EFUSE_BLK0, 234, 1, [] Represents whether to enable PVT power glitch monitor function. 1:Enable. 0:Disable
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PVT_1_GLITCH_MODE, EFUSE_BLK0, 235, 2, [] Use to configure glitch mode
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PMU_FLASH_POWER_SEL, EFUSE_BLK0, 237, 1, [] FLASH power select. 1'b1: use 3.3V1'b0: use 1.8V
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PMU_FLASH_POWER_SEL, EFUSE_BLK0, 237, 1, [] FLASH power select. 1'b1: use 3.3V 1'b0: use 1.8V
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PMU_FLASH_POWER_SEL_EN, EFUSE_BLK0, 238, 1, [] FLASH power select enable signal. 1'b1 : validates EFUSE_PMU_FLASH_POWER_SEL 1'b0: invalidates EFUSE_PMU_FLASH_POWER_SEL
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POWER_GLITCH_EN, EFUSE_BLK0, 239, 4, [] set these bit enable power glitch enable
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ENA_XTS_SHADOW, EFUSE_BLK0, 243, 1, [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled
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ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_BLK0, 244, 1, [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled
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RE_ENABLE_JTAG_SOURCE, EFUSE_BLK0, 245, 1, [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: RMA 1: HMAC
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ENA_XTS_SHADOW, EFUSE_BLK0, 243, 1, [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled
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ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_BLK0, 244, 1, [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled
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RE_ENABLE_JTAG_SOURCE, EFUSE_BLK0, 245, 1, [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: SDC 1: HMAC
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MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
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, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
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MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address
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, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address
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MAC_EXT, EFUSE_BLK1, 56, 8, [] Represents the extended bits of MAC address
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, EFUSE_BLK1, 48, 8, [] Represents the extended bits of MAC address
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WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] Minor chip version
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WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] Major chip version
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DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 120, 1, [] Disables check of wafer version major
|
||||
@@ -192,7 +229,19 @@ PSRAM_CAP, EFUSE_BLK1, 127, 3, [] Psram
|
||||
TEMP, EFUSE_BLK1, 130, 2, [] Maximum ambient temperature that ESP Chip can work properly
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 132, 2, [] Psram vendor
|
||||
PKG_VERSION, EFUSE_BLK1, 134, 2, [] Package version
|
||||
OCODE, EFUSE_BLK1, 136, 8, [] OCode calibration
|
||||
ACTIVE_HP_DBIAS, EFUSE_BLK1, 144, 4, [] Active HP DBIAS of fixed voltage
|
||||
ACTIVE_LP_DBIAS, EFUSE_BLK1, 148, 4, [] Active LP DBIAS of fixed voltage
|
||||
LSLP_HP_DBG, EFUSE_BLK1, 152, 2, [] LSLP HP DBG of fixed voltage
|
||||
LSLP_HP_DBIAS, EFUSE_BLK1, 154, 4, [] LSLP HP DBIAS of fixed voltage
|
||||
DSLP_LP_DBG, EFUSE_BLK1, 158, 4, [] DSLP LP DBG of fixed voltage
|
||||
DSLP_LP_DBIAS, EFUSE_BLK1, 162, 5, [] DSLP LP DBIAS of fixed voltage
|
||||
LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 167, 5, [] DBIAS gap between LP and HP
|
||||
PVT_DBIAS, EFUSE_BLK1, 172, 4, [] PVT DBIAS
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
TEMP_CALIBRATION, EFUSE_BLK2, 128, 10, [] Temperature calibration
|
||||
SPI_LDO_1V8_DREF, EFUSE_BLK2, 138, 4, [] SPI LDO 1.8 V DREF
|
||||
SPI_LDO_1V8_MUL, EFUSE_BLK2, 142, 3, [] SPI LDO 1.8 V multiplier
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
@@ -200,5 +249,16 @@ KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KE
|
||||
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK9, 0, 32, [BLOCK_SYS_DATA2] System data part 2 (reserved)
|
||||
USB_DEVICE_EXCHG_PINS, EFUSE_BLK9, 192, 1, [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled
|
||||
ADC1_DIFF_K, EFUSE_BLK9, 0, 11, [] Fitted slope (K) of ADC1 in differential mode
|
||||
ADC1_DIFF_B, EFUSE_BLK9, 11, 10, [] Intercept (B) of ADC1 in differential mode
|
||||
ADC1_P_K, EFUSE_BLK9, 21, 11, [] Fitted slope (K) of ADC1 in P mode
|
||||
ADC1_P_B, EFUSE_BLK9, 32, 10, [] Intercept (B) of ADC1 in P mode
|
||||
ADC1_N_K, EFUSE_BLK9, 42, 11, [] Fitted slope (K) of ADC1 in N mode
|
||||
ADC1_N_B, EFUSE_BLK9, 53, 10, [] Intercept (B) of ADC1 in N mode
|
||||
ADC2_DIFF_K, EFUSE_BLK9, 63, 11, [] Fitted slope (K) of ADC2 in differential mode
|
||||
ADC2_DIFF_B, EFUSE_BLK9, 74, 10, [] Intercept (B) of ADC2 in differential mode
|
||||
ADC2_P_K, EFUSE_BLK9, 84, 11, [] Fitted slope (K) of ADC2 in P mode
|
||||
ADC2_P_B, EFUSE_BLK9, 95, 10, [] Intercept (B) of ADC2 in P mode
|
||||
ADC2_N_K, EFUSE_BLK9, 105, 11, [] Fitted slope (K) of ADC2 in N mode
|
||||
ADC2_N_B, EFUSE_BLK9, 116, 10, [] Intercept (B) of ADC2 in N mode
|
||||
USB_DEVICE_EXCHG_PINS, EFUSE_BLK9, 192, 1, [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 1cdb8731d5e8193ceb48139f9db95994
|
||||
// md5_digest_table d75d0e39a18319b5287c3790c42a8d06
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@@ -64,9 +64,9 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_SOFT_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_NONCE_ENA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_CHIP_INFO_SOURCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_DISABLE_FAST_VEF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_NONCE_ENA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_CHIP_INFO_SOURCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_DISABLE_FAST_VEF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENA_XTS_SHADOW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENA_SPI_BOOT_CRYPT_SCRAMBLER[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RE_ENABLE_JTAG_SOURCE[];
|
||||
@@ -98,8 +98,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIBRATION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_LDO_1V8_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_LDO_1V8_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
@@ -117,6 +129,18 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_DIFF_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_DIFF_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_P_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_P_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_N_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_N_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_DIFF_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_DIFF_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_P_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_P_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_N_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_N_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
@@ -130,6 +154,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_DIFF_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_DIFF_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_P_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_P_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_N_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_N_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_DIFF_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_DIFF_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_P_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_P_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_N_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_N_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
@@ -190,11 +227,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RMA_ENA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RMA_SESSION_COUNTER[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RMA_NONCE_ENA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RMA_CHIP_INFO_SOURCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RMA_DISABLE_FAST_VEF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SDC_ENA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SDC_SESSION_COUNTER[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SDC_NONCE_ENA[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SDC_CHIP_INFO_SOURCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SDC_DISABLE_FAST_VEF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_1_GLITCH_EN[];
|
||||
@@ -218,7 +255,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIBRATION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_LDO_1V8_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_LDO_1V8_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
@@ -234,8 +283,18 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_DIFF_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_DIFF_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_P_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_P_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_N_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_N_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_DIFF_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_DIFF_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_P_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_P_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_N_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_N_B[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user