feat(dac): use default clock source for zero config

This commit is contained in:
morris
2026-08-26 12:17:04 +08:00
parent 9ff5389763
commit c47382a311
9 changed files with 26 additions and 49 deletions
@@ -83,7 +83,6 @@ void app_main(void)
.desc_num = 4,
.buf_size = 2048,
.freq_hz = CONFIG_EXAMPLE_AUDIO_SAMPLE_RATE,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_APLL, // Using APLL as clock source to get a wider frequency range
/* Assume the data in buffer is 'A B C D E F'
* DAC_CHANNEL_MODE_SIMUL:
@@ -64,8 +64,6 @@ void example_dac_continuous_by_dma(void)
.desc_num = 8,
.buf_size = 2048,
.freq_hz = EXAMPLE_CONVERT_FREQ_HZ,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // If the frequency is out of range, try 'DAC_DIGI_CLK_SRC_APLL'
/* Assume the data in buffer is 'A B C D E F'
* DAC_CHANNEL_MODE_SIMUL:
* - channel 0: A B C D E F