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feat(dac): use default clock source for zero config

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This commit is contained in:
morris
2026-08-26 11:50:52 +08:00
parent 9ff5389763
commit c47382a311
9 changed files with 26 additions and 49 deletions
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7
components/esp_driver_dac/dac_continuous.c
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@@ -228,6 +228,9 @@ esp_err_t dac_continuous_new_channels(const dac_continuous_config_t *cont_cfg, d
ESP_GOTO_ON_FALSE(handle, ESP_ERR_NO_MEM, err_dereg, TAG, "no memory for the dac continuous mode structure");
handle->cfg = *cont_cfg;
if (handle->cfg.clk_src == 0) {
handle->cfg.clk_src = DAC_DIGI_CLK_SRC_DEFAULT;
}
#if SOC_IS(ESP32)
handle->dma_lock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
@@ -240,7 +243,7 @@ esp_err_t dac_continuous_new_channels(const dac_continuous_config_t *cont_cfg, d
/* Create PM lock */
#if CONFIG_PM_ENABLE
esp_pm_lock_type_t pm_lock_type = cont_cfg->clk_src == DAC_DIGI_CLK_SRC_APLL ? ESP_PM_NO_LIGHT_SLEEP : ESP_PM_APB_FREQ_MAX;
esp_pm_lock_type_t pm_lock_type = handle->cfg.clk_src == DAC_DIGI_CLK_SRC_APLL ? ESP_PM_NO_LIGHT_SLEEP : ESP_PM_APB_FREQ_MAX;
ESP_GOTO_ON_ERROR(esp_pm_lock_create(pm_lock_type, 0, "dac_driver", &handle->pm_lock), err_free, TAG, "Failed to create DAC pm lock");
#endif
@@ -252,7 +255,7 @@ esp_err_t dac_continuous_new_channels(const dac_continuous_config_t *cont_cfg, d
.on_done = dac_dma_done_callback,
.on_teof = dac_dma_teof_callback,
};
ESP_GOTO_ON_ERROR(dac_priv_dma_init(cont_cfg->clk_src, cont_cfg->freq_hz, cont_cfg->chan_mode == DAC_CHANNEL_MODE_ALTER, &cbs, handle),
ESP_GOTO_ON_ERROR(dac_priv_dma_init(handle->cfg.clk_src, handle->cfg.freq_hz, handle->cfg.chan_mode == DAC_CHANNEL_MODE_ALTER, &cbs, handle),
err_desc, TAG, "Failed to initialize DAC DMA peripheral");
/* Connect DAC module to the DMA peripheral */

31
components/esp_driver_dac/dac_cosine.c
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@@ -41,12 +41,15 @@ esp_err_t dac_cosine_new_channel(const dac_cosine_config_t *cos_cfg, dac_cosine_
ESP_RETURN_ON_FALSE(handle, ESP_ERR_NO_MEM, TAG, "no memory for the dac cosine handle");
/* Assign configurations */
handle->cfg = *cos_cfg;
if (handle->cfg.clk_src == 0) {
handle->cfg.clk_src = DAC_COSINE_CLK_SRC_DEFAULT;
}
/* Register the handle */
ESP_GOTO_ON_ERROR(dac_priv_register_channel(cos_cfg->chan_id), err1, TAG, "register dac channel %d failed", cos_cfg->chan_id);
ESP_GOTO_ON_ERROR(dac_priv_register_channel(handle->cfg.chan_id), err1, TAG, "register dac channel %d failed", handle->cfg.chan_id);
/* Cosine wave generator uses RTC_FAST clock which is divided from RC_FAST */
/* Get the cosine wave generator clock frequency */
uint32_t rtc_clk_freq = 0;
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_RC_FAST, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rtc_clk_freq);
esp_clk_tree_src_get_freq_hz((soc_module_clk_t)handle->cfg.clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rtc_clk_freq);
if (rtc_clk_freq == 0) {
ESP_LOGW(TAG, "RTC clock calibration failed, using the approximate value as default");
@@ -54,13 +57,13 @@ esp_err_t dac_cosine_new_channel(const dac_cosine_config_t *cos_cfg, dac_cosine_
}
DAC_ENTER_CRITICAL();
/* Set coefficients for cosine wave generator */
if ((!s_cwg_freq) || cos_cfg->flags.force_set_freq) {
dac_ll_cw_set_freq(cos_cfg->freq_hz, rtc_clk_freq);
s_cwg_freq = cos_cfg->freq_hz;
if ((!s_cwg_freq) || handle->cfg.flags.force_set_freq) {
dac_ll_cw_set_freq(handle->cfg.freq_hz, rtc_clk_freq);
s_cwg_freq = handle->cfg.freq_hz;
}
dac_ll_cw_set_atten(cos_cfg->chan_id, cos_cfg->atten);
dac_ll_cw_set_phase(cos_cfg->chan_id, cos_cfg->phase);
dac_ll_cw_set_dc_offset(cos_cfg->chan_id, cos_cfg->offset);
dac_ll_cw_set_atten(handle->cfg.chan_id, handle->cfg.atten);
dac_ll_cw_set_phase(handle->cfg.chan_id, handle->cfg.phase);
dac_ll_cw_set_dc_offset(handle->cfg.chan_id, handle->cfg.offset);
DAC_EXIT_CRITICAL();
*ret_handle = handle;
@@ -94,8 +97,8 @@ esp_err_t dac_cosine_start(dac_cosine_handle_t handle)
DAC_NULL_POINTER_CHECK(handle);
ESP_RETURN_ON_FALSE(!handle->is_started, ESP_ERR_INVALID_STATE, TAG,
"the dac channel has already started");
/* Acquire the RTC clock */
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(SOC_MOD_CLK_RC_FAST, true), TAG, "RC_FAST clock enable failed");
/* Acquire the cosine wave generator clock */
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)handle->cfg.clk_src, true), TAG, "cosine clock enable failed");
/* Enabled DAC channel */
ESP_GOTO_ON_ERROR(dac_priv_enable_channel(handle->cfg.chan_id), err, TAG,
"enable dac channel %d failed", handle->cfg.chan_id);
@@ -113,7 +116,7 @@ esp_err_t dac_cosine_start(dac_cosine_handle_t handle)
return ESP_OK;
err:
esp_clk_tree_enable_src(SOC_MOD_CLK_RC_FAST, false);
esp_clk_tree_enable_src((soc_module_clk_t)handle->cfg.clk_src, false);
return ret;
}
@@ -136,8 +139,8 @@ esp_err_t dac_cosine_stop(dac_cosine_handle_t handle)
}
handle->is_started = false;
DAC_EXIT_CRITICAL();
/* Release the RTC clock */
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(SOC_MOD_CLK_RC_FAST, false), TAG, "RC_FAST clock disable failed");
/* Release the cosine wave generator clock */
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)handle->cfg.clk_src, false), TAG, "cosine clock disable failed");
return ESP_OK;
}

5
components/esp_driver_dac/include/driver/dac_continuous.h
View File

@@ -43,9 +43,8 @@ typedef struct {
* Typically not suggest to set the frequency higher than 2 MHz, otherwise the severe distortion will appear
*/
int8_t offset; /*!< The offset of the DAC digital data. Range -128~127 */
dac_continuous_digi_clk_src_t clk_src; /*!< The clock source of digital controller, which can affect the range of supported frequency
* Currently `DAC_DIGI_CLK_SRC_DEFAULT` and `DAC_DIGI_CLK_SRC_APLL` are available
*/
dac_continuous_digi_clk_src_t clk_src; /*!< The clock source of digital controller, which can affect the range of supported frequency.
Set to 0 to use `DAC_DIGI_CLK_SRC_DEFAULT`.*/
dac_continuous_channel_mode_t chan_mode; /*!< The channel mode of continuous mode, only take effect when multiple channels enabled, depends converting the buffer alternately or simultaneously */
} dac_continuous_config_t;

3
components/esp_driver_dac/include/driver/dac_cosine.h
View File

@@ -30,7 +30,8 @@ typedef struct {
* the waveform will distort at high frequency due to the hardware limitation.
* Typically not suggest to set the frequency higher than 200 KHz
*/
dac_cosine_clk_src_t clk_src; /*!< The clock source of the cosine wave generator, currently only support `DAC_COSINE_CLK_SRC_DEFAULT` */
dac_cosine_clk_src_t clk_src; /*!< The clock source of the cosine wave generator.
Set to 0 to use `DAC_COSINE_CLK_SRC_DEFAULT`. */
dac_cosine_atten_t atten; /*!< The attenuation of cosine wave amplitude */
dac_cosine_phase_t phase; /*!< The phase of cosine wave, can only support DAC_COSINE_PHASE_0 or DAC_COSINE_PHASE_180, default as 0 while setting an unsupported phase */
int8_t offset; /*!< The DC offset of cosine wave */

20
components/esp_driver_dac/test_apps/dac/main/test_dac.c
View File

@@ -59,8 +59,6 @@ TEST_CASE("DAC_API_basic_logic_test", "[dac]")
dac_cosine_config_t cos0_cfg = {
.chan_id = DAC_CHAN_0,
.freq_hz = 1000, // It will be covered by 8000 in the latter configuration
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_0,
.atten = DAC_COSINE_ATTEN_DEFAULT,
.flags.force_set_freq = false,
@@ -68,8 +66,6 @@ TEST_CASE("DAC_API_basic_logic_test", "[dac]")
dac_cosine_config_t cos1_cfg = {
.chan_id = DAC_CHAN_1,
.freq_hz = 8000,
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_180,
.atten = DAC_COSINE_ATTEN_DB_6,
.flags.force_set_freq = false,
@@ -96,8 +92,6 @@ TEST_CASE("DAC_API_basic_logic_test", "[dac]")
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
/* DMA peripheral availability test */
@@ -129,8 +123,6 @@ TEST_CASE("DAC_memory_leak_test", "[dac]")
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
size_t len = 1024;
@@ -206,8 +198,6 @@ TEST_CASE("DAC_dma_write_test", "[dac]")
.desc_num = 8,
.buf_size = 1024,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
size_t len = 520; // To test if the driver can work correctly with uncommon length
@@ -244,8 +234,6 @@ TEST_CASE("DAC_dma_sync_write_resume_test", "[dac]")
.desc_num = 4,
.buf_size = 256,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
@@ -316,8 +304,6 @@ TEST_CASE("DAC_dma_convert_frequency_test", "[dac]")
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 20000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
TEST_ESP_OK(dac_continuous_new_channels(&cont_cfg, &cont_handle));
@@ -373,8 +359,6 @@ TEST_CASE("DAC_cosine_wave_test", "[dac]")
dac_cosine_config_t cos0_cfg = {
.chan_id = DAC_CHAN_0,
.freq_hz = 1000, // It will be covered by 8000 in the latter configuration
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_0,
.atten = DAC_COSINE_ATTEN_DEFAULT,
.flags.force_set_freq = false,
@@ -382,8 +366,6 @@ TEST_CASE("DAC_cosine_wave_test", "[dac]")
dac_cosine_config_t cos1_cfg = {
.chan_id = DAC_CHAN_1,
.freq_hz = 1000,
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_180,
.atten = DAC_COSINE_ATTEN_DB_6,
.flags.force_set_freq = false,
@@ -452,8 +434,6 @@ TEST_CASE("DAC_continuous_mode_concurrency_test", "[dac]")
.desc_num = 8,
.buf_size = 1024,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};

2
components/esp_driver_dac/test_apps/dac/main/test_dac_iram.c
View File

@@ -68,8 +68,6 @@ TEST_CASE("DAC_IRAM_safe_test", "[dac]")
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 40000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // If the frequency is out of range, try 'DAC_DIGI_CLK_SRC_APLL'
/* Assume the data in buffer is 'A B C D E F'
* DAC_CHANNEL_MODE_SIMUL:
* - channel 0: A B C D E F

1
examples/peripherals/dac/dac_continuous/dac_audio/main/dac_audio_example_main.c
View File

@@ -83,7 +83,6 @@ void app_main(void)
.desc_num = 4,
.buf_size = 2048,
.freq_hz = CONFIG_EXAMPLE_AUDIO_SAMPLE_RATE,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_APLL, // Using APLL as clock source to get a wider frequency range
/* Assume the data in buffer is 'A B C D E F'
* DAC_CHANNEL_MODE_SIMUL:

2
examples/peripherals/dac/dac_continuous/signal_generator/main/dac_continuous_example_dma.c
View File

@@ -64,8 +64,6 @@ void example_dac_continuous_by_dma(void)
.desc_num = 8,
.buf_size = 2048,
.freq_hz = EXAMPLE_CONVERT_FREQ_HZ,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // If the frequency is out of range, try 'DAC_DIGI_CLK_SRC_APLL'
/* Assume the data in buffer is 'A B C D E F'
* DAC_CHANNEL_MODE_SIMUL:
* - channel 0: A B C D E F

4
examples/peripherals/dac/dac_cosine_wave/main/dac_cosine_example_main.c
View File

@@ -46,8 +46,6 @@ void app_main(void)
dac_cosine_config_t cos0_cfg = {
.chan_id = DAC_CHAN_0,
.freq_hz = 1000, // It will be covered by 8000 in the latter configuration
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_0,
.atten = DAC_COSINE_ATTEN_DEFAULT,
.flags.force_set_freq = false,
@@ -55,8 +53,6 @@ void app_main(void)
dac_cosine_config_t cos1_cfg = {
.chan_id = DAC_CHAN_1,
.freq_hz = 8000,
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_180,
.atten = DAC_COSINE_ATTEN_DB_6,
.flags.force_set_freq = true, // set true will allow to overwrite the frequency that set before