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feat(efuse): Support efuses for ESP32S31

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This commit is contained in:
Konstantin Kondrashov
2026-04-29 15:50:32 +03:00
parent 41e67e1efb
commit c29532f98c
28 changed files with 2335 additions and 2403 deletions
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components/hal/esp32s31/efuse_hal.c
+4 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,8 +10,6 @@
#include "hal/efuse_hal.h"
#include "hal/efuse_ll.h"
// TODO: [ESP32S31] IDF-14688
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block))))
#define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block))))
@@ -73,12 +71,12 @@ void efuse_hal_rs_calculate(const void *data, void *rs_values)
bool efuse_hal_is_coding_error_in_block(unsigned block)
{
if (block == 0) {
for (unsigned i = 0; i < 5; i++) {
if (REG_READ(EFUSE_RD_REPEAT_DATA_ERR0_REG + i * 4)) {
for (unsigned i = 0; i < 8; i++) {
if (REG_READ(EFUSE_RD_REPEAT_DATA_ERR0_REG + i * 4)) { // DATA_ERR0_REG ... DATA_ERR7_REG
return true;
}
}
} else if (block <= 10) {
} else if (block <= 9) {
block--;
uint32_t error_reg = REG_READ(EFUSE_RD_RS_DATA_ERR0_REG + (block / 8) * 4);
return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
components/hal/esp32s31/include/hal/efuse_ll.h
+17 -34
View File
@@ -8,10 +8,12 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_defs.h"
#include "soc/efuse_reg.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
#include "soc/efuse_defs.h"
#ifdef __cplusplus
extern "C" {
@@ -28,25 +30,20 @@ typedef enum {
// Always inline these functions even no gcc optimization is applied.
// TODO: [ESP32S31] IDF-14688 This file is inherited from verification branch, need to check all functions.
/******************* eFuse fields *************************/
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
{
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
{
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_repeat_data1.wdt_delay_sel;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_mac_sys0.mac_0;
}
@@ -63,54 +60,40 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return 0;
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_mac_sys3.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return 0;
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_mac_sys3.wafer_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return 0;
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_mac_sys3.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return 0;
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_mac_sys3.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return 0;
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_mac_sys3.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return 0;
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_mac_sys3.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
return 0;
// TODO: [ESP32S31] IDF-14688
return EFUSE.rd_mac_sys4.pkg_version;
}
// TODO: [ESP32S31] IDF-14688
// __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk)
// {
// (void) curve;
//
// }
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
@@ -125,37 +108,37 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
{
// TODO: [ESP32S31] IDF-14688
EFUSE.cmd.read_cmd = 1;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
// TODO: [ESP32S31] IDF-14688
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
// TODO: [ESP32S31] IDF-14688
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
// TODO: [ESP32S31] IDF-14688
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
// TODO: [ESP32S31] IDF-14688
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
{
// TODO: [ESP32S31] IDF-14688
EFUSE.wr_tim_conf0_rs_bypass.update = 1;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_controller_state(void)
{
// TODO: [ESP32S31] IDF-14688
return EFUSE.status.state;
}