From c29532f98cd3c36ec7d244b8363c14211f050a75 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Mon, 27 Apr 2026 11:05:13 +0300 Subject: [PATCH] feat(efuse): Support efuses for ESP32S31 --- .../src/esp32s31/bootloader_esp32s31.c | 1 + components/efuse/efuse_table_gen.py | 209 +- components/efuse/esp32s31/esp_efuse_table.c | 1674 ++++------------- components/efuse/esp32s31/esp_efuse_table.csv | 309 ++- components/efuse/esp32s31/esp_efuse_utility.c | 9 +- .../efuse/esp32s31/include/esp_efuse_chip.h | 38 +- .../efuse/esp32s31/include/esp_efuse_table.h | 187 +- .../private_include/esp_efuse_utility.h | 2 +- components/efuse/include/esp_efuse.h | 7 +- .../with_key_purposes/esp_efuse_api_key.c | 12 +- components/efuse/src/esp_efuse_utility.c | 3 +- .../efuse/test_apps/.build-test-rules.yml | 6 +- components/efuse/test_apps/README.md | 4 +- .../main/with_key_purposes/test_efuse.c | 12 +- .../main/with_key_purposes/test_efuse_keys.c | 2 +- components/hal/esp32s31/efuse_hal.c | 10 +- .../hal/esp32s31/include/hal/efuse_ll.h | 51 +- .../esp32s31/include/soc/Kconfig.soc_caps.in | 8 + .../soc/esp32s31/include/soc/soc_caps.h | 10 +- .../soc/esp32s31/register/soc/efuse_reg.h | 846 ++++++--- .../soc/esp32s31/register/soc/efuse_struct.h | 873 ++++++--- .../system/inc/espefuse_summary_ESP32-S31.rst | 195 +- .../inc/espefuse_summary_ESP32-S31_dump.rst | 21 +- .../system/inc/show-efuse-table_ESP32-S31.rst | 232 ++- .../system/inc/espefuse_summary_ESP32-S31.rst | 5 +- .../inc/espefuse_summary_ESP32-S31_dump.rst | 5 +- .../system/inc/show-efuse-table_ESP32-S31.rst | 5 +- examples/system/.build-test-rules.yml | 2 +- 28 files changed, 2335 insertions(+), 2403 deletions(-) diff --git a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c index 642c685d850..2e8df43e161 100644 --- a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c +++ b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c @@ -18,6 +18,7 @@ #include "bootloader_console.h" #include "bootloader_flash_priv.h" #include "bootloader_soc.h" +#include "esp_efuse.h" #include "esp_private/bootloader_flash_internal.h" #if SOC_RTC_WDT_SUPPORTED #include "soc/rtc_wdt_reg.h" diff --git a/components/efuse/efuse_table_gen.py b/components/efuse/efuse_table_gen.py index 1253886f47f..f9f8112d6aa 100755 --- a/components/efuse/efuse_table_gen.py +++ b/components/efuse/efuse_table_gen.py @@ -4,7 +4,7 @@ # # Converts efuse table to header file efuse_table.h. # -# SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: Apache-2.0 import argparse @@ -22,30 +22,30 @@ idf_target = 'esp32' def get_copyright(): - copyright_str = '''/* + copyright_str = """/* * SPDX-FileCopyrightText: 2017-%d Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -''' +""" return copyright_str % datetime.today().year def status(msg): - """ Print status message to stderr """ + """Print status message to stderr""" if not quiet: critical(msg) def critical(msg): - """ Print critical message to stderr """ + """Print critical message to stderr""" sys.stderr.write(msg) sys.stderr.write('\n') class FuseTable(list): def __init__(self): - super(FuseTable, self).__init__(self) + super().__init__() self.md5_digest_table = '' @classmethod @@ -57,7 +57,7 @@ class FuseTable(list): f = os.path.expandvars(f) m = re.match(r'(?', - '#include "' + file_name + '.h"', - '', - '// md5_digest_table ' + self.md5_digest_table, - '// This file was generated from the file ' + file_name + '.csv. DO NOT CHANGE THIS FILE MANUALLY.', - '// If you want to change some fields, you need to change ' + file_name + '.csv file', - '// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.', - "// To show efuse_table run the command 'show_efuse_table'."] + rows += [ + '#include "sdkconfig.h"', + '#include "esp_efuse.h"', + '#include ', + '#include "' + file_name + '.h"', + '', + '// md5_digest_table ' + self.md5_digest_table, + '// This file was generated from the file ' + file_name + '.csv. DO NOT CHANGE THIS FILE MANUALLY.', + '// If you want to change some fields, you need to change ' + file_name + '.csv file', + '// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.', + "// To show efuse_table run the command 'show_efuse_table'.", + ] rows += [''] @@ -308,20 +312,35 @@ class FuseTable(list): rows += [''] if last_free_bit_blk1 is not None: - rows += ['_Static_assert(LAST_FREE_BIT_BLK1 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' - 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] + rows += [ + '_Static_assert(' + 'LAST_FREE_BIT_BLK1 <= MAX_BLK_LEN, ' + '"The eFuse table does not match the coding scheme. ' + 'Edit the table and restart the efuse_common_table or efuse_custom_table command ' + 'to regenerate the new files.");' + ] if last_free_bit_blk2 is not None: - rows += ['_Static_assert(LAST_FREE_BIT_BLK2 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' - 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] + rows += [ + '_Static_assert(' + 'LAST_FREE_BIT_BLK2 <= MAX_BLK_LEN, ' + '"The eFuse table does not match the coding scheme. ' + 'Edit the table and restart the efuse_common_table or efuse_custom_table command ' + 'to regenerate the new files.");' + ] if last_free_bit_blk3 is not None: - rows += ['_Static_assert(LAST_FREE_BIT_BLK3 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' - 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] + rows += [ + '_Static_assert(' + 'LAST_FREE_BIT_BLK3 <= MAX_BLK_LEN, ' + '"The eFuse table does not match the coding scheme. ' + 'Edit the table and restart the efuse_common_table or efuse_custom_table command ' + 'to regenerate the new files.");' + ] rows += [''] last_name = '' for p in self: - if (p.field_name != last_name): + if p.field_name != last_name: if last_name != '': rows += ['};\n'] rows += ['static const esp_efuse_desc_t ' + p.field_name.replace('.', '_') + '[] = {'] @@ -332,21 +351,19 @@ class FuseTable(list): last_name = '' for p in self: - if (p.field_name != last_name): + if p.field_name != last_name: if last_name != '': - rows += [' NULL', - '};\n'] + rows += [' NULL', '};\n'] rows += ['const esp_efuse_desc_t* ' + 'ESP_EFUSE_' + p.field_name.replace('.', '_') + '[] = {'] last_name = p.field_name index = str(0) if str(p.group) == '' else str(p.group) rows += [' &' + p.field_name.replace('.', '_') + '[' + index + '], \t\t// ' + p.comment] - rows += [' NULL', - '};\n'] + rows += [' NULL', '};\n'] return '\n'.join(rows) -class FuseDefinition(object): +class FuseDefinition: def __init__(self): self.field_name = '' self.group = '' @@ -358,7 +375,7 @@ class FuseDefinition(object): @classmethod def from_csv(cls, line): - """ Parse a line from the CSV """ + """Parse a line from the CSV""" line_w_defaults = line + ',,,,' # lazy way to support default fields fields = [f.strip() for f in line_w_defaults.split(',')] @@ -388,7 +405,7 @@ class FuseDefinition(object): try: return int(v, 0) except ValueError: - raise InputError('Invalid field value %s' % v) + raise InputError(f'Invalid field value {v}') def parse_block(self, strval): if strval == '': @@ -397,17 +414,30 @@ class FuseDefinition(object): if strval not in ['EFUSE_BLK0', 'EFUSE_BLK1', 'EFUSE_BLK2', 'EFUSE_BLK3']: raise InputError("Field 'efuse_block' should be one of EFUSE_BLK0..EFUSE_BLK3") else: - if strval not in ['EFUSE_BLK0', 'EFUSE_BLK1', 'EFUSE_BLK2', 'EFUSE_BLK3', 'EFUSE_BLK4', - 'EFUSE_BLK5', 'EFUSE_BLK6', 'EFUSE_BLK7', 'EFUSE_BLK8', 'EFUSE_BLK9', - 'EFUSE_BLK10']: + if strval not in [ + 'EFUSE_BLK0', + 'EFUSE_BLK1', + 'EFUSE_BLK2', + 'EFUSE_BLK3', + 'EFUSE_BLK4', + 'EFUSE_BLK5', + 'EFUSE_BLK6', + 'EFUSE_BLK7', + 'EFUSE_BLK8', + 'EFUSE_BLK9', + 'EFUSE_BLK10', + ]: raise InputError("Field 'efuse_block' should be one of EFUSE_BLK0..EFUSE_BLK10") return strval def get_max_bits_of_block(self): - '''common_table: EFUSE_BLK0, EFUSE_BLK1, EFUSE_BLK2, EFUSE_BLK3 - custom_table: ----------, ----------, ----------, EFUSE_BLK3(some reserved in common_table) - ''' + """common_table: EFUSE_BLK0, EFUSE_BLK1, EFUSE_BLK2, EFUSE_BLK3 + custom_table: ----------, ----------, ----------, EFUSE_BLK3(some reserved in common_table) + """ + if idf_target == 'esp32s31': + if self.efuse_block == 'EFUSE_BLK0': + return 288 if self.efuse_block == 'EFUSE_BLK0': return 256 else: @@ -420,7 +450,10 @@ class FuseDefinition(object): raise ValidationError(self, 'bit_count field is not set') max_bits = self.get_max_bits_of_block() if self.bit_start + self.bit_count > max_bits: - raise ValidationError(self, 'The field is outside the boundaries(max_bits = %d) of the %s block' % (max_bits, self.efuse_block)) + raise ValidationError( + self, + f'The field is outside the boundaries(max_bits = {max_bits:d}) of the {self.efuse_block} block', + ) def get_bit_count(self, check_define=True): if check_define is True and self.define is not None: @@ -432,9 +465,9 @@ class FuseDefinition(object): start = ' {' if debug is True: start = ' {' + '"' + self.field_name + '" ,' - return ', '.join([start + self.efuse_block, - str(self.bit_start), - str(self.get_bit_count()) + '}, \t // ' + self.comment]) + return ', '.join( + [start + self.efuse_block, str(self.bit_start), str(self.get_bit_count()) + '}, \t // ' + self.comment] + ) def get_alt_names(self): result = re.search(r'^\[(.*?)\]', self.comment) @@ -445,8 +478,8 @@ class FuseDefinition(object): def process_input_file(file, type_table): status('Parsing efuse CSV input file ' + file.name + ' ...') - input = file.read() - table = FuseTable.from_csv(input) + input_contents = file.read() + table = FuseTable.from_csv(input_contents) status('Verifying efuse table...') table.verify(type_table) return table @@ -454,7 +487,7 @@ def process_input_file(file, type_table): def ckeck_md5_in_file(md5, filename): if os.path.exists(filename): - with open(filename, 'r', encoding='utf-8') as f: + with open(filename, encoding='utf-8') as f: for line in f: if md5 in line: return True @@ -501,16 +534,18 @@ def main(): parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true') parser.add_argument('--max_blk_len', help='Max number of bits in BLOCKs', type=int, default=256) parser.add_argument('common_input', help='Path to common CSV file to parse.', type=argparse.FileType('r')) - parser.add_argument('custom_input', help='Path to custom CSV file to parse.', type=argparse.FileType('r'), nargs='?', default=None) + parser.add_argument( + 'custom_input', help='Path to custom CSV file to parse.', type=argparse.FileType('r'), nargs='?', default=None + ) args = parser.parse_args() idf_target = args.idf_target max_blk_len = args.max_blk_len - print('Max number of bits in BLK %d' % (max_blk_len)) + print(f'Max number of bits in BLK {max_blk_len:d}') if max_blk_len not in [256, 192, 128]: - raise InputError('Unsupported block length = %d' % (max_blk_len)) + raise InputError(f'Unsupported block length = {max_blk_len:d}') quiet = args.quiet debug = args.debug @@ -536,12 +571,12 @@ def main(): class InputError(RuntimeError): def __init__(self, e): - super(InputError, self).__init__(e) + super().__init__(e) class ValidationError(InputError): def __init__(self, p, message): - super(ValidationError, self).__init__('Entry %s invalid: %s' % (p.field_name, message)) + super().__init__(f'Entry {p.field_name} invalid: {message}') if __name__ == '__main__': diff --git a/components/efuse/esp32s31/esp_efuse_table.c b/components/efuse/esp32s31/esp_efuse_table.c index c653670b6d9..061d95242d6 100644 --- a/components/efuse/esp32s31/esp_efuse_table.c +++ b/components/efuse/esp32s31/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 384d67c0f503bd731d01230c83b3d360 +// md5_digest_table 1cdb8731d5e8193ceb48139f9db95994 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -27,6 +27,10 @@ static const esp_efuse_desc_t WR_DIS_KM_RND_SWITCH_CYCLE[] = { {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_RND_SWITCH_CYCLE, }; +static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DISABLE_DEPLOY_MODE, +}; + static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE[] = { {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DEPLOY_ONLY_ONCE, }; @@ -39,18 +43,14 @@ static const esp_efuse_desc_t WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = { {EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY, }; -static const esp_efuse_desc_t WR_DIS_XTS_KEY_LENGTH_256[] = { - {EFUSE_BLK0, 1, 1}, // [] wr_dis of XTS_KEY_LENGTH_256, +static const esp_efuse_desc_t WR_DIS_KM_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_XTS_KEY_LENGTH_256, }; static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY[] = { {EFUSE_BLK0, 1, 1}, // [] wr_dis of LOCK_KM_KEY, }; -static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { - {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DISABLE_DEPLOY_MODE, -}; - static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, }; @@ -83,24 +83,8 @@ static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of WDT_DELAY_SEL, }; -static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of HYS_EN_PAD, -}; - -static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_0[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_0, -}; - -static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_1[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_1, -}; - -static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_2[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_2, -}; - -static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_3[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_3, +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, }; static const esp_efuse_desc_t WR_DIS_DIS_WDT[] = { @@ -111,8 +95,32 @@ static const esp_efuse_desc_t WR_DIS_DIS_SWD[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_SWD, }; -static const esp_efuse_desc_t WR_DIS_HP_PWR_SRC_SEL[] = { - {EFUSE_BLK0, 3, 1}, // [] wr_dis of HP_PWR_SRC_SEL, +static const esp_efuse_desc_t WR_DIS_PMU_FLASH_POWER_SEL[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of PMU_FLASH_POWER_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_PMU_FLASH_POWER_SEL_EN[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of PMU_FLASH_POWER_SEL_EN, +}; + +static const esp_efuse_desc_t WR_DIS_POWER_GLITCH_EN[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of POWER_GLITCH_EN, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_0_GLITCH_EN[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of PVT_0_GLITCH_EN, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_0_GLITCH_MODE[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of PVT_0_GLITCH_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_1_GLITCH_EN[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of PVT_1_GLITCH_EN, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_1_GLITCH_MODE[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of PVT_1_GLITCH_MODE, }; static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { @@ -151,16 +159,52 @@ static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = { {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4, }; -static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, +static const esp_efuse_desc_t WR_DIS_DIS_SM_CRYPT[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of DIS_SM_CRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of ECC_FORCE_CONST_TIME, +}; + +static const esp_efuse_desc_t WR_DIS_ECDSA_DISABLE_SOFT_K[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of ECDSA_DISABLE_SOFT_K, }; static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL, }; -static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = { - {EFUSE_BLK0, 14, 1}, // [] wr_dis of CRYPT_DPA_ENABLE, +static const esp_efuse_desc_t WR_DIS_XTS_DPA_CLK_ENABLE[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_CLK_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_PSEUDO_LEVEL, +}; + +static const esp_efuse_desc_t WR_DIS_RMA_NONCE_ENA[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of RMA_NONCE_ENA, +}; + +static const esp_efuse_desc_t WR_DIS_RMA_CHIP_INFO_SOURCE[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of RMA_CHIP_INFO_SOURCE, +}; + +static const esp_efuse_desc_t WR_DIS_RMA_DISABLE_FAST_VEF[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of RMA_DISABLE_FAST_VEF, +}; + +static const esp_efuse_desc_t WR_DIS_ENA_XTS_SHADOW[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of ENA_XTS_SHADOW, +}; + +static const esp_efuse_desc_t WR_DIS_ENA_SPI_BOOT_CRYPT_SCRAMBLER[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of ENA_SPI_BOOT_CRYPT_SCRAMBLER, +}; + +static const esp_efuse_desc_t WR_DIS_RE_ENABLE_JTAG_SOURCE[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of RE_ENABLE_JTAG_SOURCE, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { @@ -171,22 +215,10 @@ static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, }; -static const esp_efuse_desc_t WR_DIS_ECDSA_ENABLE_SOFT_K[] = { - {EFUSE_BLK0, 17, 1}, // [] wr_dis of ECDSA_ENABLE_SOFT_K, -}; - static const esp_efuse_desc_t WR_DIS_FLASH_TYPE[] = { {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TYPE, }; -static const esp_efuse_desc_t WR_DIS_FLASH_PAGE_SIZE[] = { - {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_PAGE_SIZE, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_ECC_EN[] = { - {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_EN, -}; - static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE, }; @@ -227,12 +259,8 @@ static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, }; -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, -}; - -static const esp_efuse_desc_t WR_DIS_KM_HUK_GEN_STATE[] = { - {EFUSE_BLK0, 19, 1}, // [] wr_dis of KM_HUK_GEN_STATE, +static const esp_efuse_desc_t WR_DIS_HUK_GEN_STATE[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of HUK_GEN_STATE, }; static const esp_efuse_desc_t WR_DIS_BLK1[] = { @@ -243,6 +271,10 @@ static const esp_efuse_desc_t WR_DIS_MAC[] = { {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, }; +static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, +}; + static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, }; @@ -287,122 +319,10 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; -static const esp_efuse_desc_t WR_DIS_LDO_VO1_DREF[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO1_DREF, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO2_DREF[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO2_DREF, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO1_MUL[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO1_MUL, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO2_MUL[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO2_MUL, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO3_K[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO3_K, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO3_VOS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO3_VOS, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO3_C[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO3_C, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO4_K[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO4_K, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO4_VOS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO4_VOS, -}; - -static const esp_efuse_desc_t WR_DIS_LDO_VO4_C[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LDO_VO4_C, -}; - -static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS, -}; - -static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS, -}; - -static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBIAS, -}; - -static const esp_efuse_desc_t WR_DIS_DSLP_DBG[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_DBG, -}; - -static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS, -}; - -static const esp_efuse_desc_t WR_DIS_LP_DCDC_DBIAS_VOL_GAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of LP_DCDC_DBIAS_VOL_GAP, -}; - static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_AVE_INITCODE_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_AVE_INITCODE_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_AVE_INITCODE_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_AVE_INITCODE_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3, -}; - static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, }; @@ -431,96 +351,12 @@ static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = { {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4, }; -static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = { - {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5, -}; - static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { - {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, + {EFUSE_BLK0, 28, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, }; -static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_HI_DOUT_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_HI_DOUT_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_HI_DOUT_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_HI_DOUT_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = { - {EFUSE_BLK0, 29, 1}, // [] wr_dis of TEMPERATURE_SENSOR, -}; - -static const esp_efuse_desc_t WR_DIS_USB_OTG11_EXCHG_PINS[] = { - {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_OTG11_EXCHG_PINS, -}; - -static const esp_efuse_desc_t WR_DIS_USB_PHY_SEL[] = { - {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_PHY_SEL, +static const esp_efuse_desc_t WR_DIS_USB_DEVICE_EXCHG_PINS[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of USB_DEVICE_EXCHG_PINS, }; static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { @@ -528,7 +364,7 @@ static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { }; static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-9, }; static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { @@ -551,160 +387,72 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, }; -static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = { - {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5, -}; - -static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { - {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_HI_DOUT_ATTEN0, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_HI_DOUT_ATTEN1, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_HI_DOUT_ATTEN2, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_HI_DOUT_ATTEN3, -}; - -static const esp_efuse_desc_t RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF, -}; - -static const esp_efuse_desc_t RD_DIS_TEMPERATURE_SENSOR[] = { - {EFUSE_BLK0, 38, 1}, // [] rd_dis of TEMPERATURE_SENSOR, -}; - static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 42, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = { - {EFUSE_BLK0, 43, 1}, // [] Represents whether USB-Serial_JTAG is disabled or enabled., + {EFUSE_BLK0, 42, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { - {EFUSE_BLK0, 45, 1}, // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download, + {EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_TWAI[] = { - {EFUSE_BLK0, 46, 1}, // [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 46, 1}, // [] Represents whether TWAI function is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 47, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 47, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled, }; static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled, + {EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way. Odd number: disabled Even number: enabled, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled, + {EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled, + {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled, }; -static const esp_efuse_desc_t KM_HUK_GEN_STATE[] = { - {EFUSE_BLK0, 55, 5}, // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, +static const esp_efuse_desc_t HUK_GEN_STATE[] = { + {EFUSE_BLK0, 55, 5}, // [] Represents the control of validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, }; static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = { - {EFUSE_BLK0, 64, 1}, // [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles, + {EFUSE_BLK0, 64, 1}, // [] Represents the control of key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles, }; static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = { - {EFUSE_BLK0, 66, 5}, // [] Represents whether the deploy mode of key manager is disabled or not, + {EFUSE_BLK0, 66, 5}, // [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & rma nonce; bit4: psram, }; static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = { - {EFUSE_BLK0, 71, 5}, // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds, + {EFUSE_BLK0, 71, 5}, // [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & rma nonce 4: psram, }; static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = { - {EFUSE_BLK0, 76, 5}, // [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds, + {EFUSE_BLK0, 76, 5}, // [] Represents whether corresponding key must come from key manager. 1 is true; 0 is false. 0: ecsda 1: flash 2: reserved 3: reserved 4: psram, }; static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = { - {EFUSE_BLK0, 81, 1}, // [] Set this bit to disable software written init key; and force use efuse_init_key, + {EFUSE_BLK0, 81, 1}, // [] Represents whether to disable software written init key; and force use efuse_init_key, }; -static const esp_efuse_desc_t XTS_KEY_LENGTH_256[] = { - {EFUSE_BLK0, 82, 1}, // [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key, +static const esp_efuse_desc_t KM_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 82, 1}, // [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 83, 1}, // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected, + {EFUSE_BLK0, 83, 1}, // [] Represents the threshold level of the RTC watchdog STG0 timeout.0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16, }; static const esp_efuse_desc_t DIS_SM_CRYPT[] = { - {EFUSE_BLK0, 84, 1}, // [] Set this bit to disable all the SM crypto functions, + {EFUSE_BLK0, 84, 1}, // [] Represents whether to disable all the SM crypto functions; including SM2; SM3. 1: disabled 0: enabled, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { @@ -744,11 +492,11 @@ static const esp_efuse_desc_t KEY_PURPOSE_4[] = { }; static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { - {EFUSE_BLK0, 121, 1}, // [] Represents whether permanently turn on ECC const-time mode, + {EFUSE_BLK0, 121, 1}, // [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off, }; -static const esp_efuse_desc_t ECDSA_ENABLE_SOFT_K[] = { - {EFUSE_BLK0, 122, 1}, // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used, +static const esp_efuse_desc_t ECDSA_DISABLE_SOFT_K[] = { + {EFUSE_BLK0, 122, 1}, // [] Represents whether permanently turn off ECDSA software set KEY. 1: turn off 0: turn on, }; static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { @@ -756,15 +504,15 @@ static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { }; static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { - {EFUSE_BLK0, 125, 1}, // [] Sets this bit to enable xts clock anti-dpa attack function, + {EFUSE_BLK0, 125, 1}, // [] Represents whether to enable xts clock anti-dpa attack function.0: Disabled. 1: Enabled, }; static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { - {EFUSE_BLK0, 128, 2}, // [] Sets this bit to control the xts pseudo-round anti-dpa sttack function, + {EFUSE_BLK0, 128, 2}, // [] Represents the control of the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 130, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 130, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { @@ -772,7 +520,7 @@ static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { }; static const esp_efuse_desc_t FLASH_TYPE[] = { - {EFUSE_BLK0, 133, 1}, // [] The type of interfaced flash. 0: four data lines; 1: eight data lines, + {EFUSE_BLK0, 133, 1}, // [] flash type: 0: nor flash; 1: nand flash, }; static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = { @@ -784,35 +532,35 @@ static const esp_efuse_desc_t FLASH_TPUW[] = { }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 144, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 144, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 145, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 145, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 146, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 146, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t LOCK_KM_KEY[] = { - {EFUSE_BLK0, 147, 1}, // [] Represents whether to lock the efuse xts key, + {EFUSE_BLK0, 147, 1}, // [] Represetns whether to lock the efuse xts key. 1. Lock 0: Unlock, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 148, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 148, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 149, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 149, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled 0: disabled, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 150, 2}, // [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing, + {EFUSE_BLK0, 150, 2}, // [] Represents the type of UART printing. 00: force enable printing 01: enable printing when GPIO8 is reset at low level 10: enable printing when GPIO8 is reset at high level 11: force disable printing, }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 152, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced, + {EFUSE_BLK0, 152, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced 0:not forced, }; static const esp_efuse_desc_t SECURE_VERSION[] = { @@ -820,15 +568,15 @@ static const esp_efuse_desc_t SECURE_VERSION[] = { }; static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 176, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 176, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t HYS_EN_PAD[] = { - {EFUSE_BLK0, 177, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled, + {EFUSE_BLK0, 177, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled 0:disabled, }; static const esp_efuse_desc_t DCDC_VSET_EN[] = { - {EFUSE_BLK0, 194, 1}, // [] Set the dcdc voltage default, + {EFUSE_BLK0, 194, 1}, // [] Select dcdc vset use efuse_dcdc_vset, }; static const esp_efuse_desc_t DIS_WDT[] = { @@ -840,27 +588,27 @@ static const esp_efuse_desc_t DIS_SWD[] = { }; static const esp_efuse_desc_t SECURE_BOOT_SHA384_EN[] = { - {EFUSE_BLK0, 203, 1}, // [] Represents whether secure boot using SHA-384 is enabled, + {EFUSE_BLK0, 203, 1}, // [] Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable, }; static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = { - {EFUSE_BLK0, 204, 4}, // [] Represents the anti-rollback secure version of th2 2nd stage bootloader, + {EFUSE_BLK0, 204, 4}, // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader, }; static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_EN[] = { - {EFUSE_BLK0, 208, 1}, // [] Represents whether the anti-rollback check for the 2nd stage bootloader is enabled, + {EFUSE_BLK0, 208, 1}, // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled, }; static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = { - {EFUSE_BLK0, 209, 1}, // [] Represents whether the anti-rollback SECURE_VERSION will be updated from the rom bootloader, + {EFUSE_BLK0, 209, 1}, // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable, }; static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { - {EFUSE_BLK0, 210, 12}, // [] Represents the starting flash sector of the recovery bootloader, + {EFUSE_BLK0, 210, 12}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, }; -static const esp_efuse_desc_t RMA_EN[] = { - {EFUSE_BLK0, 222, 2}, // [] Represents whether rma function is supported in download mode, +static const esp_efuse_desc_t RMA_ENA[] = { + {EFUSE_BLK0, 222, 2}, // [] Represents whether rma function is supported in download mode. 2'b01/2'b10: enabled2'b00/2'b11: disabled, }; static const esp_efuse_desc_t RMA_SESSION_COUNTER[] = { @@ -868,15 +616,55 @@ static const esp_efuse_desc_t RMA_SESSION_COUNTER[] = { }; static const esp_efuse_desc_t RMA_NONCE_ENA[] = { - {EFUSE_BLK0, 227, 2}, // [] Represents random number NONCE is used in RMA and whether the KM is used to generate the NONCE, + {EFUSE_BLK0, 227, 2}, // [] Represents whether random number NONCE is used in RMA and whether the KM module is used to generate the NONCE. 2'bx0: No NONCE 2'b1x: Use KM generate NONCE., }; static const esp_efuse_desc_t RMA_CHIP_INFO_SOURCE[] = { - {EFUSE_BLK0, 229, 1}, // [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA, + {EFUSE_BLK0, 229, 1}, // [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA.1: use HUK_info 0: use UNIQ_id, }; static const esp_efuse_desc_t RMA_DISABLE_FAST_VEF[] = { - {EFUSE_BLK0, 230, 1}, // [] Represents whether disable FAST_VEF in RMA session, + {EFUSE_BLK0, 230, 1}, // [] Represents whether disable FAST_VEF in RMA session.1: disable0: enable, +}; + +static const esp_efuse_desc_t PVT_0_GLITCH_EN[] = { + {EFUSE_BLK0, 231, 1}, // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable, +}; + +static const esp_efuse_desc_t PVT_0_GLITCH_MODE[] = { + {EFUSE_BLK0, 232, 2}, // [] Use to configure glitch mode, +}; + +static const esp_efuse_desc_t PVT_1_GLITCH_EN[] = { + {EFUSE_BLK0, 234, 1}, // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable, +}; + +static const esp_efuse_desc_t PVT_1_GLITCH_MODE[] = { + {EFUSE_BLK0, 235, 2}, // [] Use to configure glitch mode, +}; + +static const esp_efuse_desc_t PMU_FLASH_POWER_SEL[] = { + {EFUSE_BLK0, 237, 1}, // [] FLASH power select. 1'b1: use 3.3V1'b0: use 1.8V, +}; + +static const esp_efuse_desc_t PMU_FLASH_POWER_SEL_EN[] = { + {EFUSE_BLK0, 238, 1}, // [] FLASH power select enable signal. 1'b1 : validates EFUSE_PMU_FLASH_POWER_SEL 1'b0: invalidates EFUSE_PMU_FLASH_POWER_SEL, +}; + +static const esp_efuse_desc_t POWER_GLITCH_EN[] = { + {EFUSE_BLK0, 239, 4}, // [] set these bit enable power glitch enable, +}; + +static const esp_efuse_desc_t ENA_XTS_SHADOW[] = { + {EFUSE_BLK0, 243, 1}, // [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled, +}; + +static const esp_efuse_desc_t ENA_SPI_BOOT_CRYPT_SCRAMBLER[] = { + {EFUSE_BLK0, 244, 1}, // [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled, +}; + +static const esp_efuse_desc_t RE_ENABLE_JTAG_SOURCE[] = { + {EFUSE_BLK0, 245, 1}, // [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: RMA 1: HMAC, }; static const esp_efuse_desc_t MAC[] = { @@ -888,162 +676,55 @@ static const esp_efuse_desc_t MAC[] = { {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, }; +static const esp_efuse_desc_t MAC_EXT[] = { + {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address, + {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address, +}; + static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 64, 4}, // [] Minor chip version, + {EFUSE_BLK1, 114, 4}, // [] Minor chip version, }; static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 68, 2}, // [] Major chip version, + {EFUSE_BLK1, 118, 2}, // [] Major chip version, }; static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 70, 1}, // [] Disables check of wafer version major, + {EFUSE_BLK1, 120, 1}, // [] Disables check of wafer version major, }; static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK1, 71, 1}, // [] Disables check of blk version major, + {EFUSE_BLK1, 121, 1}, // [] Disables check of blk version major, }; static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK1, 72, 3}, // [] BLK_VERSION_MINOR of BLOCK2, + {EFUSE_BLK1, 122, 3}, // [] BLK_VERSION_MINOR of BLOCK2, }; static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, + {EFUSE_BLK1, 125, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, }; static const esp_efuse_desc_t PSRAM_CAP[] = { - {EFUSE_BLK1, 77, 3}, // [] PSRAM capacity, + {EFUSE_BLK1, 127, 3}, // [] Psram capacity, }; static const esp_efuse_desc_t TEMP[] = { - {EFUSE_BLK1, 80, 2}, // [] Operating temperature of the ESP chip, + {EFUSE_BLK1, 130, 2}, // [] Maximum ambient temperature that ESP Chip can work properly, }; static const esp_efuse_desc_t PSRAM_VENDOR[] = { - {EFUSE_BLK1, 82, 2}, // [] PSRAM vendor, + {EFUSE_BLK1, 132, 2}, // [] Psram vendor, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 84, 3}, // [] Package version, -}; - -static const esp_efuse_desc_t LDO_VO1_DREF[] = { - {EFUSE_BLK1, 88, 4}, // [] Output VO1 parameter, -}; - -static const esp_efuse_desc_t LDO_VO2_DREF[] = { - {EFUSE_BLK1, 92, 4}, // [] Output VO2 parameter, -}; - -static const esp_efuse_desc_t LDO_VO1_MUL[] = { - {EFUSE_BLK1, 96, 3}, // [] Output VO1 parameter, -}; - -static const esp_efuse_desc_t LDO_VO2_MUL[] = { - {EFUSE_BLK1, 99, 3}, // [] Output VO2 parameter, -}; - -static const esp_efuse_desc_t LDO_VO3_K[] = { - {EFUSE_BLK1, 102, 8}, // [] Output VO3 calibration parameter, -}; - -static const esp_efuse_desc_t LDO_VO3_VOS[] = { - {EFUSE_BLK1, 110, 6}, // [] Output VO3 calibration parameter, -}; - -static const esp_efuse_desc_t LDO_VO3_C[] = { - {EFUSE_BLK1, 116, 6}, // [] Output VO3 calibration parameter, -}; - -static const esp_efuse_desc_t LDO_VO4_K[] = { - {EFUSE_BLK1, 122, 8}, // [] Output VO4 calibration parameter, -}; - -static const esp_efuse_desc_t LDO_VO4_VOS[] = { - {EFUSE_BLK1, 130, 6}, // [] Output VO4 calibration parameter, -}; - -static const esp_efuse_desc_t LDO_VO4_C[] = { - {EFUSE_BLK1, 136, 6}, // [] Output VO4 calibration parameter, -}; - -static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = { - {EFUSE_BLK1, 144, 4}, // [] Active HP DBIAS of fixed voltage, -}; - -static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = { - {EFUSE_BLK1, 148, 4}, // [] Active LP DBIAS of fixed voltage, -}; - -static const esp_efuse_desc_t LSLP_HP_DBIAS[] = { - {EFUSE_BLK1, 152, 4}, // [] LSLP HP DBIAS of fixed voltage, -}; - -static const esp_efuse_desc_t DSLP_DBG[] = { - {EFUSE_BLK1, 156, 4}, // [] DSLP BDG of fixed voltage, -}; - -static const esp_efuse_desc_t DSLP_LP_DBIAS[] = { - {EFUSE_BLK1, 160, 5}, // [] DSLP LP DBIAS of fixed voltage, -}; - -static const esp_efuse_desc_t LP_DCDC_DBIAS_VOL_GAP[] = { - {EFUSE_BLK1, 165, 5}, // [] DBIAS gap between LP and DCDC, + {EFUSE_BLK1, 134, 2}, // [] Package version, }; static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, }; -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = { - {EFUSE_BLK2, 128, 10}, // [] Average initcode of ADC1 atten0, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = { - {EFUSE_BLK2, 138, 10}, // [] Average initcode of ADC1 atten1, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = { - {EFUSE_BLK2, 148, 10}, // [] Average initcode of ADC1 atten2, -}; - -static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = { - {EFUSE_BLK2, 158, 10}, // [] Average initcode of ADC1 atten3, -}; - -static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN0[] = { - {EFUSE_BLK2, 168, 10}, // [] Average initcode of ADC2 atten0, -}; - -static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN1[] = { - {EFUSE_BLK2, 178, 10}, // [] Average initcode of ADC2 atten1, -}; - -static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN2[] = { - {EFUSE_BLK2, 188, 10}, // [] Average initcode of ADC2 atten2, -}; - -static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN3[] = { - {EFUSE_BLK2, 198, 10}, // [] Average initcode of ADC2 atten3, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK2, 208, 10}, // [] HI_DOUT of ADC1 atten0, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK2, 218, 10}, // [] HI_DOUT of ADC1 atten1, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK2, 228, 10}, // [] HI_DOUT of ADC1 atten2, -}; - -static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK2, 238, 10}, // [] HI_DOUT of ADC1 atten3, -}; - static const esp_efuse_desc_t USER_DATA[] = { {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, }; @@ -1072,80 +753,12 @@ static const esp_efuse_desc_t KEY4[] = { {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, }; -static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN0[] = { - {EFUSE_BLK9, 0, 10}, // [] HI_DOUT of ADC2 atten0, +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK9, 0, 32}, // [BLOCK_SYS_DATA2] System data part 2 (reserved), }; -static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN1[] = { - {EFUSE_BLK9, 10, 10}, // [] HI_DOUT of ADC2 atten1, -}; - -static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN2[] = { - {EFUSE_BLK9, 20, 10}, // [] HI_DOUT of ADC2 atten2, -}; - -static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN3[] = { - {EFUSE_BLK9, 30, 10}, // [] HI_DOUT of ADC2 atten3, -}; - -static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 40, 4}, // [] Gap between ADC1_ch0 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 44, 4}, // [] Gap between ADC1_ch1 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 48, 4}, // [] Gap between ADC1_ch2 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 52, 4}, // [] Gap between ADC1_ch3 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 56, 4}, // [] Gap between ADC1_ch4 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 60, 4}, // [] Gap between ADC1_ch5 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH6_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 64, 4}, // [] Gap between ADC1_ch6 and average initcode, -}; - -static const esp_efuse_desc_t ADC1_CH7_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 68, 4}, // [] Gap between ADC1_ch7 and average initcode, -}; - -static const esp_efuse_desc_t ADC2_CH0_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 72, 4}, // [] Gap between ADC2_ch0 and average initcode, -}; - -static const esp_efuse_desc_t ADC2_CH1_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 76, 4}, // [] Gap between ADC2_ch1 and average initcode, -}; - -static const esp_efuse_desc_t ADC2_CH2_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 80, 4}, // [] Gap between ADC2_ch2 and average initcode, -}; - -static const esp_efuse_desc_t ADC2_CH3_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 84, 4}, // [] Gap between ADC2_ch3 and average initcode, -}; - -static const esp_efuse_desc_t ADC2_CH4_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 88, 4}, // [] Gap between ADC2_ch4 and average initcode, -}; - -static const esp_efuse_desc_t ADC2_CH5_ATTEN0_INITCODE_DIFF[] = { - {EFUSE_BLK9, 92, 4}, // [] Gap between ADC2_ch5 and average initcode, -}; - -static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = { - {EFUSE_BLK9, 96, 9}, // [] Temperature calibration data, +static const esp_efuse_desc_t USB_DEVICE_EXCHG_PINS[] = { + {EFUSE_BLK9, 192, 1}, // [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled, }; @@ -1167,6 +780,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { + &WR_DIS_KM_DISABLE_DEPLOY_MODE[0], // [] wr_dis of KM_DISABLE_DEPLOY_MODE + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[] = { &WR_DIS_KM_DEPLOY_ONLY_ONCE[0], // [] wr_dis of KM_DEPLOY_ONLY_ONCE NULL @@ -1182,8 +800,8 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[] = { - &WR_DIS_XTS_KEY_LENGTH_256[0], // [] wr_dis of XTS_KEY_LENGTH_256 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[] = { + &WR_DIS_KM_XTS_KEY_LENGTH_256[0], // [] wr_dis of KM_XTS_KEY_LENGTH_256 NULL }; @@ -1192,11 +810,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { - &WR_DIS_KM_DISABLE_DEPLOY_MODE[0], // [] wr_dis of KM_DISABLE_DEPLOY_MODE - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG NULL @@ -1237,28 +850,8 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = { - &WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[] = { - &WR_DIS_PXA0_TIEH_SEL_0[0], // [] wr_dis of PXA0_TIEH_SEL_0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[] = { - &WR_DIS_PXA0_TIEH_SEL_1[0], // [] wr_dis of PXA0_TIEH_SEL_1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[] = { - &WR_DIS_PXA0_TIEH_SEL_2[0], // [] wr_dis of PXA0_TIEH_SEL_2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[] = { - &WR_DIS_PXA0_TIEH_SEL_3[0], // [] wr_dis of PXA0_TIEH_SEL_3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE NULL }; @@ -1272,8 +865,38 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[] = { - &WR_DIS_HP_PWR_SRC_SEL[0], // [] wr_dis of HP_PWR_SRC_SEL +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PMU_FLASH_POWER_SEL[] = { + &WR_DIS_PMU_FLASH_POWER_SEL[0], // [] wr_dis of PMU_FLASH_POWER_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PMU_FLASH_POWER_SEL_EN[] = { + &WR_DIS_PMU_FLASH_POWER_SEL_EN[0], // [] wr_dis of PMU_FLASH_POWER_SEL_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWER_GLITCH_EN[] = { + &WR_DIS_POWER_GLITCH_EN[0], // [] wr_dis of POWER_GLITCH_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_0_GLITCH_EN[] = { + &WR_DIS_PVT_0_GLITCH_EN[0], // [] wr_dis of PVT_0_GLITCH_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_0_GLITCH_MODE[] = { + &WR_DIS_PVT_0_GLITCH_MODE[0], // [] wr_dis of PVT_0_GLITCH_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_1_GLITCH_EN[] = { + &WR_DIS_PVT_1_GLITCH_EN[0], // [] wr_dis of PVT_1_GLITCH_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_1_GLITCH_MODE[] = { + &WR_DIS_PVT_1_GLITCH_MODE[0], // [] wr_dis of PVT_1_GLITCH_MODE NULL }; @@ -1322,8 +945,18 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { - &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SM_CRYPT[] = { + &WR_DIS_DIS_SM_CRYPT[0], // [] wr_dis of DIS_SM_CRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = { + &WR_DIS_ECC_FORCE_CONST_TIME[0], // [] wr_dis of ECC_FORCE_CONST_TIME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_SOFT_K[] = { + &WR_DIS_ECDSA_DISABLE_SOFT_K[0], // [] wr_dis of ECDSA_DISABLE_SOFT_K NULL }; @@ -1332,8 +965,43 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = { - &WR_DIS_CRYPT_DPA_ENABLE[0], // [] wr_dis of CRYPT_DPA_ENABLE +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[] = { + &WR_DIS_XTS_DPA_CLK_ENABLE[0], // [] wr_dis of XTS_DPA_CLK_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { + &WR_DIS_XTS_DPA_PSEUDO_LEVEL[0], // [] wr_dis of XTS_DPA_PSEUDO_LEVEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_NONCE_ENA[] = { + &WR_DIS_RMA_NONCE_ENA[0], // [] wr_dis of RMA_NONCE_ENA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_CHIP_INFO_SOURCE[] = { + &WR_DIS_RMA_CHIP_INFO_SOURCE[0], // [] wr_dis of RMA_CHIP_INFO_SOURCE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_DISABLE_FAST_VEF[] = { + &WR_DIS_RMA_DISABLE_FAST_VEF[0], // [] wr_dis of RMA_DISABLE_FAST_VEF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENA_XTS_SHADOW[] = { + &WR_DIS_ENA_XTS_SHADOW[0], // [] wr_dis of ENA_XTS_SHADOW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENA_SPI_BOOT_CRYPT_SCRAMBLER[] = { + &WR_DIS_ENA_SPI_BOOT_CRYPT_SCRAMBLER[0], // [] wr_dis of ENA_SPI_BOOT_CRYPT_SCRAMBLER + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RE_ENABLE_JTAG_SOURCE[] = { + &WR_DIS_RE_ENABLE_JTAG_SOURCE[0], // [] wr_dis of RE_ENABLE_JTAG_SOURCE NULL }; @@ -1347,26 +1015,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[] = { - &WR_DIS_ECDSA_ENABLE_SOFT_K[0], // [] wr_dis of ECDSA_ENABLE_SOFT_K - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[] = { &WR_DIS_FLASH_TYPE[0], // [] wr_dis of FLASH_TYPE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[] = { - &WR_DIS_FLASH_PAGE_SIZE[0], // [] wr_dis of FLASH_PAGE_SIZE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[] = { - &WR_DIS_FLASH_ECC_EN[0], // [] wr_dis of FLASH_ECC_EN - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { &WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE NULL @@ -1417,13 +1070,8 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[] = { - &WR_DIS_KM_HUK_GEN_STATE[0], // [] wr_dis of KM_HUK_GEN_STATE +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[] = { + &WR_DIS_HUK_GEN_STATE[0], // [] wr_dis of HUK_GEN_STATE NULL }; @@ -1437,6 +1085,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { + &WR_DIS_MAC_EXT[0], // [] wr_dis of MAC_EXT + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR NULL @@ -1492,151 +1145,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[] = { - &WR_DIS_LDO_VO1_DREF[0], // [] wr_dis of LDO_VO1_DREF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[] = { - &WR_DIS_LDO_VO2_DREF[0], // [] wr_dis of LDO_VO2_DREF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[] = { - &WR_DIS_LDO_VO1_MUL[0], // [] wr_dis of LDO_VO1_MUL - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[] = { - &WR_DIS_LDO_VO2_MUL[0], // [] wr_dis of LDO_VO2_MUL - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[] = { - &WR_DIS_LDO_VO3_K[0], // [] wr_dis of LDO_VO3_K - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[] = { - &WR_DIS_LDO_VO3_VOS[0], // [] wr_dis of LDO_VO3_VOS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[] = { - &WR_DIS_LDO_VO3_C[0], // [] wr_dis of LDO_VO3_C - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[] = { - &WR_DIS_LDO_VO4_K[0], // [] wr_dis of LDO_VO4_K - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[] = { - &WR_DIS_LDO_VO4_VOS[0], // [] wr_dis of LDO_VO4_VOS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[] = { - &WR_DIS_LDO_VO4_C[0], // [] wr_dis of LDO_VO4_C - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = { - &WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = { - &WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = { - &WR_DIS_LSLP_HP_DBIAS[0], // [] wr_dis of LSLP_HP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[] = { - &WR_DIS_DSLP_DBG[0], // [] wr_dis of DSLP_DBG - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = { - &WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[] = { - &WR_DIS_LP_DCDC_DBIAS_VOL_GAP[0], // [] wr_dis of LP_DCDC_DBIAS_VOL_GAP - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = { - &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[] = { - &WR_DIS_ADC2_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC2_AVE_INITCODE_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[] = { - &WR_DIS_ADC2_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC2_AVE_INITCODE_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[] = { - &WR_DIS_ADC2_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC2_AVE_INITCODE_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[] = { - &WR_DIS_ADC2_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC2_AVE_INITCODE_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { - &WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3 - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA NULL @@ -1672,118 +1185,13 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = { - &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[] = { - &WR_DIS_ADC2_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC2_HI_DOUT_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[] = { - &WR_DIS_ADC2_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC2_HI_DOUT_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[] = { - &WR_DIS_ADC2_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC2_HI_DOUT_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[] = { - &WR_DIS_ADC2_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC2_HI_DOUT_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = { - &WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = { - &WR_DIS_TEMPERATURE_SENSOR[0], // [] wr_dis of TEMPERATURE_SENSOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[] = { - &WR_DIS_USB_OTG11_EXCHG_PINS[0], // [] wr_dis of USB_OTG11_EXCHG_PINS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = { - &WR_DIS_USB_PHY_SEL[0], // [] wr_dis of USB_PHY_SEL +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[] = { + &WR_DIS_USB_DEVICE_EXCHG_PINS[0], // [] wr_dis of USB_DEVICE_EXCHG_PINS NULL }; @@ -1793,7 +1201,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // [] Disable reading from BlOCK4-10 + &RD_DIS[0], // [] Disable reading from BlOCK4-9 NULL }; @@ -1822,198 +1230,88 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = { - &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { - &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[] = { - &RD_DIS_ADC2_HI_DOUT_ATTEN0[0], // [] rd_dis of ADC2_HI_DOUT_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[] = { - &RD_DIS_ADC2_HI_DOUT_ATTEN1[0], // [] rd_dis of ADC2_HI_DOUT_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[] = { - &RD_DIS_ADC2_HI_DOUT_ATTEN2[0], // [] rd_dis of ADC2_HI_DOUT_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[] = { - &RD_DIS_ADC2_HI_DOUT_ATTEN3[0], // [] rd_dis of ADC2_HI_DOUT_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = { - &RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[0], // [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[] = { - &RD_DIS_TEMPERATURE_SENSOR[0], // [] rd_dis of TEMPERATURE_SENSOR - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = { - &DIS_USB_SERIAL_JTAG[0], // [] Represents whether USB-Serial_JTAG is disabled or enabled. + &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { - &SPI_DOWNLOAD_MSPI_DIS[0], // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { - &DIS_TWAI[0], // [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled + &DIS_TWAI[0], // [] Represents whether TWAI function is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled + &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled + &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way. Odd number: disabled Even number: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled + &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled NULL }; -const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[] = { - &KM_HUK_GEN_STATE[0], // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid +const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[] = { + &HUK_GEN_STATE[0], // [] Represents the control of validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid NULL }; const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = { - &KM_RND_SWITCH_CYCLE[0], // [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles + &KM_RND_SWITCH_CYCLE[0], // [] Represents the control of key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles NULL }; const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = { - &KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the deploy mode of key manager is disabled or not + &KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & rma nonce; bit4: psram NULL }; const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = { - &KM_DEPLOY_ONLY_ONCE[0], // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds + &KM_DEPLOY_ONLY_ONCE[0], // [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & rma nonce 4: psram NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = { - &FORCE_USE_KEY_MANAGER_KEY[0], // [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds + &FORCE_USE_KEY_MANAGER_KEY[0], // [] Represents whether corresponding key must come from key manager. 1 is true; 0 is false. 0: ecsda 1: flash 2: reserved 3: reserved 4: psram NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = { - &FORCE_DISABLE_SW_INIT_KEY[0], // [] Set this bit to disable software written init key; and force use efuse_init_key + &FORCE_DISABLE_SW_INIT_KEY[0], // [] Represents whether to disable software written init key; and force use efuse_init_key NULL }; -const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[] = { - &XTS_KEY_LENGTH_256[0], // [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key +const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[] = { + &KM_XTS_KEY_LENGTH_256[0], // [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected + &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout.0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_SM_CRYPT[] = { - &DIS_SM_CRYPT[0], // [] Set this bit to disable all the SM crypto functions + &DIS_SM_CRYPT[0], // [] Represents whether to disable all the SM crypto functions; including SM2; SM3. 1: disabled 0: enabled NULL }; @@ -2063,12 +1361,12 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { }; const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { - &ECC_FORCE_CONST_TIME[0], // [] Represents whether permanently turn on ECC const-time mode + &ECC_FORCE_CONST_TIME[0], // [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[] = { - &ECDSA_ENABLE_SOFT_K[0], // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used +const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_SOFT_K[] = { + &ECDSA_DISABLE_SOFT_K[0], // [] Represents whether permanently turn off ECDSA software set KEY. 1: turn off 0: turn on NULL }; @@ -2078,17 +1376,17 @@ const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { - &XTS_DPA_CLK_ENABLE[0], // [] Sets this bit to enable xts clock anti-dpa attack function + &XTS_DPA_CLK_ENABLE[0], // [] Represents whether to enable xts clock anti-dpa attack function.0: Disabled. 1: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { - &XTS_DPA_PSEUDO_LEVEL[0], // [] Sets this bit to control the xts pseudo-round anti-dpa sttack function + &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the control of the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled + &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled NULL }; @@ -2098,7 +1396,7 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = { - &FLASH_TYPE[0], // [] The type of interfaced flash. 0: four data lines; 1: eight data lines + &FLASH_TYPE[0], // [] flash type: 0: nor flash; 1: nand flash NULL }; @@ -2113,42 +1411,42 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = { - &LOCK_KM_KEY[0], // [] Represents whether to lock the efuse xts key + &LOCK_KM_KEY[0], // [] Represetns whether to lock the efuse xts key. 1. Lock 0: Unlock NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing + &UART_PRINT_CONTROL[0], // [] Represents the type of UART printing. 00: force enable printing 01: enable printing when GPIO8 is reset at low level 10: enable printing when GPIO8 is reset at high level 11: force disable printing NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced + &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced 0:not forced NULL }; @@ -2158,17 +1456,17 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled + &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { - &HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled + &HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled 0:disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[] = { - &DCDC_VSET_EN[0], // [] Set the dcdc voltage default + &DCDC_VSET_EN[0], // [] Select dcdc vset use efuse_dcdc_vset NULL }; @@ -2183,32 +1481,32 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[] = { - &SECURE_BOOT_SHA384_EN[0], // [] Represents whether secure boot using SHA-384 is enabled + &SECURE_BOOT_SHA384_EN[0], // [] Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = { - &BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[0], // [] Represents the anti-rollback secure version of th2 2nd stage bootloader + &BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[0], // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader NULL }; const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[] = { - &BOOTLOADER_ANTI_ROLLBACK_EN[0], // [] Represents whether the anti-rollback check for the 2nd stage bootloader is enabled + &BOOTLOADER_ANTI_ROLLBACK_EN[0], // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = { - &BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[0], // [] Represents whether the anti-rollback SECURE_VERSION will be updated from the rom bootloader + &BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[0], // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable NULL }; const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { - &RECOVERY_BOOTLOADER_FLASH_SECTOR[0], // [] Represents the starting flash sector of the recovery bootloader + &RECOVERY_BOOTLOADER_FLASH_SECTOR[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RMA_EN[] = { - &RMA_EN[0], // [] Represents whether rma function is supported in download mode +const esp_efuse_desc_t* ESP_EFUSE_RMA_ENA[] = { + &RMA_ENA[0], // [] Represents whether rma function is supported in download mode. 2'b01/2'b10: enabled2'b00/2'b11: disabled NULL }; @@ -2218,17 +1516,67 @@ const esp_efuse_desc_t* ESP_EFUSE_RMA_SESSION_COUNTER[] = { }; const esp_efuse_desc_t* ESP_EFUSE_RMA_NONCE_ENA[] = { - &RMA_NONCE_ENA[0], // [] Represents random number NONCE is used in RMA and whether the KM is used to generate the NONCE + &RMA_NONCE_ENA[0], // [] Represents whether random number NONCE is used in RMA and whether the KM module is used to generate the NONCE. 2'bx0: No NONCE 2'b1x: Use KM generate NONCE. NULL }; const esp_efuse_desc_t* ESP_EFUSE_RMA_CHIP_INFO_SOURCE[] = { - &RMA_CHIP_INFO_SOURCE[0], // [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA + &RMA_CHIP_INFO_SOURCE[0], // [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA.1: use HUK_info 0: use UNIQ_id NULL }; const esp_efuse_desc_t* ESP_EFUSE_RMA_DISABLE_FAST_VEF[] = { - &RMA_DISABLE_FAST_VEF[0], // [] Represents whether disable FAST_VEF in RMA session + &RMA_DISABLE_FAST_VEF[0], // [] Represents whether disable FAST_VEF in RMA session.1: disable0: enable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_EN[] = { + &PVT_0_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_MODE[] = { + &PVT_0_GLITCH_MODE[0], // [] Use to configure glitch mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_1_GLITCH_EN[] = { + &PVT_1_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_1_GLITCH_MODE[] = { + &PVT_1_GLITCH_MODE[0], // [] Use to configure glitch mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PMU_FLASH_POWER_SEL[] = { + &PMU_FLASH_POWER_SEL[0], // [] FLASH power select. 1'b1: use 3.3V1'b0: use 1.8V + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PMU_FLASH_POWER_SEL_EN[] = { + &PMU_FLASH_POWER_SEL_EN[0], // [] FLASH power select enable signal. 1'b1 : validates EFUSE_PMU_FLASH_POWER_SEL 1'b0: invalidates EFUSE_PMU_FLASH_POWER_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_EN[] = { + &POWER_GLITCH_EN[0], // [] set these bit enable power glitch enable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ENA_XTS_SHADOW[] = { + &ENA_XTS_SHADOW[0], // [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER[] = { + &ENA_SPI_BOOT_CRYPT_SCRAMBLER[0], // [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RE_ENABLE_JTAG_SOURCE[] = { + &RE_ENABLE_JTAG_SOURCE[0], // [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: RMA 1: HMAC NULL }; @@ -2242,11 +1590,6 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { NULL }; -static const esp_efuse_desc_t MAC_EXT[] = { - {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address, - {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address, -}; - const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { &MAC_EXT[0], // [] Stores the extended bits of MAC address &MAC_EXT[1], // [] Stores the extended bits of MAC address @@ -2284,17 +1627,17 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { }; const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = { - &PSRAM_CAP[0], // [] PSRAM capacity + &PSRAM_CAP[0], // [] Psram capacity NULL }; const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = { - &TEMP[0], // [] Operating temperature of the ESP chip + &TEMP[0], // [] Maximum ambient temperature that ESP Chip can work properly NULL }; const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = { - &PSRAM_VENDOR[0], // [] PSRAM vendor + &PSRAM_VENDOR[0], // [] Psram vendor NULL }; @@ -2303,151 +1646,11 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[] = { - &LDO_VO1_DREF[0], // [] Output VO1 parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[] = { - &LDO_VO2_DREF[0], // [] Output VO2 parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[] = { - &LDO_VO1_MUL[0], // [] Output VO1 parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[] = { - &LDO_VO2_MUL[0], // [] Output VO2 parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[] = { - &LDO_VO3_K[0], // [] Output VO3 calibration parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[] = { - &LDO_VO3_VOS[0], // [] Output VO3 calibration parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[] = { - &LDO_VO3_C[0], // [] Output VO3 calibration parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[] = { - &LDO_VO4_K[0], // [] Output VO4 calibration parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[] = { - &LDO_VO4_VOS[0], // [] Output VO4 calibration parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[] = { - &LDO_VO4_C[0], // [] Output VO4 calibration parameter - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = { - &ACTIVE_HP_DBIAS[0], // [] Active HP DBIAS of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = { - &ACTIVE_LP_DBIAS[0], // [] Active LP DBIAS of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = { - &LSLP_HP_DBIAS[0], // [] LSLP HP DBIAS of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[] = { - &DSLP_DBG[0], // [] DSLP BDG of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = { - &DSLP_LP_DBIAS[0], // [] DSLP LP DBIAS of fixed voltage - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[] = { - &LP_DCDC_DBIAS_VOL_GAP[0], // [] DBIAS gap between LP and DCDC - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = { - &ADC1_AVE_INITCODE_ATTEN0[0], // [] Average initcode of ADC1 atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = { - &ADC1_AVE_INITCODE_ATTEN1[0], // [] Average initcode of ADC1 atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = { - &ADC1_AVE_INITCODE_ATTEN2[0], // [] Average initcode of ADC1 atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = { - &ADC1_AVE_INITCODE_ATTEN3[0], // [] Average initcode of ADC1 atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[] = { - &ADC2_AVE_INITCODE_ATTEN0[0], // [] Average initcode of ADC2 atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[] = { - &ADC2_AVE_INITCODE_ATTEN1[0], // [] Average initcode of ADC2 atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[] = { - &ADC2_AVE_INITCODE_ATTEN2[0], // [] Average initcode of ADC2 atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[] = { - &ADC2_AVE_INITCODE_ATTEN3[0], // [] Average initcode of ADC2 atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = { - &ADC1_HI_DOUT_ATTEN0[0], // [] HI_DOUT of ADC1 atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = { - &ADC1_HI_DOUT_ATTEN1[0], // [] HI_DOUT of ADC1 atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = { - &ADC1_HI_DOUT_ATTEN2[0], // [] HI_DOUT of ADC1 atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = { - &ADC1_HI_DOUT_ATTEN3[0], // [] HI_DOUT of ADC1 atten3 - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { &USER_DATA[0], // [BLOCK_USR_DATA] User data NULL @@ -2483,97 +1686,12 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[] = { - &ADC2_HI_DOUT_ATTEN0[0], // [] HI_DOUT of ADC2 atten0 +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[] = { - &ADC2_HI_DOUT_ATTEN1[0], // [] HI_DOUT of ADC2 atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[] = { - &ADC2_HI_DOUT_ATTEN2[0], // [] HI_DOUT of ADC2 atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[] = { - &ADC2_HI_DOUT_ATTEN3[0], // [] HI_DOUT of ADC2 atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1_ch0 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1_ch1 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1_ch2 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1_ch3 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1_ch4 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1_ch5 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH6_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1_ch6 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = { - &ADC1_CH7_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1_ch7 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = { - &ADC2_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC2_ch0 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = { - &ADC2_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC2_ch1 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = { - &ADC2_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC2_ch2 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = { - &ADC2_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC2_ch3 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = { - &ADC2_CH4_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC2_ch4 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = { - &ADC2_CH5_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC2_ch5 and average initcode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = { - &TEMPERATURE_SENSOR[0], // [] Temperature calibration data +const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[] = { + &USB_DEVICE_EXCHG_PINS[0], // [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled NULL }; diff --git a/components/efuse/esp32s31/esp_efuse_table.csv b/components/efuse/esp32s31/esp_efuse_table.csv index 592eb29f0c5..e762eeaa89d 100644 --- a/components/efuse/esp32s31/esp_efuse_table.csv +++ b/components/efuse/esp32s31/esp_efuse_table.csv @@ -9,17 +9,17 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: 73787d3f5ae45b80abca925a7562120b +# This file was generated by regtools.py based on the efuses.yaml file with the version: 2ec5c3c5bd07b0b4e073b91d75592d8f WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE +WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY -WR_DIS.XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of XTS_KEY_LENGTH_256 +WR_DIS.KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of KM_XTS_KEY_LENGTH_256 WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY -WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS @@ -28,14 +28,16 @@ WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of WDT_DELAY_SEL -WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD -WR_DIS.PXA0_TIEH_SEL_0, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_0 -WR_DIS.PXA0_TIEH_SEL_1, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_1 -WR_DIS.PXA0_TIEH_SEL_2, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_2 -WR_DIS.PXA0_TIEH_SEL_3, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_3 +WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 2, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE WR_DIS.DIS_WDT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_WDT WR_DIS.DIS_SWD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_SWD -WR_DIS.HP_PWR_SRC_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of HP_PWR_SRC_SEL +WR_DIS.PMU_FLASH_POWER_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of PMU_FLASH_POWER_SEL +WR_DIS.PMU_FLASH_POWER_SEL_EN, EFUSE_BLK0, 2, 1, [] wr_dis of PMU_FLASH_POWER_SEL_EN +WR_DIS.POWER_GLITCH_EN, EFUSE_BLK0, 2, 1, [] wr_dis of POWER_GLITCH_EN +WR_DIS.PVT_0_GLITCH_EN, EFUSE_BLK0, 3, 1, [] wr_dis of PVT_0_GLITCH_EN +WR_DIS.PVT_0_GLITCH_MODE, EFUSE_BLK0, 3, 1, [] wr_dis of PVT_0_GLITCH_MODE +WR_DIS.PVT_1_GLITCH_EN, EFUSE_BLK0, 3, 1, [] wr_dis of PVT_1_GLITCH_EN +WR_DIS.PVT_1_GLITCH_MODE, EFUSE_BLK0, 3, 1, [] wr_dis of PVT_1_GLITCH_MODE WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 @@ -45,15 +47,21 @@ WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.K WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 -WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.DIS_SM_CRYPT, EFUSE_BLK0, 14, 1, [] wr_dis of DIS_SM_CRYPT +WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME +WR_DIS.ECDSA_DISABLE_SOFT_K, EFUSE_BLK0, 14, 1, [] wr_dis of ECDSA_DISABLE_SOFT_K WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL -WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of CRYPT_DPA_ENABLE +WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE +WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL +WR_DIS.RMA_NONCE_ENA, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_NONCE_ENA +WR_DIS.RMA_CHIP_INFO_SOURCE, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_CHIP_INFO_SOURCE +WR_DIS.RMA_DISABLE_FAST_VEF, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_DISABLE_FAST_VEF +WR_DIS.ENA_XTS_SHADOW, EFUSE_BLK0, 14, 1, [] wr_dis of ENA_XTS_SHADOW +WR_DIS.ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_BLK0, 14, 1, [] wr_dis of ENA_SPI_BOOT_CRYPT_SCRAMBLER +WR_DIS.RE_ENABLE_JTAG_SOURCE, EFUSE_BLK0, 14, 1, [] wr_dis of RE_ENABLE_JTAG_SOURCE WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE -WR_DIS.ECDSA_ENABLE_SOFT_K, EFUSE_BLK0, 17, 1, [] wr_dis of ECDSA_ENABLE_SOFT_K WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE -WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE -WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE @@ -64,10 +72,10 @@ WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION -WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE -WR_DIS.KM_HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of KM_HUK_GEN_STATE +WR_DIS.HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of HUK_GEN_STATE WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR @@ -79,35 +87,7 @@ WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.LDO_VO1_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_DREF -WR_DIS.LDO_VO2_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_DREF -WR_DIS.LDO_VO1_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_MUL -WR_DIS.LDO_VO2_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_MUL -WR_DIS.LDO_VO3_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_K -WR_DIS.LDO_VO3_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_VOS -WR_DIS.LDO_VO3_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_C -WR_DIS.LDO_VO4_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_K -WR_DIS.LDO_VO4_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_VOS -WR_DIS.LDO_VO4_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_C -WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS -WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS -WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS -WR_DIS.DSLP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_DBG -WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS -WR_DIS.LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_DCDC_DBIAS_VOL_GAP WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0 -WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1 -WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2 -WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3 -WR_DIS.ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN0 -WR_DIS.ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN1 -WR_DIS.ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN2 -WR_DIS.ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN3 -WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0 -WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1 -WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2 -WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3 WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 @@ -115,164 +95,104 @@ WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.K WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 -WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 -WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 -WR_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN0 -WR_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN1 -WR_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN2 -WR_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN3 -WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF -WR_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF -WR_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF -WR_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF -WR_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF -WR_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF -WR_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF -WR_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF -WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 29, 1, [] wr_dis of TEMPERATURE_SENSOR -WR_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_OTG11_EXCHG_PINS -WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 30, 1, [] wr_dis of USB_PHY_SEL +WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 28, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 28, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG -RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-9 RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 -RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 -RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -RD_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN0 -RD_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN1 -RD_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN2 -RD_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN3 -RD_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF -RD_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF -RD_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF -RD_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF -RD_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF -RD_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF -RD_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF -RD_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF -RD_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF -RD_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF -RD_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF -RD_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF -RD_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF -RD_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF -RD_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 38, 1, [] rd_dis of TEMPERATURE_SENSOR -DIS_USB_JTAG, EFUSE_BLK0, 42, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, [] Represents whether USB-Serial_JTAG is disabled or enabled. -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download -DIS_TWAI, EFUSE_BLK0, 46, 1, [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled -JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled -SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled -DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled -KM_HUK_GEN_STATE, EFUSE_BLK0, 55, 5, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid -KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 64, 1, [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles -KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 66, 5, [] Represents whether the deploy mode of key manager is disabled or not -KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 71, 5, [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds -FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 76, 5, [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds -FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 81, 1, [] Set this bit to disable software written init key; and force use efuse_init_key -XTS_KEY_LENGTH_256, EFUSE_BLK0, 82, 1, [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key -WDT_DELAY_SEL, EFUSE_BLK0, 83, 1, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected -DIS_SM_CRYPT, EFUSE_BLK0, 84, 1, [] Set this bit to disable all the SM crypto functions, including SM2, SM3 +DIS_USB_JTAG, EFUSE_BLK0, 42, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled +DIS_TWAI, EFUSE_BLK0, 46, 1, [] Represents whether TWAI function is disabled or enabled. 1: disabled 0: enabled +JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled +SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled Even number: enabled +DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled +HUK_GEN_STATE, EFUSE_BLK0, 55, 5, [] Represents the control of validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid +KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 64, 1, [] Represents the control of key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles +KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 66, 5, [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & rma nonce; bit4: psram +KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 71, 5, [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & rma nonce 4: psram +FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 76, 5, [] Represents whether corresponding key must come from key manager. 1 is true; 0 is false. 0: ecsda 1: flash 2: reserved 3: reserved 4: psram +FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 81, 1, [] Represents whether to disable software written init key; and force use efuse_init_key +KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 82, 1, [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key +WDT_DELAY_SEL, EFUSE_BLK0, 83, 1, [] Represents the threshold level of the RTC watchdog STG0 timeout.0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16 +DIS_SM_CRYPT, EFUSE_BLK0, 84, 1, [] Represents whether to disable all the SM crypto functions; including SM2; SM3. 1: disabled 0: enabled SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 85, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 88, 1, [] Revoke 1st secure boot key SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 89, 1, [] Revoke 2nd secure boot key SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 90, 1, [] Revoke 3rd secure boot key KEY_PURPOSE_0, EFUSE_BLK0, 96, 5, [KEY0_PURPOSE] Represents the purpose of Key0 -KEY_PURPOSE_1, EFUSE_BLK0, 101, 5, [KEY1_PURPOSE] Represents the purpose of Key1 -KEY_PURPOSE_2, EFUSE_BLK0, 106, 5, [KEY2_PURPOSE] Represents the purpose of Key2 -KEY_PURPOSE_3, EFUSE_BLK0, 111, 5, [KEY3_PURPOSE] Represents the purpose of Key3 -KEY_PURPOSE_4, EFUSE_BLK0, 116, 5, [KEY4_PURPOSE] Represents the purpose of Key4 -ECC_FORCE_CONST_TIME, EFUSE_BLK0, 121, 1, [] Represents whether permanently turn on ECC const-time mode -ECDSA_ENABLE_SOFT_K, EFUSE_BLK0, 122, 1, [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used -SEC_DPA_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the spa secure level by configuring the clock random divide mode -XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 125, 1, [] Sets this bit to enable xts clock anti-dpa attack function -XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 128, 2, [] Sets this bit to control the xts pseudo-round anti-dpa sttack function -SECURE_BOOT_EN, EFUSE_BLK0, 130, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 131, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled -FLASH_TYPE, EFUSE_BLK0, 133, 1, [] The type of interfaced flash. 0: four data lines; 1: eight data lines -DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 137, 1, [] Set this bit to disable download via USB-OTG -FLASH_TPUW, EFUSE_BLK0, 140, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 144, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled -DIS_DIRECT_BOOT, EFUSE_BLK0, 145, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 146, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled -LOCK_KM_KEY, EFUSE_BLK0, 147, 1, [] Represents whether to lock the efuse xts key -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 148, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 149, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled -UART_PRINT_CONTROL, EFUSE_BLK0, 150, 2, [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing -FORCE_SEND_RESUME, EFUSE_BLK0, 152, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced -SECURE_VERSION, EFUSE_BLK0, 160, 16, [] Represents the version used by ESP-IDF anti-rollback feature -SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 176, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled -HYS_EN_PAD, EFUSE_BLK0, 177, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled -DCDC_VSET_EN, EFUSE_BLK0, 194, 1, [] Set the dcdc voltage default -DIS_WDT, EFUSE_BLK0, 195, 1, [] Set this bit to disable watch dog -DIS_SWD, EFUSE_BLK0, 196, 1, [] Set this bit to disable super-watchdog -SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 203, 1, [] Represents whether secure boot using SHA-384 is enabled -BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION, EFUSE_BLK0, 204, 4, [] Represents the anti-rollback secure version of th2 2nd stage bootloader -BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 208, 1, [] Represents whether the anti-rollback check for the 2nd stage bootloader is enabled -BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 209, 1, [] Represents whether the anti-rollback SECURE_VERSION will be updated from the rom bootloader -RECOVERY_BOOTLOADER_FLASH_SECTOR, EFUSE_BLK0, 210, 12, [] Represents the starting flash sector of the recovery bootloader -RMA_EN, EFUSE_BLK0, 222, 2, [] Represents whether rma function is supported in download mode -RMA_SESSION_COUNTER, EFUSE_BLK0, 224, 3, [] Represents the number of times the RMA session has been entered -RMA_NONCE_ENA, EFUSE_BLK0, 227, 2, [] Represents random number NONCE is used in RMA and whether the KM is used to generate the NONCE -RMA_CHIP_INFO_SOURCE, EFUSE_BLK0, 229, 1, [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA -RMA_DISABLE_FAST_VEF, EFUSE_BLK0, 230, 1, [] Represents whether disable FAST_VEF in RMA session - +KEY_PURPOSE_1, EFUSE_BLK0, 101, 5, [KEY1_PURPOSE] Represents the purpose of Key1 +KEY_PURPOSE_2, EFUSE_BLK0, 106, 5, [KEY2_PURPOSE] Represents the purpose of Key2 +KEY_PURPOSE_3, EFUSE_BLK0, 111, 5, [KEY3_PURPOSE] Represents the purpose of Key3 +KEY_PURPOSE_4, EFUSE_BLK0, 116, 5, [KEY4_PURPOSE] Represents the purpose of Key4 +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 121, 1, [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off +ECDSA_DISABLE_SOFT_K, EFUSE_BLK0, 122, 1, [] Represents whether permanently turn off ECDSA software set KEY. 1: turn off 0: turn on +SEC_DPA_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the spa secure level by configuring the clock random divide mode +XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 125, 1, [] Represents whether to enable xts clock anti-dpa attack function.0: Disabled. 1: Enabled +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 128, 2, [] Represents the control of the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation +SECURE_BOOT_EN, EFUSE_BLK0, 130, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 131, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled +FLASH_TYPE, EFUSE_BLK0, 133, 1, [] flash type: 0: nor flash; 1: nand flash +DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 137, 1, [] Set this bit to disable download via USB-OTG +FLASH_TPUW, EFUSE_BLK0, 140, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 144, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled 0: enabled +DIS_DIRECT_BOOT, EFUSE_BLK0, 145, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled 0: enabled +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 146, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled 0: enabled +LOCK_KM_KEY, EFUSE_BLK0, 147, 1, [] Represetns whether to lock the efuse xts key. 1. Lock 0: Unlock +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 148, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 149, 1, [] Represents whether security download is enabled or disabled. 1: enabled 0: disabled +UART_PRINT_CONTROL, EFUSE_BLK0, 150, 2, [] Represents the type of UART printing. 00: force enable printing 01: enable printing when GPIO8 is reset at low level 10: enable printing when GPIO8 is reset at high level 11: force disable printing +FORCE_SEND_RESUME, EFUSE_BLK0, 152, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced 0:not forced +SECURE_VERSION, EFUSE_BLK0, 160, 16, [] Represents the version used by ESP-IDF anti-rollback feature +SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 176, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled 0: enabled +HYS_EN_PAD, EFUSE_BLK0, 177, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled 0:disabled +DCDC_VSET_EN, EFUSE_BLK0, 194, 1, [] Select dcdc vset use efuse_dcdc_vset +DIS_WDT, EFUSE_BLK0, 195, 1, [] Set this bit to disable watch dog +DIS_SWD, EFUSE_BLK0, 196, 1, [] Set this bit to disable super-watchdog +SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 203, 1, [] Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable +BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION, EFUSE_BLK0, 204, 4, [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader +BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 208, 1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled +BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 209, 1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable +RECOVERY_BOOTLOADER_FLASH_SECTOR, EFUSE_BLK0, 210, 12, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +RMA_ENA, EFUSE_BLK0, 222, 2, [] Represents whether rma function is supported in download mode. 2'b01/2'b10: enabled2'b00/2'b11: disabled +RMA_SESSION_COUNTER, EFUSE_BLK0, 224, 3, [] Represents the number of times the RMA session has been entered +RMA_NONCE_ENA, EFUSE_BLK0, 227, 2, [] Represents whether random number NONCE is used in RMA and whether the KM module is used to generate the NONCE. 2'bx0: No NONCE 2'b1x: Use KM generate NONCE. +RMA_CHIP_INFO_SOURCE, EFUSE_BLK0, 229, 1, [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA.1: use HUK_info 0: use UNIQ_id +RMA_DISABLE_FAST_VEF, EFUSE_BLK0, 230, 1, [] Represents whether disable FAST_VEF in RMA session.1: disable0: enable +PVT_0_GLITCH_EN, EFUSE_BLK0, 231, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable +PVT_0_GLITCH_MODE, EFUSE_BLK0, 232, 2, [] Use to configure glitch mode +PVT_1_GLITCH_EN, EFUSE_BLK0, 234, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable +PVT_1_GLITCH_MODE, EFUSE_BLK0, 235, 2, [] Use to configure glitch mode +PMU_FLASH_POWER_SEL, EFUSE_BLK0, 237, 1, [] FLASH power select. 1'b1: use 3.3V1'b0: use 1.8V +PMU_FLASH_POWER_SEL_EN, EFUSE_BLK0, 238, 1, [] FLASH power select enable signal. 1'b1 : validates EFUSE_PMU_FLASH_POWER_SEL 1'b0: invalidates EFUSE_PMU_FLASH_POWER_SEL +POWER_GLITCH_EN, EFUSE_BLK0, 239, 4, [] set these bit enable power glitch enable +ENA_XTS_SHADOW, EFUSE_BLK0, 243, 1, [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled +ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_BLK0, 244, 1, [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled +RE_ENABLE_JTAG_SOURCE, EFUSE_BLK0, 245, 1, [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: RMA 1: HMAC MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address -WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version -WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Major chip version -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major -BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2 -BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2 -PSRAM_CAP, EFUSE_BLK1, 77, 3, [] PSRAM capacity -TEMP, EFUSE_BLK1, 80, 2, [] Operating temperature of the ESP chip -PSRAM_VENDOR, EFUSE_BLK1, 82, 2, [] PSRAM vendor -PKG_VERSION, EFUSE_BLK1, 84, 3, [] Package version -LDO_VO1_DREF, EFUSE_BLK1, 88, 4, [] Output VO1 parameter -LDO_VO2_DREF, EFUSE_BLK1, 92, 4, [] Output VO2 parameter -LDO_VO1_MUL, EFUSE_BLK1, 96, 3, [] Output VO1 parameter -LDO_VO2_MUL, EFUSE_BLK1, 99, 3, [] Output VO2 parameter -LDO_VO3_K, EFUSE_BLK1, 102, 8, [] Output VO3 calibration parameter -LDO_VO3_VOS, EFUSE_BLK1, 110, 6, [] Output VO3 calibration parameter -LDO_VO3_C, EFUSE_BLK1, 116, 6, [] Output VO3 calibration parameter -LDO_VO4_K, EFUSE_BLK1, 122, 8, [] Output VO4 calibration parameter -LDO_VO4_VOS, EFUSE_BLK1, 130, 6, [] Output VO4 calibration parameter -LDO_VO4_C, EFUSE_BLK1, 136, 6, [] Output VO4 calibration parameter -ACTIVE_HP_DBIAS, EFUSE_BLK1, 144, 4, [] Active HP DBIAS of fixed voltage -ACTIVE_LP_DBIAS, EFUSE_BLK1, 148, 4, [] Active LP DBIAS of fixed voltage -LSLP_HP_DBIAS, EFUSE_BLK1, 152, 4, [] LSLP HP DBIAS of fixed voltage -DSLP_DBG, EFUSE_BLK1, 156, 4, [] DSLP BDG of fixed voltage -DSLP_LP_DBIAS, EFUSE_BLK1, 160, 5, [] DSLP LP DBIAS of fixed voltage -LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK1, 165, 5, [] DBIAS gap between LP and DCDC +MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address +, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address +WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] Minor chip version +WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] Major chip version +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 120, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 1, [] Disables check of blk version major +BLK_VERSION_MINOR, EFUSE_BLK1, 122, 3, [] BLK_VERSION_MINOR of BLOCK2 +BLK_VERSION_MAJOR, EFUSE_BLK1, 125, 2, [] BLK_VERSION_MAJOR of BLOCK2 +PSRAM_CAP, EFUSE_BLK1, 127, 3, [] Psram capacity +TEMP, EFUSE_BLK1, 130, 2, [] Maximum ambient temperature that ESP Chip can work properly +PSRAM_VENDOR, EFUSE_BLK1, 132, 2, [] Psram vendor +PKG_VERSION, EFUSE_BLK1, 134, 2, [] Package version OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 128, 10, [] Average initcode of ADC1 atten0 -ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 138, 10, [] Average initcode of ADC1 atten1 -ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 148, 10, [] Average initcode of ADC1 atten2 -ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 158, 10, [] Average initcode of ADC1 atten3 -ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 168, 10, [] Average initcode of ADC2 atten0 -ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 178, 10, [] Average initcode of ADC2 atten1 -ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 188, 10, [] Average initcode of ADC2 atten2 -ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 198, 10, [] Average initcode of ADC2 atten3 -ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 208, 10, [] HI_DOUT of ADC1 atten0 -ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 218, 10, [] HI_DOUT of ADC1 atten1 -ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 228, 10, [] HI_DOUT of ADC1 atten2 -ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 238, 10, [] HI_DOUT of ADC1 atten3 USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data @@ -280,22 +200,5 @@ KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KE KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data -ADC2_HI_DOUT_ATTEN0, EFUSE_BLK9, 0, 10, [] HI_DOUT of ADC2 atten0 -ADC2_HI_DOUT_ATTEN1, EFUSE_BLK9, 10, 10, [] HI_DOUT of ADC2 atten1 -ADC2_HI_DOUT_ATTEN2, EFUSE_BLK9, 20, 10, [] HI_DOUT of ADC2 atten2 -ADC2_HI_DOUT_ATTEN3, EFUSE_BLK9, 30, 10, [] HI_DOUT of ADC2 atten3 -ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 40, 4, [] Gap between ADC1_ch0 and average initcode -ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 44, 4, [] Gap between ADC1_ch1 and average initcode -ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 48, 4, [] Gap between ADC1_ch2 and average initcode -ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 52, 4, [] Gap between ADC1_ch3 and average initcode -ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 56, 4, [] Gap between ADC1_ch4 and average initcode -ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 60, 4, [] Gap between ADC1_ch5 and average initcode -ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 64, 4, [] Gap between ADC1_ch6 and average initcode -ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 68, 4, [] Gap between ADC1_ch7 and average initcode -ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 72, 4, [] Gap between ADC2_ch0 and average initcode -ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 76, 4, [] Gap between ADC2_ch1 and average initcode -ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 80, 4, [] Gap between ADC2_ch2 and average initcode -ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 84, 4, [] Gap between ADC2_ch3 and average initcode -ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 88, 4, [] Gap between ADC2_ch4 and average initcode -ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK9, 92, 4, [] Gap between ADC2_ch5 and average initcode -TEMPERATURE_SENSOR, EFUSE_BLK9, 96, 9, [] Temperature calibration data +SYS_DATA_PART2, EFUSE_BLK9, 0, 32, [BLOCK_SYS_DATA2] System data part 2 (reserved) +USB_DEVICE_EXCHG_PINS, EFUSE_BLK9, 192, 1, [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled diff --git a/components/efuse/esp32s31/esp_efuse_utility.c b/components/efuse/esp32s31/esp_efuse_utility.c index bc89d26524d..01990cbef8c 100644 --- a/components/efuse/esp32s31/esp_efuse_utility.c +++ b/components/efuse/esp32s31/esp_efuse_utility.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,9 +19,8 @@ extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; #endif // CONFIG_EFUSE_VIRTUAL /*Range addresses to read blocks*/ -// TODO: [ESP32S31] IDF-14688 the table is written for passing static check, not accurate, please check. const esp_efuse_range_addr_t range_read_addr_blocks[] = { - {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT + {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA7_REG}, // range address of EFUSE_BLK0 REPEAT {EFUSE_RD_MAC_SYS0_REG, EFUSE_RD_MAC_SYS5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA @@ -30,14 +29,14 @@ const esp_efuse_range_addr_t range_read_addr_blocks[] = { {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 - {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 + {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG}, // range address of EFUSE_BLK9 SYS_DATA_PART2 }; static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; /*Range addresses to write blocks (it is not real regs, it is buffer) */ const esp_efuse_range_addr_t range_write_addr_blocks[] = { - {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][8]}, {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]}, {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]}, {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]}, diff --git a/components/efuse/esp32s31/include/esp_efuse_chip.h b/components/efuse/esp32s31/include/esp_efuse_chip.h index 9894688417e..d37404dfc8a 100644 --- a/components/efuse/esp32s31/include/esp_efuse_chip.h +++ b/components/efuse/esp32s31/include/esp_efuse_chip.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -59,20 +59,28 @@ typedef enum { * @brief Type of key purpose */ typedef enum { - ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ - ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/ - ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, /**< XTS_AES_256_KEY_1 (flash/PSRAM encryption) */ - ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, /**< XTS_AES_256_KEY_2 (flash/PSRAM encryption) */ - ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY */ - ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */ + ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (P256) (Expected in little endian order)*/ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, /**< XTS_AES_256 flash key 1 */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, /**< XTS_AES_256 flash key 2 */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128 flash key */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13, /**< XTS_AES_256 PSRAM key 1 */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14, /**< XTS_AES_256 PSRAM key 2 */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15, /**< XTS_AES_128 PSRAM key */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 = 16, /**< ECDSA private key P-192 */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L = 17, /**< ECDSA private key P-384 low part */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H = 18, /**< ECDSA private key P-384 high part */ + ESP_EFUSE_KEY_PURPOSE_SDC_KEY_DIGEST = 19, /**< SDC key digest */ + ESP_EFUSE_KEY_PURPOSE_MAX = 32, /**< MAX PURPOSE */ } esp_efuse_purpose_t; #ifdef __cplusplus diff --git a/components/efuse/esp32s31/include/esp_efuse_table.h b/components/efuse/esp32s31/include/esp_efuse_table.h index 93ccca818b2..ca5e96f2082 100644 --- a/components/efuse/esp32s31/include/esp_efuse_table.h +++ b/components/efuse/esp32s31/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 384d67c0f503bd731d01230c83b3d360 +// md5_digest_table 1cdb8731d5e8193ceb48139f9db95994 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -20,12 +20,12 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; @@ -34,14 +34,16 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PMU_FLASH_POWER_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PMU_FLASH_POWER_SEL_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWER_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_0_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_0_GLITCH_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_1_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_1_GLITCH_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; @@ -56,16 +58,21 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; #define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; #define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; -#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SM_CRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_SOFT_K[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_NONCE_ENA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_CHIP_INFO_SOURCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_DISABLE_FAST_VEF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENA_XTS_SHADOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENA_SPI_BOOT_CRYPT_SCRAMBLER[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RE_ENABLE_JTAG_SOURCE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; @@ -76,11 +83,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; #define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; @@ -92,35 +99,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; @@ -136,31 +115,9 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; #define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; #define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; -#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; #define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; @@ -173,31 +130,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; #define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; #define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; -#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; -#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; @@ -205,13 +138,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[]; extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[]; extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SM_CRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; @@ -229,7 +162,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; #define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_SOFT_K[]; extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; @@ -257,11 +190,21 @@ extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[]; extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RMA_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RMA_ENA[]; extern const esp_efuse_desc_t* ESP_EFUSE_RMA_SESSION_COUNTER[]; extern const esp_efuse_desc_t* ESP_EFUSE_RMA_NONCE_ENA[]; extern const esp_efuse_desc_t* ESP_EFUSE_RMA_CHIP_INFO_SOURCE[]; extern const esp_efuse_desc_t* ESP_EFUSE_RMA_DISABLE_FAST_VEF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_1_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_1_GLITCH_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PMU_FLASH_POWER_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PMU_FLASH_POWER_SEL_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENA_XTS_SHADOW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RE_ENABLE_JTAG_SOURCE[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; @@ -275,35 +218,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; @@ -319,25 +234,9 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; #define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; #define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[]; #ifdef __cplusplus } diff --git a/components/efuse/esp32s31/private_include/esp_efuse_utility.h b/components/efuse/esp32s31/private_include/esp_efuse_utility.h index 8dbf5c9a6c1..ac0ed54cfd5 100644 --- a/components/efuse/esp32s31/private_include/esp_efuse_utility.h +++ b/components/efuse/esp32s31/private_include/esp_efuse_utility.h @@ -10,7 +10,7 @@ extern "C" { #endif -#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ +#define COUNT_EFUSE_REG_PER_BLOCK 9 /* The maximum number of readable registers per block. */ #define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h index 3e32ec92a50..94cd0ba215d 100644 --- a/components/efuse/include/esp_efuse.h +++ b/components/efuse/include/esp_efuse.h @@ -10,6 +10,7 @@ #include #include "esp_err.h" +#include "esp_assert.h" #include "esp_log.h" #include "soc/soc_caps.h" #include "sdkconfig.h" @@ -32,11 +33,13 @@ extern "C" { * @brief Type definition for an eFuse field */ typedef struct { - esp_efuse_block_t efuse_block: 8; /**< Block of eFuse */ - uint8_t bit_start; /**< Start bit [0..255] */ + esp_efuse_block_t efuse_block: 7; /**< Block of eFuse */ + uint16_t bit_start: 9; /**< Start bit [0..511] */ uint16_t bit_count; /**< Length of bit field [1..-]*/ } esp_efuse_desc_t; +ESP_STATIC_ASSERT(sizeof(esp_efuse_desc_t) == sizeof(uint32_t), "esp_efuse_desc_t should be 32 bits"); + /** * @brief Type definition for ROM log scheme */ diff --git a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c index ccff466c596..1385d22276c 100644 --- a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c +++ b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,7 +43,7 @@ const esp_efuse_keys_t s_table[EFUSE_BLK_KEY_MAX - EFUSE_BLK_KEY0] = { {ESP_EFUSE_KEY2, ESP_EFUSE_KEY_PURPOSE_2, ESP_EFUSE_RD_DIS_KEY2, ESP_EFUSE_WR_DIS_KEY2, ESP_EFUSE_WR_DIS_KEY2_PURPOSE}, {ESP_EFUSE_KEY3, ESP_EFUSE_KEY_PURPOSE_3, ESP_EFUSE_RD_DIS_KEY3, ESP_EFUSE_WR_DIS_KEY3, ESP_EFUSE_WR_DIS_KEY3_PURPOSE}, {ESP_EFUSE_KEY4, ESP_EFUSE_KEY_PURPOSE_4, ESP_EFUSE_RD_DIS_KEY4, ESP_EFUSE_WR_DIS_KEY4, ESP_EFUSE_WR_DIS_KEY4_PURPOSE}, -#if !CONFIG_IDF_TARGET_ESP32S31 // TODO: [ESP32S31] IDF-14688 +#if !CONFIG_IDF_TARGET_ESP32S31 {ESP_EFUSE_KEY5, ESP_EFUSE_KEY_PURPOSE_5, ESP_EFUSE_RD_DIS_KEY5, ESP_EFUSE_WR_DIS_KEY5, ESP_EFUSE_WR_DIS_KEY5_PURPOSE}, #endif #if 0 @@ -78,7 +78,6 @@ bool esp_efuse_block_is_empty(esp_efuse_block_t block) return false; } -#if !CONFIG_IDF_TARGET_ESP32S31 // TODO: [ESP32S31] IDF-14688 // Sets a write protection for the whole block. esp_err_t esp_efuse_set_write_protect(esp_efuse_block_t blk) { @@ -88,7 +87,7 @@ esp_err_t esp_efuse_set_write_protect(esp_efuse_block_t blk) return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART1, 1); } else if (blk == EFUSE_BLK3) { return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_USER_DATA, 1); - } else if (blk == EFUSE_BLK10) { + } else if (blk == EFUSE_BLK_SYS_DATA_PART2) { return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART2, 1); } else if (blk >= EFUSE_BLK_KEY0 && blk < EFUSE_BLK_KEY_MAX) { unsigned idx = blk - EFUSE_BLK_KEY0; @@ -104,14 +103,15 @@ esp_err_t esp_efuse_set_read_protect(esp_efuse_block_t blk) unsigned idx = blk - EFUSE_BLK_KEY0; return esp_efuse_write_field_cnt(s_table[idx].key_rd_dis, 1); } - else if (blk == EFUSE_BLK10) { +#ifdef ESP_EFUSE_RD_DIS_SYS_DATA_PART2 + else if (blk == EFUSE_BLK_SYS_DATA_PART2) { return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_SYS_DATA_PART2, 1); } +#endif return ESP_ERR_NOT_SUPPORTED; } -#endif // get efuse coding_scheme. esp_efuse_coding_scheme_t esp_efuse_get_coding_scheme(esp_efuse_block_t blk) { diff --git a/components/efuse/src/esp_efuse_utility.c b/components/efuse/src/esp_efuse_utility.c index 7c522f4d631..d2f5cf17bc1 100644 --- a/components/efuse/src/esp_efuse_utility.c +++ b/components/efuse/src/esp_efuse_utility.c @@ -361,7 +361,8 @@ static uint32_t set_cnt_in_reg(int bit_start_in_reg, int bit_count_used_in_reg, static bool check_range_of_bits(esp_efuse_block_t blk, int offset_in_bits, int size_bits) { int max_num_bit = offset_in_bits + size_bits; - if (max_num_bit > 256) { + int max_num_bit_in_block = (blk == EFUSE_BLK0) ? COUNT_EFUSE_REG_PER_BLOCK * 32 : 256; + if (max_num_bit > max_num_bit_in_block) { return false; } else { ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(blk, max_num_bit); diff --git a/components/efuse/test_apps/.build-test-rules.yml b/components/efuse/test_apps/.build-test-rules.yml index 93c0537897d..fed8ec40856 100644 --- a/components/efuse/test_apps/.build-test-rules.yml +++ b/components/efuse/test_apps/.build-test-rules.yml @@ -3,13 +3,11 @@ components/efuse/test_apps: enable: - if: (INCLUDE_DEFAULT == 1 and SOC_EFUSE_SUPPORTED == 1) or IDF_TARGET == "linux") - disable: - - if: IDF_TARGET in ["esp32s31"] - temporary: true - reason: not support yet # TODO: [ESP32S31] IDF-14688 disable_test: - if: IDF_TARGET in ["esp32s2", "esp32s3"] reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3. + - if: IDF_TARGET == "esp32s31" + reason: no available module on CI depends_components: - *common_components - efuse diff --git a/components/efuse/test_apps/README.md b/components/efuse/test_apps/README.md index 8b53053b435..9ae4df32277 100644 --- a/components/efuse/test_apps/README.md +++ b/components/efuse/test_apps/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | ----- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | Linux | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | ----- | diff --git a/components/efuse/test_apps/main/with_key_purposes/test_efuse.c b/components/efuse/test_apps/main/with_key_purposes/test_efuse.c index 7a3c0703fa0..e372bee43c2 100644 --- a/components/efuse/test_apps/main/with_key_purposes/test_efuse.c +++ b/components/efuse/test_apps/main/with_key_purposes/test_efuse.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -149,16 +149,16 @@ TEST_CASE("Test reading inside of batch mode in a nested way", "[efuse]") esp_efuse_utility_erase_virt_blocks(); esp_efuse_utility_debug_dump_blocks(); - TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY5, &key, 256)); + TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY4, &key, 256)); TEST_ASSERT_EACH_EQUAL_HEX8(0, key, sizeof(key)); TEST_ESP_OK(esp_efuse_batch_write_begin()); TEST_ESP_OK(esp_efuse_batch_write_begin()); TEST_ESP_OK(esp_efuse_batch_write_begin()); - TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_KEY5, &new_key, 256)); - TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK_KEY5)); + TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_KEY4, &new_key, 256)); + TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK_KEY4)); ESP_LOGI(TAG, "Reading inside Batch mode, the key was not burn yet and it is empty"); - TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY5, &key, 256)); + TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY4, &key, 256)); TEST_ASSERT_EACH_EQUAL_HEX8(0, key, sizeof(key)); TEST_ESP_OK(esp_efuse_batch_write_commit()); TEST_ESP_OK(esp_efuse_batch_write_commit()); @@ -169,7 +169,7 @@ TEST_CASE("Test reading inside of batch mode in a nested way", "[efuse]") TEST_ESP_OK(esp_efuse_batch_write_begin()); TEST_ESP_OK(esp_efuse_batch_write_begin()); ESP_LOGI(TAG, "Reading inside Batch mode, the key is already set"); - TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY5, &key, 256)); + TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY4, &key, 256)); TEST_ASSERT_EQUAL_HEX8_ARRAY(new_key, key, sizeof(key)); TEST_ESP_OK(esp_efuse_batch_write_commit()); TEST_ESP_OK(esp_efuse_batch_write_commit()); diff --git a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c index 2724bf94339..f3e83bb5da3 100644 --- a/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c +++ b/components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c @@ -161,7 +161,7 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]") int tmp_purpose = 0; TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_efuse_write_key(EFUSE_BLK3, tmp_purpose, &rd_key, sizeof(rd_key))); TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_efuse_write_key(EFUSE_BLK_KEY0, tmp_purpose, &rd_key, 33)); - TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_efuse_write_key(EFUSE_BLK10, tmp_purpose, &rd_key, sizeof(rd_key))); + TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_efuse_write_key(EFUSE_BLK_SYS_DATA_PART2, tmp_purpose, &rd_key, sizeof(rd_key))); for (esp_efuse_purpose_t g_purpose = ESP_EFUSE_KEY_PURPOSE_USER; g_purpose < ESP_EFUSE_KEY_PURPOSE_MAX; ++g_purpose) { if (g_purpose == ESP_EFUSE_KEY_PURPOSE_USER) { diff --git a/components/hal/esp32s31/efuse_hal.c b/components/hal/esp32s31/efuse_hal.c index 87587970ee9..5d33663423b 100644 --- a/components/hal/esp32s31/efuse_hal.c +++ b/components/hal/esp32s31/efuse_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +10,6 @@ #include "hal/efuse_hal.h" #include "hal/efuse_ll.h" -// TODO: [ESP32S31] IDF-14688 - #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block)))) #define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block)))) @@ -73,12 +71,12 @@ void efuse_hal_rs_calculate(const void *data, void *rs_values) bool efuse_hal_is_coding_error_in_block(unsigned block) { if (block == 0) { - for (unsigned i = 0; i < 5; i++) { - if (REG_READ(EFUSE_RD_REPEAT_DATA_ERR0_REG + i * 4)) { + for (unsigned i = 0; i < 8; i++) { + if (REG_READ(EFUSE_RD_REPEAT_DATA_ERR0_REG + i * 4)) { // DATA_ERR0_REG ... DATA_ERR7_REG return true; } } - } else if (block <= 10) { + } else if (block <= 9) { block--; uint32_t error_reg = REG_READ(EFUSE_RD_RS_DATA_ERR0_REG + (block / 8) * 4); return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0; diff --git a/components/hal/esp32s31/include/hal/efuse_ll.h b/components/hal/esp32s31/include/hal/efuse_ll.h index 74ce7cfaf52..4f3b0f7bf1f 100644 --- a/components/hal/esp32s31/include/hal/efuse_ll.h +++ b/components/hal/esp32s31/include/hal/efuse_ll.h @@ -8,10 +8,12 @@ #include #include +#include "hal/misc.h" +#include "soc/efuse_defs.h" +#include "soc/efuse_reg.h" #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" -#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { @@ -28,25 +30,20 @@ typedef enum { // Always inline these functions even no gcc optimization is applied. -// TODO: [ESP32S31] IDF-14688 This file is inherited from verification branch, need to check all functions. - /******************* eFuse fields *************************/ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) { - // TODO: [ESP32S31] IDF-14688 return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) { - // TODO: [ESP32S31] IDF-14688 return EFUSE.rd_repeat_data1.wdt_delay_sel; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - // TODO: [ESP32S31] IDF-14688 return EFUSE.rd_mac_sys0.mac_0; } @@ -63,54 +60,40 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - return 0; - // TODO: [ESP32S31] IDF-14688 + return EFUSE.rd_mac_sys3.wafer_version_major; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return 0; - // TODO: [ESP32S31] IDF-14688 + return EFUSE.rd_mac_sys3.wafer_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) { - return 0; - // TODO: [ESP32S31] IDF-14688 + return EFUSE.rd_mac_sys3.disable_wafer_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - return 0; - // TODO: [ESP32S31] IDF-14688 + return EFUSE.rd_mac_sys3.blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - return 0; - // TODO: [ESP32S31] IDF-14688 + return EFUSE.rd_mac_sys3.blk_version_minor; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) { - return 0; - // TODO: [ESP32S31] IDF-14688 + return EFUSE.rd_mac_sys3.disable_blk_version_major; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - return 0; - // TODO: [ESP32S31] IDF-14688 + return EFUSE.rd_mac_sys4.pkg_version; } -// TODO: [ESP32S31] IDF-14688 -// __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) -// { -// (void) curve; -// -// } - /******************* eFuse control functions *************************/ __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) @@ -125,37 +108,37 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) { - // TODO: [ESP32S31] IDF-14688 + EFUSE.cmd.read_cmd = 1; } __attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) { - // TODO: [ESP32S31] IDF-14688 + HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD); } __attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) { - // TODO: [ESP32S31] IDF-14688 + HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE); } __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) { - // TODO: [ESP32S31] IDF-14688 + HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE); } __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) { - // TODO: [ESP32S31] IDF-14688 + HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value); } __attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void) { - // TODO: [ESP32S31] IDF-14688 + EFUSE.wr_tim_conf0_rs_bypass.update = 1; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_controller_state(void) { - // TODO: [ESP32S31] IDF-14688 return EFUSE.status.state; } diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 14800b09034..02c653a97fa 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -831,6 +831,14 @@ config SOC_EFUSE_ECDSA_KEY bool default y +config SOC_EFUSE_ECDSA_KEY_P192 + bool + default y + +config SOC_EFUSE_ECDSA_KEY_P384 + bool + default y + config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index 7b45d31de55..61f6969a386 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -53,8 +53,8 @@ // #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: [ESP32S31] IDF-14629 #define SOC_ULP_SUPPORTED 1 #define SOC_LP_CORE_SUPPORTED 1 -#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32S31] IDF-14688 -#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32S31] IDF-14688 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_EFUSE_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14645 #define SOC_RMT_SUPPORTED 1 @@ -343,17 +343,19 @@ #define SOC_ECC_SUPPORT_CURVE_P384 (1) /*-------------------------- eFuse CAPS----------------------------*/ -// TODO: [ESP32S31] IDF-14688 #define SOC_EFUSE_DIS_PAD_JTAG 1 #define SOC_EFUSE_DIS_USB_JTAG 1 #define SOC_EFUSE_DIS_DIRECT_BOOT 1 #define SOC_EFUSE_SOFT_DIS_JTAG 1 /* Capability to disable the MSPI access in download mode */ #define SOC_EFUSE_DIS_DOWNLOAD_MSPI 1 +// ECDSA_P256_KEY #define SOC_EFUSE_ECDSA_KEY 1 +#define SOC_EFUSE_ECDSA_KEY_P192 1 +#define SOC_EFUSE_ECDSA_KEY_P384 1 /*-------------------------- Key Manager CAPS----------------------------*/ -// TODO: [ESP32S31] IDF-14688 +// TODO: [ESP32S31] IDF-14626 #define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */ // #define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */ /*-------------------------- Secure Boot CAPS----------------------------*/ diff --git a/components/soc/esp32s31/register/soc/efuse_reg.h b/components/soc/esp32s31/register/soc/efuse_reg.h index 9d7e4811a6c..2c8e727f22b 100644 --- a/components/soc/esp32s31/register/soc/efuse_reg.h +++ b/components/soc/esp32s31/register/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -149,9 +149,8 @@ extern "C" { /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled. For * mapping between the bits of this field and the eFuse memory bits, please refer to - * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. - * 1: Disabled - * 0: Enabled + * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.\\1: + * Disabled\\0: Enabled\\ */ #define EFUSE_WR_DIS 0xFFFFFFFFU #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) @@ -164,46 +163,54 @@ extern "C" { #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block9) is disabled or - * enabled. - * 1: disabled - * 0: enabled + * enabled.\\ 1: disabled\\ 0: enabled\\ */ #define EFUSE_RD_DIS 0x0000007FU #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 +/** EFUSE_RD_RESERVE_0_39 : RW; bitpos: [9:7]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_39 0x00000007U +#define EFUSE_RD_RESERVE_0_39_M (EFUSE_RD_RESERVE_0_39_V << EFUSE_RD_RESERVE_0_39_S) +#define EFUSE_RD_RESERVE_0_39_V 0x00000007U +#define EFUSE_RD_RESERVE_0_39_S 7 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [10]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: + * disabled\\ 0: enabled\\ */ #define EFUSE_DIS_USB_JTAG (BIT(10)) #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; * Represents whether the function that forces chip into download mode is disabled or - * enabled. - * 1: disabled - * 0: enabled + * enabled.\\ 1: disabled\\ 0: enabled\\ */ #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot_mode_download is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled.\\ 1: disabled\\ 0: enabled\\ */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ */ #define EFUSE_DIS_TWAI (BIT(14)) #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) @@ -212,27 +219,23 @@ extern "C" { /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; * Represents whether the selection between usb_to_jtag and pad_to_jtag through * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled. - * 1: enabled - * 0: disabled + * is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ */ #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) #define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_S 15 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. - * Odd number: disabled - * Even number: enabled + * Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even + * number: enabled\\ */ #define EFUSE_SOFT_DIS_JTAG 0x00000007U #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). - * 1: disabled - * 0: enabled + * Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ + * 0: enabled\\ */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) @@ -240,14 +243,27 @@ extern "C" { #define EFUSE_DIS_PAD_JTAG_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode). - * 1: disabled - * 0: enabled + * mode).\\ 1: disabled\\ 0: enabled\\ */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_RD_RESERVE_0_53 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_53 (BIT(21)) +#define EFUSE_RD_RESERVE_0_53_M (EFUSE_RD_RESERVE_0_53_V << EFUSE_RD_RESERVE_0_53_S) +#define EFUSE_RD_RESERVE_0_53_V 0x00000001U +#define EFUSE_RD_RESERVE_0_53_S 21 +/** EFUSE_DIS_WIFI6 : RO; bitpos: [22]; default: 0; + * Represents whether the WIFI6 feature is enabled or disabled. 1: WIFI6 is disabled, 0: + * WIFI6 is enabled. + */ +#define EFUSE_DIS_WIFI6 (BIT(22)) +#define EFUSE_DIS_WIFI6_M (EFUSE_DIS_WIFI6_V << EFUSE_DIS_WIFI6_S) +#define EFUSE_DIS_WIFI6_V 0x00000001U +#define EFUSE_DIS_WIFI6_S 22 /** EFUSE_HUK_GEN_STATE : RO; bitpos: [27:23]; default: 0; * Represents the control of validation of HUK generate mode. Odd of 1 is invalid, * even of 1 is valid. @@ -256,6 +272,13 @@ extern "C" { #define EFUSE_HUK_GEN_STATE_M (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S) #define EFUSE_HUK_GEN_STATE_V 0x0000001FU #define EFUSE_HUK_GEN_STATE_S 23 +/** EFUSE_RD_RESERVE_0_60 : RW; bitpos: [31:28]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_60 0x0000000FU +#define EFUSE_RD_RESERVE_0_60_M (EFUSE_RD_RESERVE_0_60_V << EFUSE_RD_RESERVE_0_60_S) +#define EFUSE_RD_RESERVE_0_60_V 0x0000000FU +#define EFUSE_RD_RESERVE_0_60_S 28 /** EFUSE_RD_REPEAT_DATA1_REG register * Represents rd_repeat_data @@ -269,12 +292,17 @@ extern "C" { #define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) #define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000001U #define EFUSE_KM_RND_SWITCH_CYCLE_S 0 +/** EFUSE_RD_RESERVE_0_65 : RW; bitpos: [1]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_65 (BIT(1)) +#define EFUSE_RD_RESERVE_0_65_M (EFUSE_RD_RESERVE_0_65_V << EFUSE_RD_RESERVE_0_65_S) +#define EFUSE_RD_RESERVE_0_65_V 0x00000001U +#define EFUSE_RD_RESERVE_0_65_S 1 /** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [6:2]; default: 0; - * Represents whether the deploy mode of key manager is disable or not. - * 1: disabled - * 0: enabled. - * bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, bit3: ds & rma - * nonce, bit4: psram + * Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled + * \\ 0: enabled.\\ bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, + * bit3: ds & rma nonce, bit4: psram */ #define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000001FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) @@ -282,12 +310,8 @@ extern "C" { #define EFUSE_KM_DISABLE_DEPLOY_MODE_S 2 /** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [11:7]; default: 0; * Represents whether corresponding key can only be deployed once. 1 is true, 0 is - * false. - * 0: ecsda - * 1: flash & spi boot srambler - * 2: hmac & aes - * 3: ds & rma nonce - * 4: psram + * false. \\ 0: ecsda\\ 1: flash & spi boot srambler\\ 2: hmac & aes\\ 3: ds & rma + * nonce\\ 4: psram\\ */ #define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000001FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) @@ -295,12 +319,7 @@ extern "C" { #define EFUSE_KM_DEPLOY_ONLY_ONCE_S 7 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [16:12]; default: 0; * Represents whether corresponding key must come from key manager. 1 is true, 0 is - * false. - * 0: ecsda - * 1: flash - * 2: reserved - * 3: reserved - * 4: psram + * false.\\ 0: ecsda\\ 1: flash\\ 2: reserved\\ 3: reserved\\ 4: psram\\ */ #define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000001FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) @@ -316,70 +335,69 @@ extern "C" { #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 17 /** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [18]; default: 0; * Represents whether to configure flash encryption use xts-128 key. else use xts-256 - * key. - * 0: 128-bit key - * 1: 256-bit key + * key. \\ 0: 128-bit key \\ 1: 256-bit key\\ */ #define EFUSE_KM_XTS_KEY_LENGTH_256 (BIT(18)) #define EFUSE_KM_XTS_KEY_LENGTH_256_M (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S) #define EFUSE_KM_XTS_KEY_LENGTH_256_V 0x00000001U #define EFUSE_KM_XTS_KEY_LENGTH_256_S 18 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [19]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout. - * 0: Original threshold configuration value of STG0 *2 - * 1: Original threshold configuration value of STG0 *4 - * 2: Original threshold configuration value of STG0 *8 - * 3: Original threshold configuration value of STG0 *16 + * Represents the threshold level of the RTC watchdog STG0 timeout.\\0: Original + * threshold configuration value of STG0 *2 \\1: Original threshold configuration + * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: + * Original threshold configuration value of STG0 *16 \\ */ #define EFUSE_WDT_DELAY_SEL (BIT(19)) #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) #define EFUSE_WDT_DELAY_SEL_V 0x00000001U #define EFUSE_WDT_DELAY_SEL_S 19 /** EFUSE_DIS_SM_CRYPT : RO; bitpos: [20]; default: 0; - * Represents whether to disable all the SM crypto functions, including SM2, SM3. - * 1: disabled - * 0: enabled + * Represents whether to disable all the SM crypto functions, including SM2, SM3.\\ 1: + * disabled\\ 0: enabled\\ */ #define EFUSE_DIS_SM_CRYPT (BIT(20)) #define EFUSE_DIS_SM_CRYPT_M (EFUSE_DIS_SM_CRYPT_V << EFUSE_DIS_SM_CRYPT_S) #define EFUSE_DIS_SM_CRYPT_V 0x00000001U #define EFUSE_DIS_SM_CRYPT_S 20 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [23:21]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled. - * Odd number of 1: enabled - * Even number of 1: disabled + * Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of + * 1: enabled\\ Even number of 1: disabled\\ */ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [24]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(24)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 24 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [25]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(25)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 25 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [26]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(26)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 26 +/** EFUSE_RD_RESERVE_0_91 : RW; bitpos: [31:27]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_91 0x0000001FU +#define EFUSE_RD_RESERVE_0_91_M (EFUSE_RD_RESERVE_0_91_V << EFUSE_RD_RESERVE_0_91_S) +#define EFUSE_RD_RESERVE_0_91_V 0x0000001FU +#define EFUSE_RD_RESERVE_0_91_S 27 /** EFUSE_RD_REPEAT_DATA2_REG register * Represents rd_repeat_data @@ -421,18 +439,16 @@ extern "C" { #define EFUSE_KEY_PURPOSE_4_V 0x0000001FU #define EFUSE_KEY_PURPOSE_4_S 20 /** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [25]; default: 0; - * Represents whether permanently turn on ECC const-time mode. - * 1: turn on - * 0: turn off + * Represents whether permanently turn on ECC const-time mode. \\ 1: turn on\\ 0: turn + * off\\ */ #define EFUSE_ECC_FORCE_CONST_TIME (BIT(25)) #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) #define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U #define EFUSE_ECC_FORCE_CONST_TIME_S 25 /** EFUSE_ECDSA_DISABLE_SOFT_K : RO; bitpos: [26]; default: 0; - * Represents whether permanently turn off ECDSA software set KEY. - * 1: turn off - * 0: turn on + * Represents whether permanently turn off ECDSA software set KEY.\\ 1: turn off\\ 0: + * turn on\\ */ #define EFUSE_ECDSA_DISABLE_SOFT_K (BIT(26)) #define EFUSE_ECDSA_DISABLE_SOFT_K_M (EFUSE_ECDSA_DISABLE_SOFT_K_V << EFUSE_ECDSA_DISABLE_SOFT_K_S) @@ -446,47 +462,56 @@ extern "C" { #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 27 /** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0; - * Represents whether to enable xts clock anti-dpa attack function. - * 0: Disabled. - * 1: Enabled + * Represents whether to enable xts clock anti-dpa attack function.\\0: Disabled. \\1: + * Enabled\\ */ #define EFUSE_XTS_DPA_CLK_ENABLE (BIT(29)) #define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) #define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U #define EFUSE_XTS_DPA_CLK_ENABLE_S 29 +/** EFUSE_RD_RESERVE_0_126 : RW; bitpos: [31:30]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_126 0x00000003U +#define EFUSE_RD_RESERVE_0_126_M (EFUSE_RD_RESERVE_0_126_V << EFUSE_RD_RESERVE_0_126_S) +#define EFUSE_RD_RESERVE_0_126_V 0x00000003U +#define EFUSE_RD_RESERVE_0_126_S 30 /** EFUSE_RD_REPEAT_DATA3_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [1:0]; default: 0; - * Represents the control of the xts pseudo-round anti-dpa attack function. - * 0: controlled by register. - * 1-3: the higher the value is, the more pseudo-rounds are inserted to the xts-aes - * calculation + * Represents the control of the xts pseudo-round anti-dpa attack function.\\ 0: + * controlled by register.\\ 1-3: the higher the value is, the more pseudo-rounds are + * inserted to the xts-aes calculation\\ */ #define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) #define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 0 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [2]; default: 0; - * Represents whether secure boot is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ */ #define EFUSE_SECURE_BOOT_EN (BIT(2)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 2 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [3]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled. - * 1: enabled. - * 0: disabled + * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: + * enabled.\\ 0: disabled\\ */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(3)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 3 +/** EFUSE_RD_RESERVE_0_132 : RW; bitpos: [4]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_132 (BIT(4)) +#define EFUSE_RD_RESERVE_0_132_M (EFUSE_RD_RESERVE_0_132_V << EFUSE_RD_RESERVE_0_132_S) +#define EFUSE_RD_RESERVE_0_132_V 0x00000001U +#define EFUSE_RD_RESERVE_0_132_S 4 /** EFUSE_FLASH_TYPE : RO; bitpos: [5]; default: 0; * flash type: 0: nor flash, 1: nand flash */ @@ -494,6 +519,13 @@ extern "C" { #define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) #define EFUSE_FLASH_TYPE_V 0x00000001U #define EFUSE_FLASH_TYPE_S 5 +/** EFUSE_RD_RESERVE_0_134 : RW; bitpos: [8:6]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_134 0x00000007U +#define EFUSE_RD_RESERVE_0_134_M (EFUSE_RD_RESERVE_0_134_V << EFUSE_RD_RESERVE_0_134_S) +#define EFUSE_RD_RESERVE_0_134_V 0x00000007U +#define EFUSE_RD_RESERVE_0_134_S 6 /** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [9]; default: 0; * Set this bit to disable download via USB-OTG. */ @@ -501,6 +533,13 @@ extern "C" { #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 9 +/** EFUSE_RD_RESERVE_0_138 : RW; bitpos: [11:10]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_138 0x00000003U +#define EFUSE_RD_RESERVE_0_138_M (EFUSE_RD_RESERVE_0_138_V << EFUSE_RD_RESERVE_0_138_S) +#define EFUSE_RD_RESERVE_0_138_V 0x00000003U +#define EFUSE_RD_RESERVE_0_138_S 10 /** EFUSE_FLASH_TPUW : RO; bitpos: [15:12]; default: 0; * Represents the flash waiting time after power-up, in unit of ms. When the value * less than 15, the waiting time is the programmed value. Otherwise, the waiting time @@ -511,79 +550,76 @@ extern "C" { #define EFUSE_FLASH_TPUW_V 0x0000000FU #define EFUSE_FLASH_TPUW_S 12 /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [16]; default: 0; - * Represents whether Download mode is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(16)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 16 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [17]; default: 0; - * Represents whether direct boot mode is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ */ #define EFUSE_DIS_DIRECT_BOOT (BIT(17)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 17 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [18]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: + * disabled\\ 0: enabled\\ */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(18)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 18 /** EFUSE_LOCK_KM_KEY : RO; bitpos: [19]; default: 0; - * Represetns whether to lock the efuse xts key. - * 1. Lock - * 0: Unlock + * Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\ */ #define EFUSE_LOCK_KM_KEY (BIT(19)) #define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) #define EFUSE_LOCK_KM_KEY_V 0x00000001U #define EFUSE_LOCK_KM_KEY_S 19 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [20]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. - * 1: Disable - * 0: Enable + * Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ + * 1: Disable\\ 0: Enable\\ */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(20)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 20 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [21]; default: 0; - * Represents whether security download is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: + * disabled\\ */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(21)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 21 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [23:22]; default: 0; - * Represents the type of UART printing. - * 00: force enable printing - * 01: enable printing when GPIO8 is reset at low level - * 10: enable printing when GPIO8 is reset at high level - * 11: force disable printing + * Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable + * printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset + * at high level\\ 11: force disable printing\\ */ #define EFUSE_UART_PRINT_CONTROL 0x00000003U #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 22 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [24]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: forced - * 0:not forced + * Represents whether ROM code is forced to send a resume command during SPI boot.\\ + * 1: forced\\ 0:not forced\\ */ #define EFUSE_FORCE_SEND_RESUME (BIT(24)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_S 24 +/** EFUSE_RD_RESERVE_0_153 : RW; bitpos: [31:25]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_153 0x0000007FU +#define EFUSE_RD_RESERVE_0_153_M (EFUSE_RD_RESERVE_0_153_V << EFUSE_RD_RESERVE_0_153_S) +#define EFUSE_RD_RESERVE_0_153_V 0x0000007FU +#define EFUSE_RD_RESERVE_0_153_S 25 /** EFUSE_RD_REPEAT_DATA4_REG register * Represents rd_repeat_data @@ -598,28 +634,39 @@ extern "C" { #define EFUSE_SECURE_VERSION_S 0 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [16]; default: 0; * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled. - * 1: disabled - * 0: enabled + * enabled.\\ 1: disabled\\ 0: enabled\\ */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(16)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 16 /** EFUSE_HYS_EN_PAD : RO; bitpos: [17]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled. - * 1: enabled - * 0:disabled + * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: + * enabled\\ 0:disabled\\ */ #define EFUSE_HYS_EN_PAD (BIT(17)) #define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) #define EFUSE_HYS_EN_PAD_V 0x00000001U #define EFUSE_HYS_EN_PAD_S 17 +/** EFUSE_RD_RESERVE_0_178 : RW; bitpos: [31:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_178 0x00003FFFU +#define EFUSE_RD_RESERVE_0_178_M (EFUSE_RD_RESERVE_0_178_V << EFUSE_RD_RESERVE_0_178_S) +#define EFUSE_RD_RESERVE_0_178_V 0x00003FFFU +#define EFUSE_RD_RESERVE_0_178_S 18 /** EFUSE_RD_REPEAT_DATA5_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA5_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_RD_RESERVE_0_192 : RW; bitpos: [1:0]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_192 0x00000003U +#define EFUSE_RD_RESERVE_0_192_M (EFUSE_RD_RESERVE_0_192_V << EFUSE_RD_RESERVE_0_192_S) +#define EFUSE_RD_RESERVE_0_192_V 0x00000003U +#define EFUSE_RD_RESERVE_0_192_S 0 /** EFUSE_DCDC_VSET_EN : RO; bitpos: [2]; default: 0; * Select dcdc vset use efuse_dcdc_vset. */ @@ -641,6 +688,13 @@ extern "C" { #define EFUSE_DIS_SWD_M (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S) #define EFUSE_DIS_SWD_V 0x00000001U #define EFUSE_DIS_SWD_S 4 +/** EFUSE_RD_RESERVE_0_197 : RW; bitpos: [10:5]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_197 0x0000003FU +#define EFUSE_RD_RESERVE_0_197_M (EFUSE_RD_RESERVE_0_197_V << EFUSE_RD_RESERVE_0_197_S) +#define EFUSE_RD_RESERVE_0_197_V 0x0000003FU +#define EFUSE_RD_RESERVE_0_197_S 5 /** EFUSE_SECURE_BOOT_SHA384_EN : RO; bitpos: [11]; default: 0; * Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable */ @@ -657,9 +711,8 @@ extern "C" { #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_V 0x0000000FU #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_S 12 /** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN : RO; bitpos: [16]; default: 0; - * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether the ani-rollback check for the 2nd stage bootloader is + * enabled.\\1: Enabled\\0: Disabled\\ */ #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN (BIT(16)) #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S) @@ -667,9 +720,7 @@ extern "C" { #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S 16 /** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM : RO; bitpos: [17]; default: 0; * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM - * bootloader. - * 1: Enable - * 0: Disable + * bootloader.\\1: Enable\\0: Disable\\ */ #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM (BIT(17)) #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S) @@ -685,9 +736,8 @@ extern "C" { #define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V 0x00000FFFU #define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S 18 /** EFUSE_RMA_ENA : RO; bitpos: [31:30]; default: 0; - * Represents whether rma function is supported in download mode. - * 2'b01/2'b10: enabled - * 2'b00/2'b11: disabled + * Represents whether rma function is supported in download mode.\\ 2'b01/2'b10: + * enabled\\2'b00/2'b11: disabled\\ */ #define EFUSE_RMA_ENA 0x00000003U #define EFUSE_RMA_ENA_M (EFUSE_RMA_ENA_V << EFUSE_RMA_ENA_S) @@ -707,9 +757,7 @@ extern "C" { #define EFUSE_RMA_SESSION_COUNTER_S 0 /** EFUSE_RMA_NONCE_ENA : RO; bitpos: [4:3]; default: 0; * Represents whether random number NONCE is used in RMA and whether the KM module is - * used to generate the NONCE - * . 2'bx0: No NONCE - * 2'b1x: Use KM generate NONCE. + * used to generate the NONCE\\. 2'bx0: No NONCE\\ 2'b1x: Use KM generate NONCE.\\ */ #define EFUSE_RMA_NONCE_ENA 0x00000003U #define EFUSE_RMA_NONCE_ENA_M (EFUSE_RMA_NONCE_ENA_V << EFUSE_RMA_NONCE_ENA_S) @@ -717,27 +765,22 @@ extern "C" { #define EFUSE_RMA_NONCE_ENA_S 3 /** EFUSE_RMA_CHIP_INFO_SOURCE : RO; bitpos: [5]; default: 0; * Represents whether HUK_info is selected as the source for calculating CHIP_info in - * RMA. - * 1: use HUK_info - * 0: use UNIQ_id + * RMA.\\1: use HUK_info\\ 0: use UNIQ_id\\ */ #define EFUSE_RMA_CHIP_INFO_SOURCE (BIT(5)) #define EFUSE_RMA_CHIP_INFO_SOURCE_M (EFUSE_RMA_CHIP_INFO_SOURCE_V << EFUSE_RMA_CHIP_INFO_SOURCE_S) #define EFUSE_RMA_CHIP_INFO_SOURCE_V 0x00000001U #define EFUSE_RMA_CHIP_INFO_SOURCE_S 5 /** EFUSE_RMA_DISABLE_FAST_VEF : RO; bitpos: [6]; default: 0; - * Represents whether disable FAST_VEF in RMA session. - * 1: disable - * 0: enable + * Represents whether disable FAST_VEF in RMA session.\\1: disable\\0: enable\\ */ #define EFUSE_RMA_DISABLE_FAST_VEF (BIT(6)) #define EFUSE_RMA_DISABLE_FAST_VEF_M (EFUSE_RMA_DISABLE_FAST_VEF_V << EFUSE_RMA_DISABLE_FAST_VEF_S) #define EFUSE_RMA_DISABLE_FAST_VEF_V 0x00000001U #define EFUSE_RMA_DISABLE_FAST_VEF_S 6 /** EFUSE_PVT_0_GLITCH_EN : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1:Enable. - * 0:Disable + * Represents whether to enable PVT power glitch monitor function.\\1:Enable. + * \\0:Disable */ #define EFUSE_PVT_0_GLITCH_EN (BIT(7)) #define EFUSE_PVT_0_GLITCH_EN_M (EFUSE_PVT_0_GLITCH_EN_V << EFUSE_PVT_0_GLITCH_EN_S) @@ -751,9 +794,8 @@ extern "C" { #define EFUSE_PVT_0_GLITCH_MODE_V 0x00000003U #define EFUSE_PVT_0_GLITCH_MODE_S 8 /** EFUSE_PVT_1_GLITCH_EN : RO; bitpos: [10]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1:Enable. - * 0:Disable + * Represents whether to enable PVT power glitch monitor function.\\1:Enable. + * \\0:Disable */ #define EFUSE_PVT_1_GLITCH_EN (BIT(10)) #define EFUSE_PVT_1_GLITCH_EN_M (EFUSE_PVT_1_GLITCH_EN_V << EFUSE_PVT_1_GLITCH_EN_S) @@ -767,9 +809,7 @@ extern "C" { #define EFUSE_PVT_1_GLITCH_MODE_V 0x00000003U #define EFUSE_PVT_1_GLITCH_MODE_S 11 /** EFUSE_PMU_FLASH_POWER_SEL : RO; bitpos: [13]; default: 0; - * FLASH power select. - * 1'b1: use 3.3V - * 1'b0: use 1.8V + * FLASH power select.\\ 1'b1: use 3.3V\\1'b0: use 1.8V */ #define EFUSE_PMU_FLASH_POWER_SEL (BIT(13)) #define EFUSE_PMU_FLASH_POWER_SEL_M (EFUSE_PMU_FLASH_POWER_SEL_V << EFUSE_PMU_FLASH_POWER_SEL_S) @@ -792,32 +832,35 @@ extern "C" { #define EFUSE_POWER_GLITCH_EN_S 15 /** EFUSE_ENA_XTS_SHADOW : RO; bitpos: [19]; default: 0; * Represents whether to enable XTS-AES shadow core countermeasure against fault - * injection attacks. - * 0: Disabled - * 1: Enabled + * injection attacks. \\ 0: Disabled\\ 1: Enabled\\ */ #define EFUSE_ENA_XTS_SHADOW (BIT(19)) #define EFUSE_ENA_XTS_SHADOW_M (EFUSE_ENA_XTS_SHADOW_V << EFUSE_ENA_XTS_SHADOW_S) #define EFUSE_ENA_XTS_SHADOW_V 0x00000001U #define EFUSE_ENA_XTS_SHADOW_S 19 /** EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER : RO; bitpos: [20]; default: 0; - * Represents whether to enable ciphertext scrambler for external memory . - * 0: Disabled - * 1: Enabled + * Represents whether to enable ciphertext scrambler for external memory . \\ 0: + * Disabled\\ 1: Enabled\\ */ #define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER (BIT(20)) #define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_M (EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_V << EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_S) #define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_V 0x00000001U #define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_S 20 /** EFUSE_RE_ENABLE_JTAG_SOURCE : RO; bitpos: [21]; default: 0; - * Represents which Crypto peripheral is selected for re-enabling JTAG. - * 0: RMA - * 1: HMAC + * Represents which Crypto peripheral is selected for re-enabling JTAG. \\ 0: RMA\\ 1: + * HMAC\\ */ #define EFUSE_RE_ENABLE_JTAG_SOURCE (BIT(21)) #define EFUSE_RE_ENABLE_JTAG_SOURCE_M (EFUSE_RE_ENABLE_JTAG_SOURCE_V << EFUSE_RE_ENABLE_JTAG_SOURCE_S) #define EFUSE_RE_ENABLE_JTAG_SOURCE_V 0x00000001U #define EFUSE_RE_ENABLE_JTAG_SOURCE_S 21 +/** EFUSE_RD_RESERVE_0_246 : RW; bitpos: [31:22]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_246 0x000003FFU +#define EFUSE_RD_RESERVE_0_246_M (EFUSE_RD_RESERVE_0_246_V << EFUSE_RD_RESERVE_0_246_S) +#define EFUSE_RD_RESERVE_0_246_V 0x000003FFU +#define EFUSE_RD_RESERVE_0_246_S 22 /** EFUSE_RD_REPEAT_DATA7_REG register * Represents rd_repeat_data @@ -830,6 +873,13 @@ extern "C" { #define EFUSE_REPEAT7_RSVD_M (EFUSE_REPEAT7_RSVD_V << EFUSE_REPEAT7_RSVD_S) #define EFUSE_REPEAT7_RSVD_V 0x0000FFFFU #define EFUSE_REPEAT7_RSVD_S 0 +/** EFUSE_RD_RESERVE_0_272 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_272 0x0000FFFFU +#define EFUSE_RD_RESERVE_0_272_M (EFUSE_RD_RESERVE_0_272_V << EFUSE_RD_RESERVE_0_272_S) +#define EFUSE_RD_RESERVE_0_272_V 0x0000FFFFU +#define EFUSE_RD_RESERVE_0_272_S 16 /** EFUSE_RD_MAC_SYS0_REG register * Represents rd_mac_sys @@ -862,29 +912,125 @@ extern "C" { #define EFUSE_MAC_EXT_V 0x0000FFFFU #define EFUSE_MAC_EXT_S 16 +/** EFUSE_RD_MAC_SYS2_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_0 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_S 0 +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_1 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_S 14 + /** EFUSE_RD_MAC_SYS3_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [21:18]; default: 0; + * Minor chip version + */ +#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU +#define EFUSE_WAFER_VERSION_MINOR_S 18 +/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [23:22]; default: 0; + * Major chip version + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 22 +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [24]; default: 0; + * Disables check of wafer version major + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(24)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 24 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [25]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(25)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 25 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [28:26]; default: 0; + * BLK_VERSION_MINOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 26 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [30:29]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 29 +/** EFUSE_PSRAM_CAP : R; bitpos: [31]; default: 0; + * Psram capacity + */ +#define EFUSE_PSRAM_CAP (BIT(31)) +#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S) +#define EFUSE_PSRAM_CAP_V 0x00000001U +#define EFUSE_PSRAM_CAP_S 31 /** EFUSE_RD_MAC_SYS4_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. +/** EFUSE_PSRAM_CAP_1 : R; bitpos: [1:0]; default: 0; + * Psram capacity */ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_S 0 +#define EFUSE_PSRAM_CAP_1 0x00000003U +#define EFUSE_PSRAM_CAP_1_M (EFUSE_PSRAM_CAP_1_V << EFUSE_PSRAM_CAP_1_S) +#define EFUSE_PSRAM_CAP_1_V 0x00000003U +#define EFUSE_PSRAM_CAP_1_S 0 +/** EFUSE_TEMP : R; bitpos: [3:2]; default: 0; + * Maximum ambient temperature that ESP Chip can work properly + */ +#define EFUSE_TEMP 0x00000003U +#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S) +#define EFUSE_TEMP_V 0x00000003U +#define EFUSE_TEMP_S 2 +/** EFUSE_PSRAM_VENDOR : R; bitpos: [5:4]; default: 0; + * Psram vendor + */ +#define EFUSE_PSRAM_VENDOR 0x00000003U +#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S) +#define EFUSE_PSRAM_VENDOR_V 0x00000003U +#define EFUSE_PSRAM_VENDOR_S 4 +/** EFUSE_PKG_VERSION : R; bitpos: [7:6]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000003U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000003U +#define EFUSE_PKG_VERSION_S 6 +/** EFUSE_RESERVED_1_136 : R; bitpos: [31:8]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_136 0x00FFFFFFU +#define EFUSE_RESERVED_1_136_M (EFUSE_RESERVED_1_136_V << EFUSE_RESERVED_1_136_S) +#define EFUSE_RESERVED_1_136_V 0x00FFFFFFU +#define EFUSE_RESERVED_1_136_S 8 /** EFUSE_RD_MAC_SYS5_REG register * Represents rd_mac_sys @@ -902,49 +1048,49 @@ extern "C" { * Represents rd_sys_part1_data0 */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register * Represents rd_sys_part1_data1 */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register * Represents rd_sys_part1_data2 */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register * Represents rd_sys_part1_data3 */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register * Represents rd_sys_part1_data4 @@ -1070,25 +1216,39 @@ extern "C" { * Represents rd_usr_data6 */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0xa0) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register * Represents rd_usr_data7 */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0xa4) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register * Represents rd_key0_data0 @@ -1647,14 +1807,75 @@ extern "C" { */ #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x160) /** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [0]; default: 0; - * Represents whether enable usb device exchange pins of D+ and D- or not. - * 1: enabled - * 0: disabled + * Represents whether enable usb device exchange pins of D+ and D- or not. \\ 1: + * enabled\\ 0: disabled\\ */ #define EFUSE_USB_DEVICE_EXCHG_PINS (BIT(0)) #define EFUSE_USB_DEVICE_EXCHG_PINS_M (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S) #define EFUSE_USB_DEVICE_EXCHG_PINS_V 0x00000001U #define EFUSE_USB_DEVICE_EXCHG_PINS_S 0 +/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [2:1]; default: 0; + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DEVICE_DREFH 0x00000003U +#define EFUSE_USB_DEVICE_DREFH_M (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S) +#define EFUSE_USB_DEVICE_DREFH_V 0x00000003U +#define EFUSE_USB_DEVICE_DREFH_S 1 +/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [4:3]; default: 0; + * Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step + * of 80 mV. + */ +#define EFUSE_USB_DEVICE_DREFL 0x00000003U +#define EFUSE_USB_DEVICE_DREFL_M (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S) +#define EFUSE_USB_DEVICE_DREFL_V 0x00000003U +#define EFUSE_USB_DEVICE_DREFL_S 3 +/** EFUSE_RD_RESERVE_9_197 : RW; bitpos: [16:5]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_9_197 0x00000FFFU +#define EFUSE_RD_RESERVE_9_197_M (EFUSE_RD_RESERVE_9_197_V << EFUSE_RD_RESERVE_9_197_S) +#define EFUSE_RD_RESERVE_9_197_V 0x00000FFFU +#define EFUSE_RD_RESERVE_9_197_S 5 +/** EFUSE_PVT_0_CELL_SELECT : RO; bitpos: [23:17]; default: 0; + * Power glitch monitor PVT cell select. + */ +#define EFUSE_PVT_0_CELL_SELECT 0x0000007FU +#define EFUSE_PVT_0_CELL_SELECT_M (EFUSE_PVT_0_CELL_SELECT_V << EFUSE_PVT_0_CELL_SELECT_S) +#define EFUSE_PVT_0_CELL_SELECT_V 0x0000007FU +#define EFUSE_PVT_0_CELL_SELECT_S 17 +/** EFUSE_PVT_1_CELL_SELECT : RO; bitpos: [30:24]; default: 0; + * Power glitch monitor PVT cell select. + */ +#define EFUSE_PVT_1_CELL_SELECT 0x0000007FU +#define EFUSE_PVT_1_CELL_SELECT_M (EFUSE_PVT_1_CELL_SELECT_V << EFUSE_PVT_1_CELL_SELECT_S) +#define EFUSE_PVT_1_CELL_SELECT_V 0x0000007FU +#define EFUSE_PVT_1_CELL_SELECT_S 24 +/** EFUSE_RD_RESERVE_9_223 : RW; bitpos: [31]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_9_223 (BIT(31)) +#define EFUSE_RD_RESERVE_9_223_M (EFUSE_RD_RESERVE_9_223_V << EFUSE_RD_RESERVE_9_223_S) +#define EFUSE_RD_RESERVE_9_223_V 0x00000001U +#define EFUSE_RD_RESERVE_9_223_S 31 + +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Represents rd_sys_part2_data + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_PVT_0_LIMIT : RO; bitpos: [15:0]; default: 0; + * Power glitch monitor threthold. + */ +#define EFUSE_PVT_0_LIMIT 0x0000FFFFU +#define EFUSE_PVT_0_LIMIT_M (EFUSE_PVT_0_LIMIT_V << EFUSE_PVT_0_LIMIT_S) +#define EFUSE_PVT_0_LIMIT_V 0x0000FFFFU +#define EFUSE_PVT_0_LIMIT_S 0 +/** EFUSE_PVT_1_LIMIT : RO; bitpos: [31:16]; default: 0; + * Power glitch monitor threthold. + */ +#define EFUSE_PVT_1_LIMIT 0x0000FFFFU +#define EFUSE_PVT_1_LIMIT_M (EFUSE_PVT_1_LIMIT_V << EFUSE_PVT_1_LIMIT_S) +#define EFUSE_PVT_1_LIMIT_V 0x0000FFFFU +#define EFUSE_PVT_1_LIMIT_S 16 /** EFUSE_RD_REPEAT_DATA_ERR0_REG register * Represents rd_repeat_data_err @@ -1674,6 +1895,13 @@ extern "C" { #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_USB_JTAG_ERR_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ @@ -1723,6 +1951,13 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_DIS_WIFI6_ERR : RO; bitpos: [22]; default: 0; + * Represents the programming error of EFUSE_DIS_WIFI6 + */ +#define EFUSE_DIS_WIFI6_ERR (BIT(22)) +#define EFUSE_DIS_WIFI6_ERR_M (EFUSE_DIS_WIFI6_ERR_V << EFUSE_DIS_WIFI6_ERR_S) +#define EFUSE_DIS_WIFI6_ERR_V 0x00000001U +#define EFUSE_DIS_WIFI6_ERR_S 22 /** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [27:23]; default: 0; * Represents the programming error of EFUSE_HUK_GEN_STATE */ @@ -2205,143 +2440,136 @@ extern "C" { */ #define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x188) /** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_mac_sys */ #define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U #define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) #define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U #define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 /** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. */ #define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) #define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) #define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U #define EFUSE_RD_MAC_SYS_FAIL_S 3 /** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part1_data */ #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 /** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. */ #define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) #define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) #define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U #define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 /** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_usr_data */ #define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) #define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_USR_DATA_ERR_NUM_S 8 /** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_USR_DATA_FAIL (BIT(11)) #define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) #define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U #define EFUSE_RD_USR_DATA_FAIL_S 11 /** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key0_data */ #define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) #define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 /** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) #define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) #define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY0_DATA_FAIL_S 15 /** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key1_data */ #define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) #define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 /** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) #define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) #define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY1_DATA_FAIL_S 19 /** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key2_data */ #define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) #define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 /** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) #define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) #define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY2_DATA_FAIL_S 23 /** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key3_data */ #define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) #define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 /** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) #define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) #define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY3_DATA_FAIL_S 27 /** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key4_data */ #define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) #define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 /** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. */ #define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) #define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) @@ -2353,18 +2581,17 @@ extern "C" { */ #define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x18c) /** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 0 /** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. */ #define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(3)) #define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) @@ -2389,36 +2616,30 @@ extern "C" { */ #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect + * Configures whether to force power down eFuse SRAM.\\ 1: Force\\ 0: No effect\\ */ #define EFUSE_MEM_FORCE_PD (BIT(0)) #define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) #define EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_MEM_FORCE_PD_S 0 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect + * Configures whether to force activate clock signal of eFuse SRAM.\\ 1: Force + * activate\\ 0: No effect\\ */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 /** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect + * Configures whether to force power up eFuse SRAM.\\ 1: Force\\ 0: No effect\\ */ #define EFUSE_MEM_FORCE_PU (BIT(2)) #define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) #define EFUSE_MEM_FORCE_PU_V 0x00000001U #define EFUSE_MEM_FORCE_PU_S 2 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers + * Configures whether to force enable eFuse register configuration clock signal.\\ 1: + * Force\\ 0: The clock is enabled only during the reading and writing of registers\\ */ #define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) @@ -2430,10 +2651,8 @@ extern "C" { */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect + * Configures operation command type.\\ 0x5A5A: Program operation command\\ 0x5AA5: + * Read operation command\\ Other values: No effect\\ */ #define EFUSE_OP_CODE 0x0000FFFFU #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) @@ -2506,15 +2725,55 @@ extern "C" { */ #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d4) /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state + * Represents the state of the eFuse state machine.\\ 0: Reset state, the initial + * state after power-up\\ 1: Idle state\\ Other values: Non-idle state\\ */ #define EFUSE_STATE 0x0000000FU #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) #define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * Represents the value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * Represents the value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * Represents the value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * Represents the value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * Represents the value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * Represents the value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; * Represents the number of block valid bit. */ @@ -2528,18 +2787,14 @@ extern "C" { */ #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d8) /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect + * Configures whether to send read commands.\\ 1: Send\\ 0: No effect\\ */ #define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) #define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect + * Configures whether to send programming commands.\\ 1: Send\\ 0: No effect\\ */ #define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) @@ -2659,9 +2914,8 @@ extern "C" { #define EFUSE_DAC_NUM_V 0x000000FFU #define EFUSE_DAC_NUM_S 9 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce + * Configures whether to reduce the power supply of programming voltage.\\ 0: Not + * reduce\\ 1: Reduce\\ */ #define EFUSE_OE_CLR (BIT(17)) #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) @@ -2761,9 +3015,8 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1fc) /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass + * Configures whether to bypass the Reed-Solomon (RS) correction step.\\ 0: Not + * bypass\\ 1: Bypass\\ */ #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) #define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) @@ -2777,9 +3030,8 @@ extern "C" { #define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_S 1 /** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect + * Configures whether to update multi-bit register signals.\\ 1: Update\\ 0: No + * effect\\ */ #define EFUSE_UPDATE (BIT(12)) #define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) diff --git a/components/soc/esp32s31/register/soc/efuse_struct.h b/components/soc/esp32s31/register/soc/efuse_struct.h index 85266450cfe..b05187d5fd5 100644 --- a/components/soc/esp32s31/register/soc/efuse_struct.h +++ b/components/soc/esp32s31/register/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -47,9 +47,8 @@ typedef union { /** wr_dis : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled. For * mapping between the bits of this field and the eFuse memory bits, please refer to - * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. - * 1: Disabled - * 0: Enabled + * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.\\1: + * Disabled\\0: Enabled\\ */ uint32_t wr_dis:32; }; @@ -63,72 +62,77 @@ typedef union { struct { /** rd_dis : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block9) is disabled or - * enabled. - * 1: disabled - * 0: enabled + * enabled.\\ 1: disabled\\ 0: enabled\\ */ uint32_t rd_dis:7; - uint32_t reserved_7:3; + /** rd_reserve_0_39 : RW; bitpos: [9:7]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_39:3; /** dis_usb_jtag : RO; bitpos: [10]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: + * disabled\\ 0: enabled\\ */ uint32_t dis_usb_jtag:1; - uint32_t reserved_11:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ + */ + uint32_t dis_usb_serial_jtag:1; /** dis_force_download : RO; bitpos: [12]; default: 0; * Represents whether the function that forces chip into download mode is disabled or - * enabled. - * 1: disabled - * 0: enabled + * enabled.\\ 1: disabled\\ 0: enabled\\ */ uint32_t dis_force_download:1; /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot_mode_download is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled.\\ 1: disabled\\ 0: enabled\\ */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; * Represents whether the selection between usb_to_jtag and pad_to_jtag through * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled. - * 1: enabled - * 0: disabled + * is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. - * Odd number: disabled - * Even number: enabled + * Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even + * number: enabled\\ */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). - * 1: disabled - * 0: enabled + * Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ + * 0: enabled\\ */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode). - * 1: disabled - * 0: enabled + * mode).\\ 1: disabled\\ 0: enabled\\ */ uint32_t dis_download_manual_encrypt:1; - uint32_t reserved_21:2; + /** rd_reserve_0_53 : RW; bitpos: [21]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_53:1; + /** dis_wifi6 : RO; bitpos: [22]; default: 0; + * Represents whether the WIFI6 feature is enabled or disabled. 1: WIFI6 is disabled, 0: + * WIFI6 is enabled. + */ + uint32_t dis_wifi6:1; /** huk_gen_state : RO; bitpos: [27:23]; default: 0; * Represents the control of validation of HUK generate mode. Odd of 1 is invalid, * even of 1 is valid. */ uint32_t huk_gen_state:5; - uint32_t reserved_28:4; + /** rd_reserve_0_60 : RW; bitpos: [31:28]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_60:4; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; @@ -143,33 +147,25 @@ typedef union { * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles */ uint32_t km_rnd_switch_cycle:1; - uint32_t reserved_1:1; + /** rd_reserve_0_65 : RW; bitpos: [1]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_65:1; /** km_disable_deploy_mode : RO; bitpos: [6:2]; default: 0; - * Represents whether the deploy mode of key manager is disable or not. - * 1: disabled - * 0: enabled. - * bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, bit3: ds & rma - * nonce, bit4: psram + * Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled + * \\ 0: enabled.\\ bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, + * bit3: ds & rma nonce, bit4: psram */ uint32_t km_disable_deploy_mode:5; /** km_deploy_only_once : RO; bitpos: [11:7]; default: 0; * Represents whether corresponding key can only be deployed once. 1 is true, 0 is - * false. - * 0: ecsda - * 1: flash & spi boot srambler - * 2: hmac & aes - * 3: ds & rma nonce - * 4: psram + * false. \\ 0: ecsda\\ 1: flash & spi boot srambler\\ 2: hmac & aes\\ 3: ds & rma + * nonce\\ 4: psram\\ */ uint32_t km_deploy_only_once:5; /** force_use_key_manager_key : RO; bitpos: [16:12]; default: 0; * Represents whether corresponding key must come from key manager. 1 is true, 0 is - * false. - * 0: ecsda - * 1: flash - * 2: reserved - * 3: reserved - * 4: psram + * false.\\ 0: ecsda\\ 1: flash\\ 2: reserved\\ 3: reserved\\ 4: psram\\ */ uint32_t force_use_key_manager_key:5; /** force_disable_sw_init_key : RO; bitpos: [17]; default: 0; @@ -179,50 +175,45 @@ typedef union { uint32_t force_disable_sw_init_key:1; /** km_xts_key_length_256 : RO; bitpos: [18]; default: 0; * Represents whether to configure flash encryption use xts-128 key. else use xts-256 - * key. - * 0: 128-bit key - * 1: 256-bit key + * key. \\ 0: 128-bit key \\ 1: 256-bit key\\ */ uint32_t km_xts_key_length_256:1; /** wdt_delay_sel : RO; bitpos: [19]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout. - * 0: Original threshold configuration value of STG0 *2 - * 1: Original threshold configuration value of STG0 *4 - * 2: Original threshold configuration value of STG0 *8 - * 3: Original threshold configuration value of STG0 *16 + * Represents the threshold level of the RTC watchdog STG0 timeout.\\0: Original + * threshold configuration value of STG0 *2 \\1: Original threshold configuration + * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: + * Original threshold configuration value of STG0 *16 \\ */ uint32_t wdt_delay_sel:1; /** dis_sm_crypt : RO; bitpos: [20]; default: 0; - * Represents whether to disable all the SM crypto functions, including SM2, SM3. - * 1: disabled - * 0: enabled + * Represents whether to disable all the SM crypto functions, including SM2, SM3.\\ 1: + * disabled\\ 0: enabled\\ */ uint32_t dis_sm_crypt:1; /** spi_boot_crypt_cnt : RO; bitpos: [23:21]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled. - * Odd number of 1: enabled - * Even number of 1: disabled + * Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of + * 1: enabled\\ Even number of 1: disabled\\ */ uint32_t spi_boot_crypt_cnt:3; /** secure_boot_key_revoke0 : RO; bitpos: [24]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ */ uint32_t secure_boot_key_revoke0:1; /** secure_boot_key_revoke1 : RO; bitpos: [25]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ */ uint32_t secure_boot_key_revoke1:1; /** secure_boot_key_revoke2 : RO; bitpos: [26]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: + * enabled\\ 0: disabled\\ */ uint32_t secure_boot_key_revoke2:1; - uint32_t reserved_27:5; + /** rd_reserve_0_91 : RW; bitpos: [31:27]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_91:5; }; uint32_t val; } efuse_rd_repeat_data1_reg_t; @@ -253,15 +244,13 @@ typedef union { */ uint32_t key_purpose_4:5; /** ecc_force_const_time : RO; bitpos: [25]; default: 0; - * Represents whether permanently turn on ECC const-time mode. - * 1: turn on - * 0: turn off + * Represents whether permanently turn on ECC const-time mode. \\ 1: turn on\\ 0: turn + * off\\ */ uint32_t ecc_force_const_time:1; /** ecdsa_disable_soft_k : RO; bitpos: [26]; default: 0; - * Represents whether permanently turn off ECDSA software set KEY. - * 1: turn off - * 0: turn on + * Represents whether permanently turn off ECDSA software set KEY.\\ 1: turn off\\ 0: + * turn on\\ */ uint32_t ecdsa_disable_soft_k:1; /** sec_dpa_level : RO; bitpos: [28:27]; default: 0; @@ -269,12 +258,14 @@ typedef union { */ uint32_t sec_dpa_level:2; /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0; - * Represents whether to enable xts clock anti-dpa attack function. - * 0: Disabled. - * 1: Enabled + * Represents whether to enable xts clock anti-dpa attack function.\\0: Disabled. \\1: + * Enabled\\ */ uint32_t xts_dpa_clk_enable:1; - uint32_t reserved_30:2; + /** rd_reserve_0_126 : RW; bitpos: [31:30]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_126:2; }; uint32_t val; } efuse_rd_repeat_data2_reg_t; @@ -285,35 +276,40 @@ typedef union { typedef union { struct { /** xts_dpa_pseudo_level : RO; bitpos: [1:0]; default: 0; - * Represents the control of the xts pseudo-round anti-dpa attack function. - * 0: controlled by register. - * 1-3: the higher the value is, the more pseudo-rounds are inserted to the xts-aes - * calculation + * Represents the control of the xts pseudo-round anti-dpa attack function.\\ 0: + * controlled by register.\\ 1-3: the higher the value is, the more pseudo-rounds are + * inserted to the xts-aes calculation\\ */ uint32_t xts_dpa_pseudo_level:2; /** secure_boot_en : RO; bitpos: [2]; default: 0; - * Represents whether secure boot is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ */ uint32_t secure_boot_en:1; /** secure_boot_aggressive_revoke : RO; bitpos: [3]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled. - * 1: enabled. - * 0: disabled + * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: + * enabled.\\ 0: disabled\\ */ uint32_t secure_boot_aggressive_revoke:1; - uint32_t reserved_4:1; + /** rd_reserve_0_132 : RW; bitpos: [4]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_132:1; /** flash_type : RO; bitpos: [5]; default: 0; * flash type: 0: nor flash, 1: nand flash */ uint32_t flash_type:1; - uint32_t reserved_6:3; + /** rd_reserve_0_134 : RW; bitpos: [8:6]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_134:3; /** dis_usb_otg_download_mode : RO; bitpos: [9]; default: 0; * Set this bit to disable download via USB-OTG. */ uint32_t dis_usb_otg_download_mode:1; - uint32_t reserved_10:2; + /** rd_reserve_0_138 : RW; bitpos: [11:10]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_138:2; /** flash_tpuw : RO; bitpos: [15:12]; default: 0; * Represents the flash waiting time after power-up, in unit of ms. When the value * less than 15, the waiting time is the programmed value. Otherwise, the waiting time @@ -321,56 +317,49 @@ typedef union { */ uint32_t flash_tpuw:4; /** dis_download_mode : RO; bitpos: [16]; default: 0; - * Represents whether Download mode is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [17]; default: 0; - * Represents whether direct boot mode is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: + * enabled\\ */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [18]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. - * 1: disabled - * 0: enabled + * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: + * disabled\\ 0: enabled\\ */ uint32_t dis_usb_serial_jtag_rom_print:1; /** lock_km_key : RO; bitpos: [19]; default: 0; - * Represetns whether to lock the efuse xts key. - * 1. Lock - * 0: Unlock + * Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\ */ uint32_t lock_km_key:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [20]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. - * 1: Disable - * 0: Enable + * Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ + * 1: Disable\\ 0: Enable\\ */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [21]; default: 0; - * Represents whether security download is enabled or disabled. - * 1: enabled - * 0: disabled + * Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: + * disabled\\ */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [23:22]; default: 0; - * Represents the type of UART printing. - * 00: force enable printing - * 01: enable printing when GPIO8 is reset at low level - * 10: enable printing when GPIO8 is reset at high level - * 11: force disable printing + * Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable + * printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset + * at high level\\ 11: force disable printing\\ */ uint32_t uart_print_control:2; /** force_send_resume : RO; bitpos: [24]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: forced - * 0:not forced + * Represents whether ROM code is forced to send a resume command during SPI boot.\\ + * 1: forced\\ 0:not forced\\ */ uint32_t force_send_resume:1; - uint32_t reserved_25:7; + /** rd_reserve_0_153 : RW; bitpos: [31:25]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_153:7; }; uint32_t val; } efuse_rd_repeat_data3_reg_t; @@ -386,18 +375,18 @@ typedef union { uint32_t secure_version:16; /** secure_boot_disable_fast_wake : RO; bitpos: [16]; default: 0; * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled. - * 1: disabled - * 0: enabled + * enabled.\\ 1: disabled\\ 0: enabled\\ */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad : RO; bitpos: [17]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled. - * 1: enabled - * 0:disabled + * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: + * enabled\\ 0:disabled\\ */ uint32_t hys_en_pad:1; - uint32_t reserved_18:14; + /** rd_reserve_0_178 : RW; bitpos: [31:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_178:14; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; @@ -407,7 +396,10 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:2; + /** rd_reserve_0_192 : RW; bitpos: [1:0]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_192:2; /** dcdc_vset_en : RO; bitpos: [2]; default: 0; * Select dcdc vset use efuse_dcdc_vset. */ @@ -420,7 +412,10 @@ typedef union { * Set this bit to disable super-watchdog. */ uint32_t dis_swd:1; - uint32_t reserved_5:6; + /** rd_reserve_0_197 : RW; bitpos: [10:5]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_197:6; /** secure_boot_sha384_en : RO; bitpos: [11]; default: 0; * Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable */ @@ -431,16 +426,13 @@ typedef union { */ uint32_t bootloader_anti_rollback_secure_version:4; /** bootloader_anti_rollback_en : RO; bitpos: [16]; default: 0; - * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether the ani-rollback check for the 2nd stage bootloader is + * enabled.\\1: Enabled\\0: Disabled\\ */ uint32_t bootloader_anti_rollback_en:1; /** bootloader_anti_rollback_update_in_rom : RO; bitpos: [17]; default: 0; * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM - * bootloader. - * 1: Enable - * 0: Disable + * bootloader.\\1: Enable\\0: Disable\\ */ uint32_t bootloader_anti_rollback_update_in_rom:1; /** recovery_bootloader_flash_sector : RO; bitpos: [29:18]; default: 0; @@ -450,9 +442,8 @@ typedef union { */ uint32_t recovery_bootloader_flash_sector:12; /** rma_ena : RO; bitpos: [31:30]; default: 0; - * Represents whether rma function is supported in download mode. - * 2'b01/2'b10: enabled - * 2'b00/2'b11: disabled + * Represents whether rma function is supported in download mode.\\ 2'b01/2'b10: + * enabled\\2'b00/2'b11: disabled\\ */ uint32_t rma_ena:2; }; @@ -470,28 +461,21 @@ typedef union { uint32_t rma_session_counter:3; /** rma_nonce_ena : RO; bitpos: [4:3]; default: 0; * Represents whether random number NONCE is used in RMA and whether the KM module is - * used to generate the NONCE - * . 2'bx0: No NONCE - * 2'b1x: Use KM generate NONCE. + * used to generate the NONCE\\. 2'bx0: No NONCE\\ 2'b1x: Use KM generate NONCE.\\ */ uint32_t rma_nonce_ena:2; /** rma_chip_info_source : RO; bitpos: [5]; default: 0; * Represents whether HUK_info is selected as the source for calculating CHIP_info in - * RMA. - * 1: use HUK_info - * 0: use UNIQ_id + * RMA.\\1: use HUK_info\\ 0: use UNIQ_id\\ */ uint32_t rma_chip_info_source:1; /** rma_disable_fast_vef : RO; bitpos: [6]; default: 0; - * Represents whether disable FAST_VEF in RMA session. - * 1: disable - * 0: enable + * Represents whether disable FAST_VEF in RMA session.\\1: disable\\0: enable\\ */ uint32_t rma_disable_fast_vef:1; /** pvt_0_glitch_en : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1:Enable. - * 0:Disable + * Represents whether to enable PVT power glitch monitor function.\\1:Enable. + * \\0:Disable */ uint32_t pvt_0_glitch_en:1; /** pvt_0_glitch_mode : RO; bitpos: [9:8]; default: 0; @@ -499,9 +483,8 @@ typedef union { */ uint32_t pvt_0_glitch_mode:2; /** pvt_1_glitch_en : RO; bitpos: [10]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1:Enable. - * 0:Disable + * Represents whether to enable PVT power glitch monitor function.\\1:Enable. + * \\0:Disable */ uint32_t pvt_1_glitch_en:1; /** pvt_1_glitch_mode : RO; bitpos: [12:11]; default: 0; @@ -509,9 +492,7 @@ typedef union { */ uint32_t pvt_1_glitch_mode:2; /** pmu_flash_power_sel : RO; bitpos: [13]; default: 0; - * FLASH power select. - * 1'b1: use 3.3V - * 1'b0: use 1.8V + * FLASH power select.\\ 1'b1: use 3.3V\\1'b0: use 1.8V */ uint32_t pmu_flash_power_sel:1; /** pmu_flash_power_sel_en : RO; bitpos: [14]; default: 0; @@ -525,24 +506,23 @@ typedef union { uint32_t power_glitch_en:4; /** ena_xts_shadow : RO; bitpos: [19]; default: 0; * Represents whether to enable XTS-AES shadow core countermeasure against fault - * injection attacks. - * 0: Disabled - * 1: Enabled + * injection attacks. \\ 0: Disabled\\ 1: Enabled\\ */ uint32_t ena_xts_shadow:1; /** ena_spi_boot_crypt_scrambler : RO; bitpos: [20]; default: 0; - * Represents whether to enable ciphertext scrambler for external memory . - * 0: Disabled - * 1: Enabled + * Represents whether to enable ciphertext scrambler for external memory . \\ 0: + * Disabled\\ 1: Enabled\\ */ uint32_t ena_spi_boot_crypt_scrambler:1; /** re_enable_jtag_source : RO; bitpos: [21]; default: 0; - * Represents which Crypto peripheral is selected for re-enabling JTAG. - * 0: RMA - * 1: HMAC + * Represents which Crypto peripheral is selected for re-enabling JTAG. \\ 0: RMA\\ 1: + * HMAC\\ */ uint32_t re_enable_jtag_source:1; - uint32_t reserved_22:10; + /** rd_reserve_0_246 : RW; bitpos: [31:22]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_246:10; }; uint32_t val; } efuse_rd_repeat_data6_reg_t; @@ -556,7 +536,10 @@ typedef union { * Reserved. */ uint32_t repeat7_rsvd:16; - uint32_t reserved_16:16; + /** rd_reserve_0_272 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_272:16; }; uint32_t val; } efuse_rd_repeat_data7_reg_t; @@ -593,16 +576,60 @@ typedef union { uint32_t val; } efuse_rd_mac_sys1_reg_t; +/** Type of rd_mac_sys2 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_0:14; + /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_1:18; + }; + uint32_t val; +} efuse_rd_mac_sys2_reg_t; + /** Type of rd_mac_sys3 register * Represents rd_mac_sys */ typedef union { struct { - uint32_t reserved_0:18; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. */ - uint32_t sys_data_part0_0:14; + uint32_t mac_reserved_2:18; + /** wafer_version_minor : R; bitpos: [21:18]; default: 0; + * Minor chip version + */ + uint32_t wafer_version_minor:4; + /** wafer_version_major : R; bitpos: [23:22]; default: 0; + * Major chip version + */ + uint32_t wafer_version_major:2; + /** disable_wafer_version_major : R; bitpos: [24]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [25]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** blk_version_minor : R; bitpos: [28:26]; default: 0; + * BLK_VERSION_MINOR of BLOCK2 + */ + uint32_t blk_version_minor:3; + /** blk_version_major : R; bitpos: [30:29]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ + uint32_t blk_version_major:2; + /** psram_cap : R; bitpos: [31]; default: 0; + * Psram capacity + */ + uint32_t psram_cap:1; }; uint32_t val; } efuse_rd_mac_sys3_reg_t; @@ -612,10 +639,26 @@ typedef union { */ typedef union { struct { - /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. + /** psram_cap_1 : R; bitpos: [1:0]; default: 0; + * Psram capacity */ - uint32_t sys_data_part0_1:32; + uint32_t psram_cap_1:2; + /** temp : R; bitpos: [3:2]; default: 0; + * Maximum ambient temperature that ESP Chip can work properly + */ + uint32_t temp:2; + /** psram_vendor : R; bitpos: [5:4]; default: 0; + * Psram vendor + */ + uint32_t psram_vendor:2; + /** pkg_version : R; bitpos: [7:6]; default: 0; + * Package version + */ + uint32_t pkg_version:2; + /** reserved_1_136 : R; bitpos: [31:8]; default: 0; + * reserved + */ + uint32_t reserved_1_136:24; }; uint32_t val; } efuse_rd_mac_sys4_reg_t; @@ -635,34 +678,223 @@ typedef union { /** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan +/** Type of rd_sys_part1_data0 register + * Represents rd_sys_part1_data0 */ typedef union { struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ - uint32_t sys_data_part1_n:32; + uint32_t optional_unique_id:32; }; uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Represents rd_sys_part1_data1 + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Represents rd_sys_part1_data2 + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Represents rd_sys_part1_data3 + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Represents rd_sys_part1_data4 + */ +typedef union { + struct { + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_4:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Represents rd_sys_part1_data5 + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Represents rd_sys_part1_data6 + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Represents rd_sys_part1_data7 + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; /** Group: block3 registers */ -/** Type of rd_usr_datan register - * Represents rd_usr_datan +/** Type of rd_usr_data0 register + * Represents rd_usr_data0 */ typedef union { struct { - /** usr_datan : RO; bitpos: [31:0]; default: 0; + /** usr_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ - uint32_t usr_datan:32; + uint32_t usr_data0:32; }; uint32_t val; -} efuse_rd_usr_datan_reg_t; +} efuse_rd_usr_data0_reg_t; +/** Type of rd_usr_data1 register + * Represents rd_usr_data1 + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Represents rd_usr_data2 + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Represents rd_usr_data3 + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Represents rd_usr_data4 + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Represents rd_usr_data5 + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Represents rd_usr_data6 + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Represents rd_usr_data7 + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; /** Group: block4 registers */ /** Type of rd_key0_datan register @@ -824,16 +1056,56 @@ typedef union { typedef union { struct { /** usb_device_exchg_pins : RO; bitpos: [0]; default: 0; - * Represents whether enable usb device exchange pins of D+ and D- or not. - * 1: enabled - * 0: disabled + * Represents whether enable usb device exchange pins of D+ and D- or not. \\ 1: + * enabled\\ 0: disabled\\ */ uint32_t usb_device_exchg_pins:1; - uint32_t reserved_1:31; + /** usb_device_drefh : RO; bitpos: [2:1]; default: 0; + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_device_drefh:2; + /** usb_device_drefl : RO; bitpos: [4:3]; default: 0; + * Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step + * of 80 mV. + */ + uint32_t usb_device_drefl:2; + /** rd_reserve_9_197 : RW; bitpos: [16:5]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_9_197:12; + /** pvt_0_cell_select : RO; bitpos: [23:17]; default: 0; + * Power glitch monitor PVT cell select. + */ + uint32_t pvt_0_cell_select:7; + /** pvt_1_cell_select : RO; bitpos: [30:24]; default: 0; + * Power glitch monitor PVT cell select. + */ + uint32_t pvt_1_cell_select:7; + /** rd_reserve_9_223 : RW; bitpos: [31]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_9_223:1; }; uint32_t val; } efuse_rd_sys_part2_data6_reg_t; +/** Type of rd_sys_part2_data7 register + * Represents rd_sys_part2_data + */ +typedef union { + struct { + /** pvt_0_limit : RO; bitpos: [15:0]; default: 0; + * Power glitch monitor threthold. + */ + uint32_t pvt_0_limit:16; + /** pvt_1_limit : RO; bitpos: [31:16]; default: 0; + * Power glitch monitor threthold. + */ + uint32_t pvt_1_limit:16; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + /** Group: block0 error report registers */ /** Type of rd_repeat_data_err0 register @@ -850,7 +1122,10 @@ typedef union { * Represents the programming error of EFUSE_DIS_USB_JTAG */ uint32_t dis_usb_jtag_err:1; - uint32_t reserved_11:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + */ + uint32_t dis_usb_serial_jtag_err:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ @@ -879,7 +1154,11 @@ typedef union { * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT */ uint32_t dis_download_manual_encrypt_err:1; - uint32_t reserved_21:2; + uint32_t reserved_21:1; + /** dis_wifi6_err : RO; bitpos: [22]; default: 0; + * Represents the programming error of EFUSE_DIS_WIFI6 + */ + uint32_t dis_wifi6_err:1; /** huk_gen_state_err : RO; bitpos: [27:23]; default: 0; * Represents the programming error of EFUSE_HUK_GEN_STATE */ @@ -1220,98 +1499,91 @@ typedef union { typedef union { struct { /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_mac_sys */ uint32_t rd_mac_sys_err_num:3; /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. */ uint32_t rd_mac_sys_fail:1; /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part1_data */ uint32_t rd_sys_part1_data_err_num:3; /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. */ uint32_t rd_sys_part1_data_fail:1; /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_usr_data */ uint32_t rd_usr_data_err_num:3; /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. */ uint32_t rd_usr_data_fail:1; /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key0_data */ uint32_t rd_key0_data_err_num:3; /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key0_data_fail:1; /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key1_data */ uint32_t rd_key1_data_err_num:3; /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key1_data_fail:1; /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key2_data */ uint32_t rd_key2_data_err_num:3; /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key2_data_fail:1; /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key3_data */ uint32_t rd_key3_data_err_num:3; /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key3_data_fail:1; /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key4_data */ uint32_t rd_key4_data_err_num:3; /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. */ uint32_t rd_key4_data_fail:1; }; @@ -1324,15 +1596,14 @@ typedef union { typedef union { struct { /** rd_sys_part2_data_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part2_data */ uint32_t rd_sys_part2_data_err_num:3; /** rd_sys_part2_data_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. */ uint32_t rd_sys_part2_data_fail:1; uint32_t reserved_4:28; @@ -1365,28 +1636,22 @@ typedef union { typedef union { struct { /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect + * Configures whether to force power down eFuse SRAM.\\ 1: Force\\ 0: No effect\\ */ uint32_t mem_force_pd:1; /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect + * Configures whether to force activate clock signal of eFuse SRAM.\\ 1: Force + * activate\\ 0: No effect\\ */ uint32_t mem_clk_force_on:1; /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect + * Configures whether to force power up eFuse SRAM.\\ 1: Force\\ 0: No effect\\ */ uint32_t mem_force_pu:1; uint32_t reserved_3:13; /** clk_en : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers + * Configures whether to force enable eFuse register configuration clock signal.\\ 1: + * Force\\ 0: The clock is enabled only during the reading and writing of registers\\ */ uint32_t clk_en:1; uint32_t reserved_17:15; @@ -1402,10 +1667,8 @@ typedef union { typedef union { struct { /** op_code : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect + * Configures operation command type.\\ 0x5A5A: Program operation command\\ 0x5AA5: + * Read operation command\\ Other values: No effect\\ */ uint32_t op_code:16; uint32_t reserved_16:16; @@ -1434,9 +1697,8 @@ typedef union { */ uint32_t dac_num:8; /** oe_clr : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce + * Configures whether to reduce the power supply of programming voltage.\\ 0: Not + * reduce\\ 1: Reduce\\ */ uint32_t oe_clr:1; uint32_t reserved_18:14; @@ -1523,9 +1785,8 @@ typedef union { typedef union { struct { /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass + * Configures whether to bypass the Reed-Solomon (RS) correction step.\\ 0: Not + * bypass\\ 1: Bypass\\ */ uint32_t bypass_rs_correction:1; /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; @@ -1533,9 +1794,8 @@ typedef union { */ uint32_t bypass_rs_blk_num:11; /** update : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect + * Configures whether to update multi-bit register signals.\\ 1: Update\\ 0: No + * effect\\ */ uint32_t update:1; /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; @@ -1599,13 +1859,34 @@ typedef union { typedef union { struct { /** state : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state + * Represents the state of the eFuse state machine.\\ 0: Reset state, the initial + * state after power-up\\ 1: Idle state\\ Other values: Non-idle state\\ */ uint32_t state:4; - uint32_t reserved_4:6; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * Represents the value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * Represents the value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * Represents the value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * Represents the value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * Represents the value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * Represents the value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; * Represents the number of block valid bit. */ @@ -1623,15 +1904,11 @@ typedef union { typedef union { struct { /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect + * Configures whether to send read commands.\\ 1: Send\\ 0: No effect\\ */ uint32_t read_cmd:1; /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect + * Configures whether to send programming commands.\\ 1: Send\\ 0: No effect\\ */ uint32_t pgm_cmd:1; /** blk_num : R/W; bitpos: [5:2]; default: 0; @@ -1733,12 +2010,26 @@ typedef struct { volatile efuse_rd_repeat_data7_reg_t rd_repeat_data7; volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; - uint32_t reserved_058; + volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; - volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; @@ -1751,7 +2042,7 @@ typedef struct { volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; - uint32_t reserved_164; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S31.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S31.rst index 94c835a6e45..bddd303fd26 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S31.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S31.rst @@ -1,3 +1,194 @@ -.. note:: +.. code-block:: none - To be updated. + idf.py efuse-summary + + Executing action: efuse-summary + (...) + + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Config fuses: + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + RESERVED_0_39 (BLOCK0) Enable usb device exchange pins of D+ and D- = 0 R/W (0b000) + DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + EFUSE_DIS_WIFI6 (BLOCK0) USB intphy of usb device signle-end input high thr = False R/W (0b0) + eshold; 1.76V to 2V. Step by 80mV + KM_HUK_GEN_STATE (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b00000) + mode. Odd of 1 is invalid; even of 1 is valid + KM_RND_SWITCH_CYCLE (BLOCK0) Set bits to control key manager random number swit = False R/W (0b0) + ch cycle. 0: control by register. 1: 8 km clk cycl + es. 2: 16 km cycles. 3: 32 km cycles + KM_DISABLE_DEPLOY_MODE (BLOCK0) Set bits to control key manager random number swit = 0 R/W (0b00000) + ch cycle. 0: control by register. 1: 8 km clk cycl + es. 2: 16 km cycles. 3: 32 km cycles + KM_DEPLOY_ONLY_ONCE (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0b00000) + can only be deployed once. 1 is true; 0 is false. + Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds + ECC_FORCE_CONST_TIME (BLOCK0) Represents the spa secure level by configuring the = False R/W (0b0) + clock random divide mode + DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) + enabled. 1: disabled. 0: enabled + UART_PRINT_CONTROL (BLOCK0) Represents the type of UART printing. 00: force en = 0 R/W (0b00) + able printing. 01: enable printing when GPIO8 is r + eset at low level. 10: enable printing when GPIO8 + is reset at high level. 11: force disable printing + HYS_EN_PAD (BLOCK0) Represents whether the hysteresis function of = False R/W (0b0) + corresponding PAD is enabled. 1: enabled. 0:disabled + DCDC_VSET_EN (BLOCK0) Select dcdc vset use efuse_dcdc_vset = False R/W (0b0) + DIS_SWD (BLOCK0) Set this bit to disable super-watchdog = False R/W (0b0) + BOOTLOADER_ANTI_ROLLBACK_EN (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + BOOTLOADER_ANTI_ROLLBACK_UPDATE (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + RMA_ENA (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = 0 R/W (0b00) + RMA_SESSION_COUNTER (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = 0 R/W (0b000) + RMA_NONCE_ENA (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = 0 R/W (0b00) + RMA_CHIP_INFO_SOURCE (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + RMA_DISABLE_FAST_VEF (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + PVT_0_GLITCH_EN (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + PVT_0_GLITCH_MODE (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = 0 R/W (0b00) + PVT_1_GLITCH_EN (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + PVT_1_GLITCH_MODE (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = 0 R/W (0b00) + POWER_GLITCH_EN (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = 0 R/W (0x0) + XTS_SHADOW_EN (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + SPI_BOOT_CRYPT_SCRAMBLER_EN (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + PSRAM_CAP (BLOCK1) PSRAM capacity = 0 R/W (0b000) + TEMP (BLOCK1) Operating temperature of the ESP chip = 0 R/W (0b00) + PSRAM_VENDOR (BLOCK1) PSRAM vendor = 0 R/W (0b00) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK9) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TYPE (BLOCK0) The type of interfaced flash. 0: four data lines; = False R/W (0b0) + 1: eight data lines + FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) + in unit of ms. When the value less than 15; the wa + iting time is the programmed value. Otherwise; the + waiting time is 2 times the programmed value + FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) + sume command during SPI boot. 1: forced. 0:not for + ced + RECOVERY_BOOTLOADER_FLASH_SECTOR (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = 0 R/W (0x000) + PMU_FLASH_POWEL_SEL (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + PMU_FLASH_POWEL_SEL_EN (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + + Identity fuses: + BOOTLOADER_ANTI_ROLLBACK_VERSION (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = 0 R/W (0x0) + WAFER_VERSION_MINOR (BLOCK1) Minor chip version = 0 R/W (0x0) + WAFER_VERSION_MAJOR (BLOCK1) Major chip version = 0 R/W (0b00) + DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK1) Disables check of blk version major = False R/W (0b0) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) + BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Jtag fuses: + JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio15 when b + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 is enabled or disabled. 1: enabled. 0: + disabled + SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way. O = 0 R/W (0b000) + dd number: disabled. Even number: enabled + DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) + y(permanently). 1: disabled. 0: enabled + RE_ENABLE_JTAG_SOURCE (BLOCK0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0) + + Mac fuses: + MAC (BLOCK1) MAC address + = 00:00:00:00:00:00 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W + + Security fuses: + DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) + nto download mode is disabled or enabled. 1: disab + led. 0: enabled + SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Set this bit to disable accessing MSPI flash/MSPI = False R/W (0b0) + ram by SYS AXI matrix during boot_mode_download + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) + led or enabled(except in SPI boot mode). 1: disable + ed. 0: enabled + FORCE_USE_KEY_MANAGER_KEY (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0b00000) + must come from key manager.. 1 is true; 0 is false + . Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds + FORCE_DISABLE_SW_INIT_KEY (BLOCK0) Set this bit to disable software written init key; = False R/W (0b0) + and force use efuse_init_key + KM_XTS_KEY_LENGTH_256 (BLOCK0) Set this bit to configure flash encryption use xts = False R/W (0b0) + -128 key; else use xts-256 key + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0b00000) + KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0b00000) + KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0b00000) + KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0b00000) + KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0b00000) + ECDSA_ENABLE_SOFT_K (BLOCK0) Represents whether hardware random number k is for = False R/W (0b0) + ced used in ESDCA. 1: force used. 0: not force use + d + SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) + clock random divide mode + XTS_DPA_CLK_ENABLE (BLOCK0) Represents the spa secure level by configuring the = False R/W (0b0) + clock random divide mode + XTS_DPA_PSEUDO_LEVEL (BLOCK0) Represents whether anti-dpa attack is enabled. 1:e = 0 R/W (0b00) + nabled. 0: disabled + SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led. 1: enabled. 0: disabled + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) + is enabled or disabled. 1: enabled. 0: disabled + DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) + abled. 1: disabled. 0: enabled + LOCK_KM_KEY (BLOCK0) TBD = False R/W (0b0) + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) + disabled. 1: enabled. 0: disabled + SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) + ck feature + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) + or enabled when Secure Boot is enabled. 1: disable + ed. 0: enabled + SECURE_BOOT_SHA384_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led. 1: enabled. 0: disabled + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Usb fuses: + DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) + tag is disabled or enabled. 1: disabled. 0: enable + d + DIS_USB_OTG_DOWNLOAD_MODE (BLOCK0) Set this bit to disable download via USB-OTG = False R/W (0b0) + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0) + isabled or enabled. 1: disabled. 0: enabled + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) + nction is disabled or enabled. 1: disabled. 0: ena + bled + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) Represents whether RTC watchdog timeout threshold = 0 R/W (0b0) + is selected at startup. 1: selected. 0: not select + ed + DIS_WDT (BLOCK0) Set this bit to disable watch dog = False R/W (0b0) diff --git a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst index 94c835a6e45..f54f2148b60 100644 --- a/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst +++ b/docs/en/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst @@ -1,3 +1,20 @@ -.. note:: +.. code-block:: none - To be updated. + idf.py efuse-dump + + Executing action: efuse-dump + Running espefuse in directory + Executing "espefuse dump --chip esp32s31"... + espefuse v5.3.dev2 + + === Run "dump" command === + BLOCK0 ( ) [0 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + MAC_SPI_8M_0 (BLOCK1 ) [1 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_SYS_DATA (BLOCK2 ) [2 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_USR_DATA (BLOCK3 ) [3 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY0 (BLOCK4 ) [4 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY1 (BLOCK5 ) [5 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY2 (BLOCK6 ) [6 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY3 (BLOCK7 ) [7 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_KEY4 (BLOCK8 ) [8 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + BLOCK_SYS_DATA2 (BLOCK9 ) [9 ] dump: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 diff --git a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S31.rst b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S31.rst index 94c835a6e45..4f3172a0016 100644 --- a/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S31.rst +++ b/docs/en/api-reference/system/inc/show-efuse-table_ESP32-S31.rst @@ -1,3 +1,231 @@ -.. note:: +.. code-block:: none - To be updated. + $ ./efuse_table_gen.py -t {IDF_TARGET_PATH_NAME} {IDF_TARGET_PATH_NAME}/esp_efuse_table.csv --info + + Max number of bits in BLK 256 + Sorted efuse table: + # field_name efuse_block bit_start bit_count + 1 WR_DIS EFUSE_BLK0 0 32 + 2 WR_DIS.RD_DIS EFUSE_BLK0 0 1 + 3 WR_DIS.KM_RND_SWITCH_CYCLE EFUSE_BLK0 1 1 + 4 WR_DIS.KM_DISABLE_DEPLOY_MODE EFUSE_BLK0 1 1 + 5 WR_DIS.KM_DEPLOY_ONLY_ONCE EFUSE_BLK0 1 1 + 6 WR_DIS.FORCE_USE_KEY_MANAGER_KEY EFUSE_BLK0 1 1 + 7 WR_DIS.FORCE_DISABLE_SW_INIT_KEY EFUSE_BLK0 1 1 + 8 WR_DIS.KM_XTS_KEY_LENGTH_256 EFUSE_BLK0 1 1 + 9 WR_DIS.LOCK_KM_KEY EFUSE_BLK0 1 1 + 10 WR_DIS.DIS_USB_JTAG EFUSE_BLK0 2 1 + 11 WR_DIS.DIS_FORCE_DOWNLOAD EFUSE_BLK0 2 1 + 12 WR_DIS.SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 2 1 + 13 WR_DIS.DIS_TWAI EFUSE_BLK0 2 1 + 14 WR_DIS.JTAG_SEL_ENABLE EFUSE_BLK0 2 1 + 15 WR_DIS.DIS_PAD_JTAG EFUSE_BLK0 2 1 + 16 WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 2 1 + 17 WR_DIS.WDT_DELAY_SEL EFUSE_BLK0 2 1 + 18 WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 2 1 + 19 WR_DIS.DIS_WDT EFUSE_BLK0 2 1 + 20 WR_DIS.DIS_SWD EFUSE_BLK0 2 1 + 21 WR_DIS.PMU_FLASH_POWER_SEL EFUSE_BLK0 2 1 + 22 WR_DIS.PMU_FLASH_POWER_SEL_EN EFUSE_BLK0 2 1 + 23 WR_DIS.POWER_GLITCH_EN EFUSE_BLK0 2 1 + 24 WR_DIS.PVT_0_GLITCH_EN EFUSE_BLK0 3 1 + 25 WR_DIS.PVT_0_GLITCH_MODE EFUSE_BLK0 3 1 + 26 WR_DIS.PVT_1_GLITCH_EN EFUSE_BLK0 3 1 + 27 WR_DIS.PVT_1_GLITCH_MODE EFUSE_BLK0 3 1 + 28 WR_DIS.SPI_BOOT_CRYPT_CNT EFUSE_BLK0 4 1 + 29 WR_DIS.SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 5 1 + 30 WR_DIS.SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 6 1 + 31 WR_DIS.SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 7 1 + 32 WR_DIS.KEY_PURPOSE_0 EFUSE_BLK0 8 1 + 33 WR_DIS.KEY_PURPOSE_1 EFUSE_BLK0 9 1 + 34 WR_DIS.KEY_PURPOSE_2 EFUSE_BLK0 10 1 + 35 WR_DIS.KEY_PURPOSE_3 EFUSE_BLK0 11 1 + 36 WR_DIS.KEY_PURPOSE_4 EFUSE_BLK0 12 1 + 37 WR_DIS.DIS_SM_CRYPT EFUSE_BLK0 14 1 + 38 WR_DIS.ECC_FORCE_CONST_TIME EFUSE_BLK0 14 1 + 39 WR_DIS.ECDSA_DISABLE_SOFT_K EFUSE_BLK0 14 1 + 40 WR_DIS.SEC_DPA_LEVEL EFUSE_BLK0 14 1 + 41 WR_DIS.XTS_DPA_CLK_ENABLE EFUSE_BLK0 14 1 + 42 WR_DIS.XTS_DPA_PSEUDO_LEVEL EFUSE_BLK0 14 1 + 43 WR_DIS.RMA_NONCE_ENA EFUSE_BLK0 14 1 + 44 WR_DIS.RMA_CHIP_INFO_SOURCE EFUSE_BLK0 14 1 + 45 WR_DIS.RMA_DISABLE_FAST_VEF EFUSE_BLK0 14 1 + 46 WR_DIS.ENA_XTS_SHADOW EFUSE_BLK0 14 1 + 47 WR_DIS.ENA_SPI_BOOT_CRYPT_SCRAMBLER EFUSE_BLK0 14 1 + 48 WR_DIS.RE_ENABLE_JTAG_SOURCE EFUSE_BLK0 14 1 + 49 WR_DIS.SECURE_BOOT_EN EFUSE_BLK0 15 1 + 50 WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 16 1 + 51 WR_DIS.FLASH_TYPE EFUSE_BLK0 18 1 + 52 WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 53 WR_DIS.FLASH_TPUW EFUSE_BLK0 18 1 + 54 WR_DIS.DIS_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 55 WR_DIS.DIS_DIRECT_BOOT EFUSE_BLK0 18 1 + 56 WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 18 1 + 57 WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 18 1 + 58 WR_DIS.ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 18 1 + 59 WR_DIS.UART_PRINT_CONTROL EFUSE_BLK0 18 1 + 60 WR_DIS.FORCE_SEND_RESUME EFUSE_BLK0 18 1 + 61 WR_DIS.SECURE_VERSION EFUSE_BLK0 18 1 + 62 WR_DIS.HUK_GEN_STATE EFUSE_BLK0 19 1 + 63 WR_DIS.BLK1 EFUSE_BLK0 20 1 + 64 WR_DIS.MAC EFUSE_BLK0 20 1 + 65 WR_DIS.MAC_EXT EFUSE_BLK0 20 1 + 66 WR_DIS.WAFER_VERSION_MINOR EFUSE_BLK0 20 1 + 67 WR_DIS.WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 68 WR_DIS.DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK0 20 1 + 69 WR_DIS.DISABLE_BLK_VERSION_MAJOR EFUSE_BLK0 20 1 + 70 WR_DIS.BLK_VERSION_MINOR EFUSE_BLK0 20 1 + 71 WR_DIS.BLK_VERSION_MAJOR EFUSE_BLK0 20 1 + 72 WR_DIS.PSRAM_CAP EFUSE_BLK0 20 1 + 73 WR_DIS.TEMP EFUSE_BLK0 20 1 + 74 WR_DIS.PSRAM_VENDOR EFUSE_BLK0 20 1 + 75 WR_DIS.PKG_VERSION EFUSE_BLK0 20 1 + 76 WR_DIS.SYS_DATA_PART1 EFUSE_BLK0 21 1 + 77 WR_DIS.OPTIONAL_UNIQUE_ID EFUSE_BLK0 21 1 + 78 WR_DIS.BLOCK_USR_DATA EFUSE_BLK0 22 1 + 79 WR_DIS.CUSTOM_MAC EFUSE_BLK0 22 1 + 80 WR_DIS.BLOCK_KEY0 EFUSE_BLK0 23 1 + 81 WR_DIS.BLOCK_KEY1 EFUSE_BLK0 24 1 + 82 WR_DIS.BLOCK_KEY2 EFUSE_BLK0 25 1 + 83 WR_DIS.BLOCK_KEY3 EFUSE_BLK0 26 1 + 84 WR_DIS.BLOCK_KEY4 EFUSE_BLK0 27 1 + 85 WR_DIS.BLOCK_SYS_DATA2 EFUSE_BLK0 28 1 + 86 WR_DIS.USB_DEVICE_EXCHG_PINS EFUSE_BLK0 28 1 + 87 WR_DIS.SOFT_DIS_JTAG EFUSE_BLK0 31 1 + 88 RD_DIS EFUSE_BLK0 32 7 + 89 RD_DIS.BLOCK_KEY0 EFUSE_BLK0 32 1 + 90 RD_DIS.BLOCK_KEY1 EFUSE_BLK0 33 1 + 91 RD_DIS.BLOCK_KEY2 EFUSE_BLK0 34 1 + 92 RD_DIS.BLOCK_KEY3 EFUSE_BLK0 35 1 + 93 RD_DIS.BLOCK_KEY4 EFUSE_BLK0 36 1 + 94 DIS_USB_JTAG EFUSE_BLK0 42 1 + 95 DIS_FORCE_DOWNLOAD EFUSE_BLK0 44 1 + 96 SPI_DOWNLOAD_MSPI_DIS EFUSE_BLK0 45 1 + 97 DIS_TWAI EFUSE_BLK0 46 1 + 98 JTAG_SEL_ENABLE EFUSE_BLK0 47 1 + 99 SOFT_DIS_JTAG EFUSE_BLK0 48 3 + 100 DIS_PAD_JTAG EFUSE_BLK0 51 1 + 101 DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_BLK0 52 1 + 102 HUK_GEN_STATE EFUSE_BLK0 55 5 + 103 KM_RND_SWITCH_CYCLE EFUSE_BLK0 64 1 + 104 KM_DISABLE_DEPLOY_MODE EFUSE_BLK0 66 5 + 105 KM_DEPLOY_ONLY_ONCE EFUSE_BLK0 71 5 + 106 FORCE_USE_KEY_MANAGER_KEY EFUSE_BLK0 76 5 + 107 FORCE_DISABLE_SW_INIT_KEY EFUSE_BLK0 81 1 + 108 KM_XTS_KEY_LENGTH_256 EFUSE_BLK0 82 1 + 109 WDT_DELAY_SEL EFUSE_BLK0 83 1 + 110 DIS_SM_CRYPT EFUSE_BLK0 84 1 + 111 SPI_BOOT_CRYPT_CNT EFUSE_BLK0 85 3 + 112 SECURE_BOOT_KEY_REVOKE0 EFUSE_BLK0 88 1 + 113 SECURE_BOOT_KEY_REVOKE1 EFUSE_BLK0 89 1 + 114 SECURE_BOOT_KEY_REVOKE2 EFUSE_BLK0 90 1 + 115 KEY_PURPOSE_0 EFUSE_BLK0 96 5 + 116 KEY_PURPOSE_1 EFUSE_BLK0 101 5 + 117 KEY_PURPOSE_2 EFUSE_BLK0 106 5 + 118 KEY_PURPOSE_3 EFUSE_BLK0 111 5 + 119 KEY_PURPOSE_4 EFUSE_BLK0 116 5 + 120 ECC_FORCE_CONST_TIME EFUSE_BLK0 121 1 + 121 ECDSA_DISABLE_SOFT_K EFUSE_BLK0 122 1 + 122 SEC_DPA_LEVEL EFUSE_BLK0 123 2 + 123 XTS_DPA_CLK_ENABLE EFUSE_BLK0 125 1 + 124 XTS_DPA_PSEUDO_LEVEL EFUSE_BLK0 128 2 + 125 SECURE_BOOT_EN EFUSE_BLK0 130 1 + 126 SECURE_BOOT_AGGRESSIVE_REVOKE EFUSE_BLK0 131 1 + 127 FLASH_TYPE EFUSE_BLK0 133 1 + 128 DIS_USB_OTG_DOWNLOAD_MODE EFUSE_BLK0 137 1 + 129 FLASH_TPUW EFUSE_BLK0 140 4 + 130 DIS_DOWNLOAD_MODE EFUSE_BLK0 144 1 + 131 DIS_DIRECT_BOOT EFUSE_BLK0 145 1 + 132 DIS_USB_SERIAL_JTAG_ROM_PRINT EFUSE_BLK0 146 1 + 133 LOCK_KM_KEY EFUSE_BLK0 147 1 + 134 DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE EFUSE_BLK0 148 1 + 135 ENABLE_SECURITY_DOWNLOAD EFUSE_BLK0 149 1 + 136 UART_PRINT_CONTROL EFUSE_BLK0 150 2 + 137 FORCE_SEND_RESUME EFUSE_BLK0 152 1 + 138 SECURE_VERSION EFUSE_BLK0 160 16 + 139 SECURE_BOOT_DISABLE_FAST_WAKE EFUSE_BLK0 176 1 + 140 HYS_EN_PAD EFUSE_BLK0 177 1 + 141 DCDC_VSET_EN EFUSE_BLK0 194 1 + 142 DIS_WDT EFUSE_BLK0 195 1 + 143 DIS_SWD EFUSE_BLK0 196 1 + 144 SECURE_BOOT_SHA384_EN EFUSE_BLK0 203 1 + 145 BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION EFUSE_BLK0 204 4 + 146 BOOTLOADER_ANTI_ROLLBACK_EN EFUSE_BLK0 208 1 + 147 BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM EFUSE_BLK0 209 1 + 148 RECOVERY_BOOTLOADER_FLASH_SECTOR EFUSE_BLK0 210 12 + 149 RMA_ENA EFUSE_BLK0 222 2 + 150 RMA_SESSION_COUNTER EFUSE_BLK0 224 3 + 151 RMA_NONCE_ENA EFUSE_BLK0 227 2 + 152 RMA_CHIP_INFO_SOURCE EFUSE_BLK0 229 1 + 153 RMA_DISABLE_FAST_VEF EFUSE_BLK0 230 1 + 154 PVT_0_GLITCH_EN EFUSE_BLK0 231 1 + 155 PVT_0_GLITCH_MODE EFUSE_BLK0 232 2 + 156 PVT_1_GLITCH_EN EFUSE_BLK0 234 1 + 157 PVT_1_GLITCH_MODE EFUSE_BLK0 235 2 + 158 PMU_FLASH_POWER_SEL EFUSE_BLK0 237 1 + 159 PMU_FLASH_POWER_SEL_EN EFUSE_BLK0 238 1 + 160 POWER_GLITCH_EN EFUSE_BLK0 239 4 + 161 ENA_XTS_SHADOW EFUSE_BLK0 243 1 + 162 ENA_SPI_BOOT_CRYPT_SCRAMBLER EFUSE_BLK0 244 1 + 163 RE_ENABLE_JTAG_SOURCE EFUSE_BLK0 245 1 + 164 MAC EFUSE_BLK1 0 8 + 165 MAC EFUSE_BLK1 8 8 + 166 MAC EFUSE_BLK1 16 8 + 167 MAC EFUSE_BLK1 24 8 + 168 MAC EFUSE_BLK1 32 8 + 169 MAC EFUSE_BLK1 40 8 + 170 MAC_EXT EFUSE_BLK1 48 8 + 171 MAC_EXT EFUSE_BLK1 56 8 + 172 WAFER_VERSION_MINOR EFUSE_BLK1 114 4 + 173 WAFER_VERSION_MAJOR EFUSE_BLK1 118 2 + 174 DISABLE_WAFER_VERSION_MAJOR EFUSE_BLK1 120 1 + 175 DISABLE_BLK_VERSION_MAJOR EFUSE_BLK1 121 1 + 176 BLK_VERSION_MINOR EFUSE_BLK1 122 3 + 177 BLK_VERSION_MAJOR EFUSE_BLK1 125 2 + 178 PSRAM_CAP EFUSE_BLK1 127 3 + 179 TEMP EFUSE_BLK1 130 2 + 180 PSRAM_VENDOR EFUSE_BLK1 132 2 + 181 PKG_VERSION EFUSE_BLK1 134 2 + 182 OPTIONAL_UNIQUE_ID EFUSE_BLK2 0 128 + 183 USER_DATA EFUSE_BLK3 0 256 + 184 USER_DATA.MAC_CUSTOM EFUSE_BLK3 200 48 + 185 KEY0 EFUSE_BLK4 0 256 + 186 KEY1 EFUSE_BLK5 0 256 + 187 KEY2 EFUSE_BLK6 0 256 + 188 KEY3 EFUSE_BLK7 0 256 + 189 KEY4 EFUSE_BLK8 0 256 + 190 SYS_DATA_PART2 EFUSE_BLK9 0 32 + 191 USB_DEVICE_EXCHG_PINS EFUSE_BLK9 192 1 + + Used bits in efuse table: + EFUSE_BLK0 + [0 31] [0 1] [1 1] [1 1] ... [140 152] [160 177] [194 196] [203 245] + + EFUSE_BLK1 + [0 63] [114 135] + + EFUSE_BLK2 + [0 127] + + EFUSE_BLK3 + [0 255] [200 247] + + EFUSE_BLK4 + [0 255] + + EFUSE_BLK5 + [0 255] + + EFUSE_BLK6 + [0 255] + + EFUSE_BLK7 + [0 255] + + EFUSE_BLK8 + [0 255] + + EFUSE_BLK9 + [0 31] [192 192] + + Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif) diff --git a/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-S31.rst b/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-S31.rst index 94c835a6e45..18ba1cccdf7 100644 --- a/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-S31.rst +++ b/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-S31.rst @@ -1,3 +1,2 @@ -.. note:: - - To be updated. +.. Translation not required: source file contains only code. +.. include:: ../../../en/api-reference/system/inc/espefuse_summary_ESP32-S31.rst diff --git a/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst b/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst index 94c835a6e45..ce5fcfcf8c8 100644 --- a/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst +++ b/docs/zh_CN/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst @@ -1,3 +1,2 @@ -.. note:: - - To be updated. +.. Translation not required: source file contains only code. +.. include:: ../../../en/api-reference/system/inc/espefuse_summary_ESP32-S31_dump.rst diff --git a/docs/zh_CN/api-reference/system/inc/show-efuse-table_ESP32-S31.rst b/docs/zh_CN/api-reference/system/inc/show-efuse-table_ESP32-S31.rst index 94c835a6e45..2c12a64f37e 100644 --- a/docs/zh_CN/api-reference/system/inc/show-efuse-table_ESP32-S31.rst +++ b/docs/zh_CN/api-reference/system/inc/show-efuse-table_ESP32-S31.rst @@ -1,3 +1,2 @@ -.. note:: - - To be updated. +.. Translation not required: source file contains only code. +.. include:: ../../../en/api-reference/system/inc/show-efuse-table_ESP32-S31.rst diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index beacae08dc9..d0e91a1fe19 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -45,7 +45,7 @@ examples/system/efuse: reason: Secure Boot V2 with ECDSA P384 is not supported. - if: IDF_TARGET in ["esp32s31"] temporary: true - reason: not support yet # TODO: [ESP32S31] IDF-14688 + reason: not support yet # TODO: [ESP32S31] IDF-14442 depends_components: - *common_components - efuse