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docs(esp_system): add detailed RTC memory layout documentation

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wuzhenghui
2026-01-09 11:15:15 +08:00
parent 9a20ef85f5
commit c17787722c
9 changed files with 369 additions and 1 deletions
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components/esp_system/ld/esp32c6/memory.ld.in
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@@ -78,6 +78,41 @@ MEMORY
/* (See irom_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* LP RAM (RTC Memory) Layout for ESP32-C6
* Total Size: 16KB (0x4000)
* Address Range: 0x50000000 - 0x50004000
*
* The LP RAM persists over deep sleep and is used for:
* - ULP coprocessor code and data (optional)
* - RTC wake stub code and data
* - Data that needs to survive deep sleep
* - Bootloader retain memory (for reboot counter, OTA info, etc.)
*
* +-----------------------------+ 0x50004000 (LP RAM end)
* | Secure Boot Image Digest |
* | for fast wake secure boot. | ( For ROM using, must keep it at the end 32 bytes of LP RAM)
* |(only if CONFIG_SECURE_BOOT) |
* |- - - - - - - - - - - - - - -|
* | bootloader_data_rtc_mem |
* | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM)
* |- - - - - - - - - - - - - - -|
* | rtc_timer_data_in_rtc_mem |
* | (RTC_TIMER_RESERVE_RTC=24B) |
* +-----------------------------+ 0x50004000 - RESERVE_RTC_MEM
* | .rtc.force_slow |
* | .rtc_noinit (NOLOAD) |
* | .rtc.bss (NOLOAD) |
* | .rtc.data | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg)
* | .rtc.force_fast |
* |- - - - - - - - - - - - - - -|
* | .rtc.text | RTC wake stub code
* +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled)
* | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM)
* | (code + data) |
* +-----------------------------+ 0x50000000 (LP RAM start)
*/
/**
* lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
*/