From c17787722c6d416f34336c4f124d983622c42d0a Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 8 Dec 2025 17:10:07 +0800 Subject: [PATCH] docs(esp_system): add detailed RTC memory layout documentation --- components/esp_system/ld/esp32/memory.ld.in | 54 ++++++++++++++++++ components/esp_system/ld/esp32c3/memory.ld.in | 32 ++++++++++- components/esp_system/ld/esp32c5/memory.ld.in | 36 ++++++++++++ components/esp_system/ld/esp32c6/memory.ld.in | 35 ++++++++++++ components/esp_system/ld/esp32h2/memory.ld.in | 32 +++++++++++ .../esp_system/ld/esp32h21/memory.ld.in | 31 ++++++++++ components/esp_system/ld/esp32p4/memory.ld.in | 39 +++++++++++++ components/esp_system/ld/esp32s2/memory.ld.in | 56 +++++++++++++++++++ components/esp_system/ld/esp32s3/memory.ld.in | 55 ++++++++++++++++++ 9 files changed, 369 insertions(+), 1 deletion(-) diff --git a/components/esp_system/ld/esp32/memory.ld.in b/components/esp_system/ld/esp32/memory.ld.in index df13722b0ce..a498654feef 100644 --- a/components/esp_system/ld/esp32/memory.ld.in +++ b/components/esp_system/ld/esp32/memory.ld.in @@ -88,6 +88,60 @@ MEMORY /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/** + * RTC Memory Layout for ESP32 + * + * ESP32 has two separate RTC memory regions: + * 1. RTC FAST Memory: 8KB, accessible by PRO_CPU only + * 2. RTC SLOW Memory: 8KB, accessible by both CPUs and ULP coprocessor + * + * ==================== RTC FAST Memory ==================== + * Size: 8KB (0x2000) + * IRAM View: 0x400C0000 - 0x400C2000 (executable) + * DRAM View: 0x3FF80000 - 0x3FF82000 (data access) + * + * +-----------------------------+ 0x400C2000 / 0x3FF82000 (RTC FAST memory end) + * | rtc_fast_reserved_seg | + * | (ESP_BOOTLOADER_RESERVE_RTC)| + * |- - - - - - - - - - - - - - -| + * | bootloader_data_rtc_mem | s_bootloader_retain_mem + * +-----------------------------+ 0x400C2000 - ESP_BOOTLOADER_RESERVE_RTC + * | rtc_iram_seg / | + * | rtc_data_seg | + * | .rtc.text | RTC wake stub code + * |- - - - - - - - - - - - - - -| + * | .rtc.data / .rtc.rodata | (when CONFIG_ESP32_RTCDATA_IN_FAST_MEM) + * |- - - - - - - - - - - - - - -| + * | .rtc.bss | + * +-----------------------------+ 0x400C0000 / 0x3FF80000 (RTC FAST memory start) + * + * ==================== RTC SLOW Memory ==================== + * Size: 8KB (0x2000) + * Address: 0x50000000 - 0x50002000 + * + * +-----------------------------+ 0x50002000 (RTC SLOW memory end) + * | rtc_slow_reserved_seg | + * | (RESERVE_RTC_MEM = 24) | + * |- - - - - - - - - - - - - - -| + * | rtc_timer_data_in_rtc_mem | s_rtc_timer_retain_mem (24 bytes) + * | (RTC_TIMER_RESERVE_RTC) | + * +-----------------------------+ 0x50002000 - RESERVE_RTC_MEM + * | rtc_slow_seg | + * |- - - - - - - - - - - - - - -| + * | .rtc.data / .rtc.rodata | (when !CONFIG_ESP32_RTCDATA_IN_FAST_MEM) + * | .rtc.bss | + * +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled) + * | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM) + * | (code + data) | + * +-----------------------------+ 0x50000000 (RTC SLOW memory start) + * + * ESP_BOOTLOADER_RESERVE_RTC = ALIGN_UP(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE, 8) + * RESERVE_RTC_MEM = RTC_TIMER_RESERVE_RTC (24 bytes) for ESP32 + * + * Note: RTC data can be placed in either FAST or SLOW memory based on + * CONFIG_ESP32_RTCDATA_IN_FAST_MEM configuration option. + */ + /* RTC fast memory (executable). Persists over deep sleep. */ rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC diff --git a/components/esp_system/ld/esp32c3/memory.ld.in b/components/esp_system/ld/esp32c3/memory.ld.in index 4c623138331..930a3df6a6d 100644 --- a/components/esp_system/ld/esp32c3/memory.ld.in +++ b/components/esp_system/ld/esp32c3/memory.ld.in @@ -16,7 +16,7 @@ #include "ld.common" /** - * physical memory is mapped twice to the vritual address (IRAM and DRAM). + * physical memory is mapped twice to the virtual address (IRAM and DRAM). * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory */ #define SRAM_IRAM_START 0x4037C000 @@ -69,6 +69,36 @@ MEMORY /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/** + * RTC Memory (LP RAM) Layout for ESP32-C3 + * Total Size: 8KB (0x2000) + * Address Range: 0x50000000 - 0x50002000 + * + * ESP32-C3 has only unified RTC FAST memory (no separate RTC SLOW). + * The LP RAM persists over deep sleep and is used for: + * - RTC wake stub code and data + * - Data that needs to survive deep sleep + * - Bootloader retain memory (for reboot counter, OTA info, etc.) + * + * +-----------------------------+ 0x50002000 (RTC memory end) + * | bootloader_data_rtc_mem | + * | (ESP_BOOTLOADER_RESERVE_RTC)| + * |- - - - - - - - - - - - - - -| rtc_reserved_seg (RESERVE_RTC_MEM) + * | rtc_timer_data_in_rtc_mem | + * | (RTC_TIMER_RESERVE_RTC=24B) | + * +-----------------------------+ 0x50002000 - RESERVE_RTC_MEM + * | .rtc.force_slow | + * | .rtc_noinit (NOLOAD) | + * | .rtc.bss (NOLOAD) | + * | .rtc.data | rtc_iram_seg (= rtc_data_seg = rtc_slow_seg) + * | .rtc.force_fast | + * |- - - - - - - - - - - - - - -| + * | .rtc.text | RTC wake stub code + * +-----------------------------+ 0x50000000 (RTC memory start) + * + * RESERVE_RTC_MEM = RTC_TIMER_RESERVE_RTC (24B) + ESP_BOOTLOADER_RESERVE_RTC + */ + /** * RTC fast memory (executable). Persists over deep sleep. */ diff --git a/components/esp_system/ld/esp32c5/memory.ld.in b/components/esp_system/ld/esp32c5/memory.ld.in index 160b3232a4f..3a518972943 100644 --- a/components/esp_system/ld/esp32c5/memory.ld.in +++ b/components/esp_system/ld/esp32c5/memory.ld.in @@ -76,6 +76,42 @@ MEMORY /* (See irom_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/** + * LP RAM (RTC Memory) Layout for ESP32-C5 + * Total Size: 16KB (0x4000) + * Address Range: 0x50000000 - 0x50004000 + * + * ESP32-C5 has only unified LP RAM (no separate RTC FAST/SLOW). + * The LP RAM persists over deep sleep and is used for: + * - ULP coprocessor code and data (optional) + * - RTC wake stub code and data + * - Data that needs to survive deep sleep + * - Bootloader retain memory (for reboot counter, OTA info, etc.) + * + * +-----------------------------+ 0x50004000 (LP RAM end) + * | Secure Boot Image Digest | ( For ROM using, must keep it at the end ESP_SECURE_BOOT_DIGEST_LEN bytes of LP RAM) + * | for fast wake secure boot. | + * |(only if CONFIG_SECURE_BOOT) | + * |- - - - - - - - - - - - - - -| + * | bootloader_data_rtc_mem | + * | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM) + * |- - - - - - - - - - - - - - -| + * | rtc_timer_data_in_rtc_mem | + * | (RTC_TIMER_RESERVE_RTC=24B) | + * +-----------------------------+ 0x50004000 - RESERVE_RTC_MEM + * | .rtc.force_slow | + * | .rtc_noinit (NOLOAD) | + * | .rtc.bss (NOLOAD) | + * | .rtc.data | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg) + * | .rtc.force_fast | + * |- - - - - - - - - - - - - - -| + * | .rtc.text | RTC wake stub code + * +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled) + * | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM) + * | (code + data) | + * +-----------------------------+ 0x50000000 (LP RAM start) + */ + /** * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 */ diff --git a/components/esp_system/ld/esp32c6/memory.ld.in b/components/esp_system/ld/esp32c6/memory.ld.in index 4345cd201fe..9ca127b96d3 100644 --- a/components/esp_system/ld/esp32c6/memory.ld.in +++ b/components/esp_system/ld/esp32c6/memory.ld.in @@ -78,6 +78,41 @@ MEMORY /* (See irom_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/** + * LP RAM (RTC Memory) Layout for ESP32-C6 + * Total Size: 16KB (0x4000) + * Address Range: 0x50000000 - 0x50004000 + * + * The LP RAM persists over deep sleep and is used for: + * - ULP coprocessor code and data (optional) + * - RTC wake stub code and data + * - Data that needs to survive deep sleep + * - Bootloader retain memory (for reboot counter, OTA info, etc.) + * + * +-----------------------------+ 0x50004000 (LP RAM end) + * | Secure Boot Image Digest | + * | for fast wake secure boot. | ( For ROM using, must keep it at the end 32 bytes of LP RAM) + * |(only if CONFIG_SECURE_BOOT) | + * |- - - - - - - - - - - - - - -| + * | bootloader_data_rtc_mem | + * | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM) + * |- - - - - - - - - - - - - - -| + * | rtc_timer_data_in_rtc_mem | + * | (RTC_TIMER_RESERVE_RTC=24B) | + * +-----------------------------+ 0x50004000 - RESERVE_RTC_MEM + * | .rtc.force_slow | + * | .rtc_noinit (NOLOAD) | + * | .rtc.bss (NOLOAD) | + * | .rtc.data | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg) + * | .rtc.force_fast | + * |- - - - - - - - - - - - - - -| + * | .rtc.text | RTC wake stub code + * +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled) + * | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM) + * | (code + data) | + * +-----------------------------+ 0x50000000 (LP RAM start) + */ + /** * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 */ diff --git a/components/esp_system/ld/esp32h2/memory.ld.in b/components/esp_system/ld/esp32h2/memory.ld.in index ba1e5d9960e..6ca92701697 100644 --- a/components/esp_system/ld/esp32h2/memory.ld.in +++ b/components/esp_system/ld/esp32h2/memory.ld.in @@ -78,6 +78,38 @@ MEMORY /* (See irom_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/** + * LP RAM (RTC Memory) Layout for ESP32-H2 + * Total Size: 4KB (0x1000) + * Address Range: 0x50000000 - 0x50001000 + * + * ESP32-H2 has only unified LP RAM (no separate RTC FAST/SLOW). + * The LP RAM persists over deep sleep and is used for: + * - RTC wake stub code and data + * - Data that needs to survive deep sleep + * - Bootloader retain memory (for reboot counter, OTA info, etc.) + * + * +-----------------------------+ 0x50001000 (LP RAM end) + * | Secure Boot Image Digest | + * | for fast wake secure boot. | ( For ROM using, must keep it at the end 32 bytes of LP RAM) + * |(only if CONFIG_SECURE_BOOT) | + * |- - - - - - - - - - - - - - -| + * | bootloader_data_rtc_mem | + * | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM) + * |- - - - - - - - - - - - - - -| + * | rtc_timer_data_in_rtc_mem | + * | (RTC_TIMER_RESERVE_RTC=24B) | + * +-----------------------------+ 0x50001000 - RESERVE_RTC_MEM + * | .rtc.force_slow | + * | .rtc_noinit (NOLOAD) | + * | .rtc.bss (NOLOAD) | + * | .rtc.data | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg) + * | .rtc.force_fast | + * |- - - - - - - - - - - - - - -| + * | .rtc.text | RTC wake stub code + * +-----------------------------+ 0x50000000 (LP RAM start) + */ + /** * lp ram memory (RWX). Persists over deep sleep. */ diff --git a/components/esp_system/ld/esp32h21/memory.ld.in b/components/esp_system/ld/esp32h21/memory.ld.in index e8d8e8c2ce7..ba0c0866fa1 100644 --- a/components/esp_system/ld/esp32h21/memory.ld.in +++ b/components/esp_system/ld/esp32h21/memory.ld.in @@ -61,6 +61,37 @@ MEMORY /* (See irom_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/** + * LP RAM (RTC Memory) Layout for ESP32-H21 + * Total Size: 4KB (0x1000) + * Address Range: 0x50000000 - 0x50001000 + * + * ESP32-H21 has only unified LP RAM (no separate RTC FAST/SLOW). + * The LP RAM persists over deep sleep and is used for: + * - RTC wake stub code and data + * - Data that needs to survive deep sleep + * - Bootloader retain memory (for reboot counter, OTA info, etc.) + * + * +-----------------------------+ 0x50001000 (LP RAM end) + * | Secure Boot Image Digest | + * | for fast wake secure boot. | ( For ROM using, must keep it at the end 32 bytes of LP RAM) + * |(only if CONFIG_SECURE_BOOT) | + * |- - - - - - - - - - - - - - -| + * | bootloader_data_rtc_mem | + * | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM) + * |- - - - - - - - - - - - - - -| + * | rtc_timer_data_in_rtc_mem | + * | (RTC_TIMER_RESERVE_RTC=24B) | + * +-----------------------------+ 0x50001000 - RESERVE_RTC_MEM + * | .rtc.force_slow | + * | .rtc_noinit (NOLOAD) | + * | .rtc.bss (NOLOAD) | + * | .rtc.data | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg) + * | .rtc.force_fast | + * |- - - - - - - - - - - - - - -| + * | .rtc.text | RTC wake stub code + * +-----------------------------+ 0x50000000 (LP RAM start) + */ /** * lp ram memory (RWX). Persists over deep sleep. */ diff --git a/components/esp_system/ld/esp32p4/memory.ld.in b/components/esp_system/ld/esp32p4/memory.ld.in index 37b5f0f8f1f..698d6dac409 100644 --- a/components/esp_system/ld/esp32p4/memory.ld.in +++ b/components/esp_system/ld/esp32p4/memory.ld.in @@ -93,6 +93,45 @@ MEMORY /* Used to store the deep sleep workaround code of P4 rev3.0. The reset vector will be set here before the chip enters sleep. */ rev3_mspi_workaround_seg(RWX) : org = 0x50108000, len = MSPI_WORKAROUND_SIZE + +/** + * LP RAM (RTC Memory) Layout for ESP32-P4 + * Total Size: 32KB (0x8000) + * Address Range: 0x50108000 - 0x50110000 + * + * ESP32-P4 has LP ROM, and LP RAM layout is different from other chips. + * The reserved segments are placed at the BEGINNING of LP RAM (low address), + * because the END of LP RAM is occupied by LP ROM stack/data. + * + * +-----------------------------+ 0x50110000 (LP RAM end) + * | LP ROM Reserved | LP ROM bss/data/stack (reserved by ROM) + * | (LP_ROM_DRAM_SIZE) | ~1.4KB from 0x5010FA80 + * +-----------------------------+ (LP_ROM_DRAM_START, see soc.h) + * | .rtc.force_slow | + * | .rtc_noinit (NOLOAD) | + * | .rtc.bss (NOLOAD) | + * | .rtc.data | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg) + * | .rtc.force_fast | + * |- - - - - - - - - - - - - - -| + * | .rtc.text | RTC wake stub code + * +-----------------------------+ lp_ram_seg start (after reserved areas) + * | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM) + * | (code + data) | + * +-----------------------------+ 0x50108000 + MSPI_WORKAROUND_SIZE + RESERVE_RTC_MEM + * | bootloader_data_rtc_mem | + * | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM) + * |- - - - - - - - - - - - - - -| + * | rtc_timer_data_in_rtc_mem | + * | (RTC_TIMER_RESERVE_RTC=24B) | + * +-----------------------------+ 0x50108000 + MSPI_WORKAROUND_SIZE + * | rev3_mspi_workaround_seg | Deep sleep workaround code for P4 rev3.0 + * | (MSPI_WORKAROUND_SIZE) | Reset vector set here before sleep + * +-----------------------------+ 0x50108000 (LP RAM start) + * + * Note: ESP32-P4's reserved segments are at LOW address (beginning of LP RAM), + * unlike other chips where they are at HIGH address (end of LP RAM). + * This is because LP ROM uses the end of LP RAM for its stack/data. + */ /** * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 */ diff --git a/components/esp_system/ld/esp32s2/memory.ld.in b/components/esp_system/ld/esp32s2/memory.ld.in index 82fa95625c6..ca7c4d6d932 100644 --- a/components/esp_system/ld/esp32s2/memory.ld.in +++ b/components/esp_system/ld/esp32s2/memory.ld.in @@ -12,6 +12,7 @@ Please use preprocessor features sparingly! Restrict to simple macros with numeric values, and/or #if/#endif blocks. */ + #include "sdkconfig.h" #include "ld.common" @@ -68,6 +69,61 @@ MEMORY /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/** + * RTC Memory Layout for ESP32-S2 + * + * ESP32-S2 has two separate RTC memory regions: + * 1. RTC FAST Memory: 8KB, used for RTC code and data + * 2. RTC SLOW Memory: 8KB, used for ULP coprocessor + * + * ==================== RTC FAST Memory ==================== + * Size: 8KB (0x2000) + * IRAM View: 0x40070000 - 0x40072000 (executable) + * DRAM View: 0x3FF9E000 - 0x3FFA0000 (data access) + * + * +-----------------------------+ 0x40072000 / 0x3FFA0000 (RTC FAST memory end) + * | rtc_reserved_seg | + * | (RESERVE_RTC_MEM) | + * |- - - - - - - - - - - - - - -| + * | bootloader_data_rtc_mem | s_bootloader_retain_mem + * | (ESP_BOOTLOADER_RESERVE_RTC)| + * |- - - - - - - - - - - - - - -| + * | rtc_timer_data_in_rtc_mem | s_rtc_timer_retain_mem (24 bytes) + * | (RTC_TIMER_RESERVE_RTC) | + * +-----------------------------+ 0x40072000 - RESERVE_RTC_MEM + * | rtc_iram_seg / | + * | rtc_data_seg | + * |- - - - - - - - - - - - - - -| + * | .rtc.text | RTC wake stub code + * |- - - - - - - - - - - - - - -| + * | .rtc.data / .rtc.rodata | (when CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM) + * |- - - - - - - - - - - - - - -| + * | .rtc.bss | + * +-----------------------------+ 0x40070000 / 0x3FF9E000 (RTC FAST memory start) + * + * ==================== RTC SLOW Memory ==================== + * Size: 8KB (0x2000) + * Address: 0x50000000 - 0x50002000 + * + * +-----------------------------+ 0x50002000 (RTC SLOW memory end) + * | rtc_slow_seg | + * |- - - - - - - - - - - - - - -| + * | .rtc.data / .rtc.rodata | (when !CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM) + * |- - - - - - - - - - - - - - -| + * | .rtc.bss | + * +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled) + * | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM) + * | (code + data) | + * +-----------------------------+ 0x50000000 (RTC SLOW memory start) + * + * RESERVE_RTC_MEM calculation: + * - RTC_TIMER_RESERVE_RTC = 24 bytes + * - ESP_BOOTLOADER_RESERVE_RTC = ALIGN_UP(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE, 8) + * + * Note: RTC data can be placed in either FAST or SLOW memory based on + * CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM configuration option. + */ + /* RTC fast memory (executable). Persists over deep sleep. */ rtc_iram_seg(RWX) : org = 0x40070000, len = 0x2000 - RESERVE_RTC_MEM diff --git a/components/esp_system/ld/esp32s3/memory.ld.in b/components/esp_system/ld/esp32s3/memory.ld.in index 5055aaf7f7f..87103fff8d9 100644 --- a/components/esp_system/ld/esp32s3/memory.ld.in +++ b/components/esp_system/ld/esp32s3/memory.ld.in @@ -87,6 +87,61 @@ MEMORY /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS +/** + * RTC Memory Layout for ESP32-S3 + * + * ESP32-S3 has two separate RTC memory regions: + * 1. RTC FAST Memory: 8KB, used for RTC code and data + * 2. RTC SLOW Memory: 8KB, used for ULP coprocessor + * + * ==================== RTC FAST Memory ==================== + * Size: 8KB (0x2000) + * Address: 0x600FE000 - 0x60100000 (data and instruction access on same bus) + * + * +-----------------------------+ 0x60100000 (RTC FAST memory end) + * | rtc_reserved_seg | + * | (RESERVE_RTC_MEM) | + * |- - - - - - - - - - - - - - -| + * | bootloader_data_rtc_mem | s_bootloader_retain_mem + * | (ESP_BOOTLOADER_RESERVE_RTC)| + * |- - - - - - - - - - - - - - -| + * | rtc_timer_data_in_rtc_mem | s_rtc_timer_retain_mem (24 bytes) + * | (RTC_TIMER_RESERVE_RTC) | + * +-----------------------------+ 0x60100000 - RESERVE_RTC_MEM + * | rtc_iram_seg | + * | (= rtc_data_seg) | + * |- - - - - - - - - - - - - - -| + * | .rtc.text | RTC wake stub code + * |- - - - - - - - - - - - - - -| + * | .rtc.data / .rtc.rodata | (when CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM) + * |- - - - - - - - - - - - - - -| + * | .rtc.bss | + * +-----------------------------+ 0x600FE000 (RTC FAST memory start) + * + * ==================== RTC SLOW Memory ==================== + * Size: 8KB (0x2000) + * Address: 0x50000000 - 0x50002000 + * + * +-----------------------------+ 0x50002000 (RTC FAST memory end) + * | rtc_slow_seg | + * |- - - - - - - - - - - - - - -| + * | .rtc.data / .rtc.rodata | (when !CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM) + * |- - - - - - - - - - - - - - -| + * | .rtc.bss | + * +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled) + * | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM) + * | (code + data) | + * +-----------------------------+ 0x50000000 (RTC FAST memory start) + * + * RESERVE_RTC_MEM calculation: + * - RTC_TIMER_RESERVE_RTC = 24 bytes + * - ESP_BOOTLOADER_RESERVE_RTC = ALIGN_UP(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE, 8) + * + * Note: RTC FAST memory shares the same address range for both data and + * instruction access. RTC data can be placed in either FAST or SLOW + * memory based on CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM configuration. + */ + /** * RTC fast memory (executable). Persists over deep sleep. */