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docs(esp_system): add detailed RTC memory layout documentation

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wuzhenghui
2026-01-09 11:15:15 +08:00
parent 9a20ef85f5
commit c17787722c
9 changed files with 369 additions and 1 deletions
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components/esp_system/ld/esp32/memory.ld.in
+54
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@@ -88,6 +88,60 @@ MEMORY
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* RTC Memory Layout for ESP32
*
* ESP32 has two separate RTC memory regions:
* 1. RTC FAST Memory: 8KB, accessible by PRO_CPU only
* 2. RTC SLOW Memory: 8KB, accessible by both CPUs and ULP coprocessor
*
* ==================== RTC FAST Memory ====================
* Size: 8KB (0x2000)
* IRAM View: 0x400C0000 - 0x400C2000 (executable)
* DRAM View: 0x3FF80000 - 0x3FF82000 (data access)
*
* +-----------------------------+ 0x400C2000 / 0x3FF82000 (RTC FAST memory end)
* | rtc_fast_reserved_seg |
* | (ESP_BOOTLOADER_RESERVE_RTC)|
* |- - - - - - - - - - - - - - -|
* | bootloader_data_rtc_mem | s_bootloader_retain_mem
* +-----------------------------+ 0x400C2000 - ESP_BOOTLOADER_RESERVE_RTC
* | rtc_iram_seg / |
* | rtc_data_seg |
* | .rtc.text | RTC wake stub code
* |- - - - - - - - - - - - - - -|
* | .rtc.data / .rtc.rodata | (when CONFIG_ESP32_RTCDATA_IN_FAST_MEM)
* |- - - - - - - - - - - - - - -|
* | .rtc.bss |
* +-----------------------------+ 0x400C0000 / 0x3FF80000 (RTC FAST memory start)
*
* ==================== RTC SLOW Memory ====================
* Size: 8KB (0x2000)
* Address: 0x50000000 - 0x50002000
*
* +-----------------------------+ 0x50002000 (RTC SLOW memory end)
* | rtc_slow_reserved_seg |
* | (RESERVE_RTC_MEM = 24) |
* |- - - - - - - - - - - - - - -|
* | rtc_timer_data_in_rtc_mem | s_rtc_timer_retain_mem (24 bytes)
* | (RTC_TIMER_RESERVE_RTC) |
* +-----------------------------+ 0x50002000 - RESERVE_RTC_MEM
* | rtc_slow_seg |
* |- - - - - - - - - - - - - - -|
* | .rtc.data / .rtc.rodata | (when !CONFIG_ESP32_RTCDATA_IN_FAST_MEM)
* | .rtc.bss |
* +-----------------------------+ 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled)
* | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM)
* | (code + data) |
* +-----------------------------+ 0x50000000 (RTC SLOW memory start)
*
* ESP_BOOTLOADER_RESERVE_RTC = ALIGN_UP(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE, 8)
* RESERVE_RTC_MEM = RTC_TIMER_RESERVE_RTC (24 bytes) for ESP32
*
* Note: RTC data can be placed in either FAST or SLOW memory based on
* CONFIG_ESP32_RTCDATA_IN_FAST_MEM configuration option.
*/
/* RTC fast memory (executable). Persists over deep sleep. */
rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC