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update rng souce enable and disable

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This commit is contained in:
hongshuqing
2026-03-30 15:49:16 +08:00
committed by gaoxu
parent 8c74734591
commit ad310ce681
2 changed files with 106 additions and 21 deletions
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87
components/bootloader_support/src/bootloader_random_esp32h4.c
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@@ -9,32 +9,89 @@
#include "soc/soc.h"
#include "soc/rng_reg.h"
#include "esp_rom_sys.h"
#include "soc/pcr_reg.h"
#include "soc/pmu_reg.h"
#include "soc/apb_saradc_reg.h"
#include "esp_private/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
static const uint32_t SAR2_CHANNEL = 9;
static const uint32_t SAR1_CHANNEL = 7;
static const uint32_t PATTERN_BIT_WIDTH = 6;
static const uint32_t SAR1_ATTEN = 3;
static const uint32_t SAR2_ATTEN = 3;
void sar_adc_enable(void)
{
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
REG_CLR_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SARADC, I2C_SARADC_DTEST, 0);
REGI2C_WRITE_MASK(I2C_SARADC, I2C_SARADC_ENT_SAR, 1);
REGI2C_WRITE_MASK(I2C_SARADC, I2C_SARADC_SAR1_EN_TOUT, 1);
REGI2C_WRITE_MASK(I2C_SARADC, I2C_SARADC_SAR2_EN_TOUT, 1);
REGI2C_WRITE_MASK(I2C_SARADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0x08);
REGI2C_WRITE_MASK(I2C_SARADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0x66);
REGI2C_WRITE_MASK(I2C_SARADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0x08);
REGI2C_WRITE_MASK(I2C_SARADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0x66);
uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN;
uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN;
uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) |pattern_one << 2 * PATTERN_BIT_WIDTH;
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1);
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
}
void sar_adc_disable(void)
{
REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
}
void bootloader_random_enable(void)
{
REG_SET_BIT(RNG_DATE_REG, RNG_CLK_EN);
REG_SET_BIT(RNG_CFG_REG, RNG_TIMER_EN);
REG_SET_FIELD(RNG_CFG_REG, RNG_RTC_TIMER_EN, 0x3);
// Enable source of saradc
sar_adc_enable();
// Enable source of ring
REG_SET_BIT(RNG_CFG_REG, RNG_SAMPLE_ENABLE);
// // For dieharder test
// esp_rom_printf("H4: Random bytes (%s) follow:\n", "test");
// while (1)
// {
// uint32_t random_sync = REG_READ(RNG_DATA_SYNC_REG);
// // esp_rom_printf("sync_random_data: %d\n", random_sync);
for (int i = 0; i < 10; i++) {
uint32_t random_sync = REG_READ(RNG_DATA_SYNC_REG);
uint32_t random_unsync = REG_READ(RNG_DATA_REG);
uint32_t rng_cfg = REG_READ(RNG_CFG_REG);
uint32_t sample_cnt = (rng_cfg >> RNG_SAMPLE_CNT_S) & 0xFF;
esp_rom_printf(" [%d] sync: 0x%08x, unsync: 0x%08x, sample_cnt: 0x%02x\r\n",
i + 1, random_sync, random_unsync, sample_cnt);
esp_rom_delay_us(1000);
}
// uart_tx_one_char(random_sync >> 24);
// uart_tx_one_char(random_sync >> 16);
// uart_tx_one_char(random_sync >> 8);
// uart_tx_one_char(random_sync);
// }
}
void bootloader_random_disable(void)
{
// Disable source of saradc
sar_adc_disable();
// Disable source of ring
REG_CLR_BIT(RNG_CFG_REG, RNG_SAMPLE_ENABLE);
REG_SET_FIELD(RNG_CFG_REG, RNG_RTC_TIMER_EN, 0x0);
REG_CLR_BIT(RNG_CFG_REG, RNG_TIMER_EN);
REG_CLR_BIT(RNG_DATE_REG, RNG_CLK_EN);
}

40
components/soc/esp32h4/include/soc/regi2c_saradc.h
View File

@@ -1,11 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#define I2C_SAR_ADC 0x69
#define I2C_SAR_ADC_HOSTID 0
@@ -52,7 +50,37 @@
#define ADC_SAR1_ENCAL_GND_ADDR 0x8
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x1
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x1
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 0x3
#define I2C_SARADC_TSENS_DAC_LSB 0x0
#define I2C_SARADC 0x69
#define I2C_SARADC_HOSTID 0
#define I2C_SARADC_SAR1_INIT_CODE_LSB 0
#define I2C_SARADC_SAR1_INIT_CODE_LSB_MSB 7
#define I2C_SARADC_SAR1_INIT_CODE_LSB_LSB 0
#define I2C_SARADC_SAR1_INIT_CODE_MSB 1
#define I2C_SARADC_SAR1_INIT_CODE_MSB_MSB 3
#define I2C_SARADC_SAR1_INIT_CODE_MSB_LSB 0
#define I2C_SARADC_SAR2_INIT_CODE_LSB 3
#define I2C_SARADC_SAR2_INIT_CODE_LSB_MSB 7
#define I2C_SARADC_SAR2_INIT_CODE_LSB_LSB 0
#define I2C_SARADC_SAR2_INIT_CODE_MSB 4
#define I2C_SARADC_SAR2_INIT_CODE_MSB_MSB 3
#define I2C_SARADC_SAR2_INIT_CODE_MSB_LSB 0
#define I2C_SARADC_SAR1_EN_TOUT 8
#define I2C_SARADC_SAR1_EN_TOUT_MSB 0
#define I2C_SARADC_SAR1_EN_TOUT_LSB 0
#define I2C_SARADC_SAR2_EN_TOUT 8
#define I2C_SARADC_SAR2_EN_TOUT_MSB 2
#define I2C_SARADC_SAR2_EN_TOUT_LSB 2