Merge branch 'fix/cache_panic_reset_reason' into 'master'

fix: changed the expected axi reset reason for S31

See merge request espressif/esp-idf!52062

components/esp_system/test_apps/.build-test-rules.yml

@@ -1,6 +1,8 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
 
 components/esp_system/test_apps/cache_panic:
+  disable:
+    - if: (CONFIG_NAME == "panic_iram" and IDF_TARGET not in ["esp32p4", "esp32s31"])
   depends_components:
     - *common_components
     - spi_flash  # esp_system is included by default

components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c

@@ -96,7 +96,7 @@ static void IRAM_ATTR cache_access_test_func(void* arg)
 #define CACHE_ERROR_REASON "Cache error,SW_CPU"
 #endif
 
-// These tests works properly if they resets the chip with the
+// These tests work properly if they reset the chip with the
 // "Cache Error" reason and the correct CPU is logged.
 static void invalid_access_to_cache_pro_cpu(void)
 {
@@ -119,13 +119,11 @@ TEST_CASE_MULTIPLE_STAGES("invalid access to cache raises panic (APP CPU)", "[ms
 #endif // !CONFIG_FREERTOS_UNICORE
 #endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
 
-#if MSPI_LL_AXI_DISABLE_SUPPORTED
-#if CONFIG_IDF_TARGET_ESP32P4
-#define AXI_RESET_REASON    ESP_RST_WDT
-#elif CONFIG_IDF_TARGET_ESP32S31
-//aligned with rom impl
-#define AXI_RESET_REASON    5
-#endif
+#if MSPI_LL_AXI_DISABLE_SUPPORTED && CONFIG_ESP_PANIC_HANDLER_IRAM
+// AXI stays closed after the first fault. A flash-resident panic handler would nested-fault (CPU lockup / WDT).
+// Using IRAM handler can complete with ESP_RST_PANIC.
+
+#define AXI_RESET_REASON    ESP_RST_PANIC
 static void reset_after_disable_axi(void)
 {
     //For now we only support AXI disabling LL APIs, so the reset reason will be AXI_RESET_REASON
@@ -149,4 +147,4 @@ static void NOINLINE_ATTR IRAM_ATTR s_invalid_axi_access(void)
 }
 
 TEST_CASE_MULTIPLE_STAGES("invalid access to axi bus", "[mspi][reset="CACHE_ERROR_REASON"]", s_invalid_axi_access, reset_after_disable_axi);
-#endif // MSPI_LL_AXI_DISABLE_SUPPORTED
+#endif // MSPI_LL_AXI_DISABLE_SUPPORTED && CONFIG_ESP_PANIC_HANDLER_IRAM

components/esp_system/test_apps/cache_panic/pytest_cache_panic_test.py

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 import pytest
 from pytest_embedded import Dut
@@ -6,6 +6,14 @@ from pytest_embedded_idf.utils import idf_parametrize
 
 
 @pytest.mark.generic
+@idf_parametrize('config', ['default'], indirect=['config'])
 @idf_parametrize('target', ['supported_targets'], indirect=['target'])
 def test_cache_panic(dut: Dut) -> None:
     dut.run_all_single_board_cases()
+
+
+@pytest.mark.generic
+@idf_parametrize('config', ['panic_iram'], indirect=['config'])
+@idf_parametrize('target', ['esp32p4', 'esp32s31'], indirect=['target'])
+def test_cache_panic_axi(dut: Dut) -> None:
+    dut.run_all_single_board_cases()

components/esp_system/test_apps/cache_panic/sdkconfig.ci.panic_iram

@@ -0,0 +1,4 @@
+# Place the panic handler in IRAM for the AXI access case.
+# Closing AXI then fetching a flash-resident handler causes a nested
+# exception (CPU lockup / WDT reset) instead of ESP_RST_PANIC.
+CONFIG_ESP_PANIC_HANDLER_IRAM=y