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Merge branch 'fix/spi_clean_soc_caps' into 'master'

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refactor(driver_spi): clean spi soc caps

See merge request espressif/esp-idf!44083
This commit is contained in:
Wan Lei
2025-12-15 20:48:21 +08:00
parent d43b601ae0 13e1ae57e1
commit a633083633
50 changed files with 348 additions and 1037 deletions
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components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+8 -56
View File
@@ -443,70 +443,14 @@ config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAX_CS_NUM
int
default 6
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_SPI_SUPPORT_CLK_PLL_F40M
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_SPI_SCT_SUPPORTED
bool
default y
config SOC_SPI_SCT_REG_NUM
int
default 14
config SOC_SPI_SCT_BUFFER_NUM_MAX
bool
default y
config SOC_SPI_SCT_CONF_BITLEN_MAX
hex
default 0x3FFFA
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
@@ -535,6 +479,14 @@ config SOC_SPI_MEM_SUPPORT_WRAP
bool
default y
config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED
bool
default y
components/soc/esp32c2/include/soc/soc_caps.h
+8 -27
View File
@@ -211,35 +211,13 @@
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAX_CS_NUM 6
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define SOC_SPI_SUPPORT_CLK_XTAL 1
#define SOC_SPI_SUPPORT_CLK_PLL_F40M 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_SPI_SCT_SUPPORTED 1
#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer
#define SOC_SPI_SCT_REG_NUM 14
#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs
#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4
#define SOC_SPI_SCT_SUPPORTED(host_id) ((host_id) == 1)
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
@@ -250,6 +228,9 @@
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
// Peripheral supports output given level during its "dummy phase"
#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1