diff --git a/components/esp_driver_spi/include/esp_private/spi_master_internal.h b/components/esp_driver_spi/include/esp_private/spi_master_internal.h index 8ac30ca9217..cdd85114ec1 100644 --- a/components/esp_driver_spi/include/esp_private/spi_master_internal.h +++ b/components/esp_driver_spi/include/esp_private/spi_master_internal.h @@ -20,7 +20,7 @@ extern "C" { #endif -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED /** * @Backgrounds: `SCT Mode` * Segmented-Configure-Transfer Mode @@ -115,7 +115,7 @@ esp_err_t spi_device_queue_multi_trans(spi_device_handle_t handle, spi_multi_tra * - ESP_ERR_TIMEOUT: Timeout, didn't get a completed SCT transaction */ esp_err_t spi_device_get_multi_trans_result(spi_device_handle_t handle, spi_multi_transaction_t **seg_trans_desc, uint32_t ticks_to_wait); -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED #ifdef __cplusplus } diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index 648683d07b3..90d6f66e959 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -154,7 +154,7 @@ int spicommon_irqdma_source_for_host(spi_host_device_t host) #if SPI_LL_DMA_SHARED static inline shared_periph_module_t get_dma_periph(int dma_chan) { - assert(dma_chan >= 1 && dma_chan <= SOC_SPI_DMA_CHAN_NUM); + assert(dma_chan >= 1 && dma_chan <= SPI_LL_DMA_CHANNEL_NUM); if (dma_chan == 1) { return PERIPH_SPI2_DMA_MODULE; } else if (dma_chan == 2) { @@ -220,7 +220,7 @@ static esp_err_t alloc_dma_chan(spi_host_device_t host_id, spi_dma_chan_t dma_ch if (dma_chan == SPI_DMA_CH_AUTO) { #if CONFIG_IDF_TARGET_ESP32 - for (int i = 1; i < SOC_SPI_DMA_CHAN_NUM + 1; i++) { + for (int i = 1; i < SPI_LL_DMA_CHANNEL_NUM + 1; i++) { success = claim_dma_chan(i, &actual_dma_chan); if (success) { break; diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c index 99adebb6d2c..d034c909672 100644 --- a/components/esp_driver_spi/src/gpspi/spi_master.c +++ b/components/esp_driver_spi/src/gpspi/spi_master.c @@ -188,12 +188,12 @@ typedef struct { const uint32_t *buffer_to_send; //equals to tx_data, if SPI_TRANS_USE_RXDATA is applied; otherwise if original buffer wasn't in DMA-capable memory, this gets the address of a temporary buffer that is; //otherwise sets to the original buffer or NULL if no buffer is assigned. uint32_t *buffer_to_rcv; //similar to buffer_to_send -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED uint32_t reserved[2]; //As we create the queue when in init, to use sct mode private descriptor as a queue item (when in sct mode), we need to add a dummy member here to keep the same size with `spi_sct_trans_priv_t`. #endif } spi_trans_priv_t; -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED //Type of dma descriptors that used under SPI SCT mode typedef struct { spi_dma_desc_t *tx_seg_head; @@ -225,7 +225,7 @@ typedef struct { intr_handle_t intr; spi_hal_context_t hal; spi_trans_priv_t cur_trans_buf; -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED spi_sct_desc_ctx_t sct_desc_pool; spi_sct_trans_priv_t cur_sct_trans; #endif @@ -453,14 +453,12 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa const spi_bus_attr_t* bus_attr = host->bus_attr; SPI_CHECK(dev_config->spics_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(dev_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG); SPI_CHECK(dev_config->clock_speed_hz > 0, "invalid sclk speed", ESP_ERR_INVALID_ARG); -#if SOC_SPI_SUPPORT_CLK_RC_FAST - if (dev_config->clock_source == SPI_CLK_SRC_RC_FAST) { - SPI_CHECK(periph_rtc_dig_clk8m_enable(), "the selected clock not available", ESP_ERR_INVALID_STATE); - } -#endif uint32_t clock_source_hz = 0; uint32_t clock_source_div = 1; spi_clock_source_t clk_src = dev_config->clock_source ? dev_config->clock_source : SPI_CLK_SRC_DEFAULT; + if ((soc_module_clk_t)clk_src == SOC_MOD_CLK_RC_FAST) { + SPI_CHECK(periph_rtc_dig_clk8m_enable(), "the selected clock not available", ESP_ERR_INVALID_STATE); + } SPI_CHECK(esp_clk_tree_enable_src(clk_src, true) == ESP_OK, "clock source enable failed", ESP_ERR_INVALID_STATE); esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz); #if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV @@ -576,7 +574,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa hal_dev->tx_lsbfirst = dev_config->flags & SPI_DEVICE_TXBIT_LSBFIRST ? 1 : 0; hal_dev->rx_lsbfirst = dev_config->flags & SPI_DEVICE_RXBIT_LSBFIRST ? 1 : 0; hal_dev->no_compensate = dev_config->flags & SPI_DEVICE_NO_DUMMY ? 1 : 0; -#if SOC_SPI_AS_CS_SUPPORTED +#if SPI_LL_SUPPORT_CLK_AS_CS hal_dev->as_cs = dev_config->flags & SPI_DEVICE_CLK_AS_CS ? 1 : 0; #endif hal_dev->positive_cs = dev_config->flags & SPI_DEVICE_POSITIVE_CS ? 1 : 0; @@ -611,8 +609,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle) SPI_CHECK(uxQueueMessagesWaiting(handle->ret_queue) == 0, "Have unfinished transactions", ESP_ERR_INVALID_STATE); } -#if SOC_SPI_SUPPORT_CLK_RC_FAST - if (handle->hal_dev.timing_conf.clock_source == SPI_CLK_SRC_RC_FAST) { + if ((soc_module_clk_t)handle->hal_dev.timing_conf.clock_source == SOC_MOD_CLK_RC_FAST) { // If no transactions from other device, acquire the bus to switch module clock to `SPI_CLK_SRC_DEFAULT` // because `SPI_CLK_SRC_RC_FAST` will be disabled then, which block following transactions if (handle->host->cur_cs == DEV_NUM_MAX) { @@ -624,7 +621,6 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle) } periph_rtc_dig_clk8m_disable(); } -#endif SPI_CHECK(esp_clk_tree_enable_src(handle->hal_dev.timing_conf.clock_source, false) == ESP_OK, "clock source disable failed", ESP_ERR_INVALID_STATE); //return @@ -870,7 +866,7 @@ static void SPI_MASTER_ISR_ATTR spi_post_trans(spi_host_t *host) host->cur_cs = DEV_NUM_MAX; } -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED static void SPI_MASTER_ISR_ATTR spi_sct_set_hal_trans_config(spi_multi_transaction_t *trans_header, spi_hal_trans_config_t *hal_trans) { spi_transaction_t *trans = &trans_header->base; @@ -943,7 +939,7 @@ static void SPI_MASTER_ISR_ATTR spi_post_sct_trans(spi_host_t *host) host->cur_cs = DEV_NUM_MAX; } -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED static void SPI_MASTER_ISR_ATTR spi_trans_dma_error_check(spi_host_t *host) { @@ -976,7 +972,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) const spi_dma_ctx_t *dma_ctx = host->dma_ctx; #endif -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED assert(spi_hal_usr_is_done(&host->hal) || spi_hal_get_intr_mask(&host->hal, SPI_LL_INTR_SEG_DONE)); #else assert(spi_hal_usr_is_done(&host->hal)); @@ -1005,7 +1001,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) spi_trans_dma_error_check(host); } -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED if (host->sct_mode_enabled) { //cur_cs is changed to DEV_NUM_MAX here spi_post_sct_trans(host); @@ -1013,7 +1009,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) xQueueSendFromISR(host->device[cs]->ret_queue, &host->cur_sct_trans, &do_yield); } } else -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED { //cur_cs is changed to DEV_NUM_MAX here spi_post_trans(host); @@ -1058,11 +1054,11 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) bool dev_has_req = spi_bus_lock_bg_check_dev_req(desired_dev); if (dev_has_req) { device_to_send = host->device[spi_bus_lock_get_dev_id(desired_dev)]; -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED if (host->sct_mode_enabled) { trans_found = xQueueReceiveFromISR(device_to_send->trans_queue, &host->cur_sct_trans, &do_yield); } else -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED { trans_found = xQueueReceiveFromISR(device_to_send->trans_queue, &host->cur_trans_buf, &do_yield); } @@ -1073,11 +1069,11 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) } if (trans_found) { -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED if (host->sct_mode_enabled) { spi_new_sct_trans(device_to_send, &host->cur_sct_trans); } else -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED { spi_trans_priv_t *const cur_trans_buf = &host->cur_trans_buf; #if CONFIG_IDF_TARGET_ESP32 @@ -1521,7 +1517,7 @@ esp_err_t spi_bus_get_max_transaction_len(spi_host_device_t host_id, size_t *max return ESP_OK; } -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED /*----------------------------------------------------------- * Below functions should be in the same spinlock @@ -1568,12 +1564,12 @@ static void SPI_MASTER_ISR_ATTR spi_hal_sct_tx_dma_desc_recycle(spi_sct_desc_ctx desc_ctx->tx_free_desc_num += recycle_num; } -static void SPI_MASTER_ISR_ATTR s_sct_prepare_tx_seg(spi_sct_desc_ctx_t *desc_ctx, const uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX], const void *send_buffer, uint32_t buf_len_bytes, spi_dma_desc_t **trans_head) +static void SPI_MASTER_ISR_ATTR s_sct_prepare_tx_seg(spi_sct_desc_ctx_t *desc_ctx, const uint32_t *conf_buffer, const void *send_buffer, uint32_t buf_len_bytes, spi_dma_desc_t **trans_head) { const spi_dma_ctx_t *dma_ctx = __containerof(desc_ctx, spi_host_t, sct_desc_pool)->dma_ctx; *trans_head = desc_ctx->cur_tx_seg_link; - s_sct_setup_desc_anywhere(dma_ctx->dmadesc_tx, desc_ctx->cur_tx_seg_link, dma_ctx->dma_desc_num, conf_buffer, SOC_SPI_SCT_BUFFER_NUM_MAX * 4, false); + s_sct_setup_desc_anywhere(dma_ctx->dmadesc_tx, desc_ctx->cur_tx_seg_link, dma_ctx->dma_desc_num, conf_buffer, SPI_LL_SCT_CONF_BUF_NUM * 4, false); spi_dma_desc_t *conf_buffer_link = desc_ctx->cur_tx_seg_link; desc_ctx->tx_free_desc_num -= 1; @@ -1596,7 +1592,7 @@ static void SPI_MASTER_ISR_ATTR s_sct_prepare_tx_seg(spi_sct_desc_ctx_t *desc_ct } } -static esp_err_t SPI_MASTER_ISR_ATTR spi_hal_sct_new_tx_dma_desc_head(spi_sct_desc_ctx_t *desc_ctx, const uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX], const void *send_buffer, uint32_t buf_len_bytes, spi_dma_desc_t **trans_head, uint32_t *used_desc_num) +static esp_err_t SPI_MASTER_ISR_ATTR spi_hal_sct_new_tx_dma_desc_head(spi_sct_desc_ctx_t *desc_ctx, const uint32_t *conf_buffer, const void *send_buffer, uint32_t buf_len_bytes, spi_dma_desc_t **trans_head, uint32_t *used_desc_num) { //1 desc for the conf_buffer, other for data. int desc_need = 1 + s_sct_desc_get_required_num(buf_len_bytes); @@ -1610,7 +1606,7 @@ static esp_err_t SPI_MASTER_ISR_ATTR spi_hal_sct_new_tx_dma_desc_head(spi_sct_de return ESP_OK; } -static esp_err_t SPI_MASTER_ISR_ATTR spi_hal_sct_link_tx_seg_dma_desc(spi_sct_desc_ctx_t *desc_ctx, const uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX], const void *send_buffer, uint32_t buf_len_bytes, uint32_t *used_desc_num) +static esp_err_t SPI_MASTER_ISR_ATTR spi_hal_sct_link_tx_seg_dma_desc(spi_sct_desc_ctx_t *desc_ctx, const uint32_t *conf_buffer, const void *send_buffer, uint32_t buf_len_bytes, uint32_t *used_desc_num) { //1 desc for the conf_buffer, other for data. int desc_need = 1 + s_sct_desc_get_required_num(buf_len_bytes); @@ -1703,7 +1699,7 @@ static void s_spi_sct_reset_dma_pool(const spi_dma_ctx_t *dma_ctx, spi_sct_desc_ esp_err_t spi_bus_multi_trans_mode_enable(spi_device_handle_t handle, bool enable) { SPI_CHECK(handle, "Invalid arguments.", ESP_ERR_INVALID_ARG); - SPI_CHECK(SOC_SPI_SCT_SUPPORTED_PERIPH(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG); + SPI_CHECK(SOC_SPI_SCT_SUPPORTED(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG); SPI_CHECK(handle->cfg.flags & SPI_DEVICE_HALFDUPLEX, "SCT mode only available under Half Duplex mode", ESP_ERR_INVALID_STATE); SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot queue new transaction while previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE); SPI_CHECK(uxQueueMessagesWaiting(handle->trans_queue) == 0, "Cannot enable SCT mode when internal Queue still has items", ESP_ERR_INVALID_STATE); @@ -1756,11 +1752,11 @@ static void SPI_MASTER_ATTR s_sct_init_conf_buffer(spi_hal_context_t *hal, uint3 { // read from HW need waiting for slower APB clock domain return data, loop to contact slow clock domain will waste time. // use one imagen then copied by cpu instead. - uint32_t conf_buffer_img[SOC_SPI_SCT_BUFFER_NUM_MAX]; + uint32_t conf_buffer_img[SPI_LL_SCT_CONF_BUF_NUM]; spi_hal_sct_init_conf_buffer(hal, conf_buffer_img); for (int i = 0; i < trans_num; i++) { - memcpy(&buffer[i * SOC_SPI_SCT_BUFFER_NUM_MAX], conf_buffer_img, sizeof(conf_buffer_img)); + memcpy(&buffer[i * SPI_LL_SCT_CONF_BUF_NUM], conf_buffer_img, sizeof(conf_buffer_img)); } } @@ -1827,7 +1823,7 @@ static void SPI_MASTER_ATTR s_sct_format_conf_buffer(spi_device_handle_t handle, esp_err_t SPI_MASTER_ATTR spi_device_queue_multi_trans(spi_device_handle_t handle, spi_multi_transaction_t *seg_trans_desc, uint32_t trans_num, uint32_t ticks_to_wait) { SPI_CHECK(handle, "Invalid arguments.", ESP_ERR_INVALID_ARG); - SPI_CHECK(SOC_SPI_SCT_SUPPORTED_PERIPH(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG); + SPI_CHECK(SOC_SPI_SCT_SUPPORTED(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG); SPI_CHECK(handle->host->sct_mode_enabled == 1, "SCT mode isn't enabled", ESP_ERR_INVALID_STATE); esp_err_t ret = ESP_OK; @@ -1836,7 +1832,7 @@ esp_err_t SPI_MASTER_ATTR spi_device_queue_multi_trans(spi_device_handle_t handl } SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot queue new transaction while previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE); - uint32_t *conf_buffer = heap_caps_malloc(trans_num * SOC_SPI_SCT_BUFFER_NUM_MAX * sizeof(uint32_t), MALLOC_CAP_DMA); + uint32_t *conf_buffer = heap_caps_malloc(trans_num * SPI_LL_SCT_CONF_BUF_NUM * sizeof(uint32_t), MALLOC_CAP_DMA); SPI_CHECK(conf_buffer, "No enough memory", ESP_ERR_NO_MEM); spi_hal_context_t *hal = &handle->host->hal; @@ -1872,12 +1868,12 @@ esp_err_t SPI_MASTER_ATTR spi_device_queue_multi_trans(spi_device_handle_t handl /*--------------Prepare other segments--------------*/ for (int i = 1; i < trans_num; i++) { - s_sct_format_conf_buffer(handle, &seg_trans_desc[i], &conf_buffer[i * SOC_SPI_SCT_BUFFER_NUM_MAX], (i == (trans_num - 1))); + s_sct_format_conf_buffer(handle, &seg_trans_desc[i], &conf_buffer[i * SPI_LL_SCT_CONF_BUF_NUM], (i == (trans_num - 1))); //TX tx_buf_len = (seg_trans_desc[i].base.length + 8 - 1) / 8; portENTER_CRITICAL(&handle->host->spinlock); - dma_desc_status = spi_hal_sct_link_tx_seg_dma_desc(&handle->host->sct_desc_pool, &conf_buffer[i * SOC_SPI_SCT_BUFFER_NUM_MAX], seg_trans_desc[i].base.tx_buffer, tx_buf_len, &tx_used_dma_desc_num); + dma_desc_status = spi_hal_sct_link_tx_seg_dma_desc(&handle->host->sct_desc_pool, &conf_buffer[i * SPI_LL_SCT_CONF_BUF_NUM], seg_trans_desc[i].base.tx_buffer, tx_buf_len, &tx_used_dma_desc_num); portEXIT_CRITICAL(&handle->host->spinlock); SPI_CHECK(dma_desc_status == ESP_OK, "No available dma descriptors, increase the `max_transfer_sz`, or wait queued transactions are done", ESP_ERR_INVALID_STATE); @@ -1925,7 +1921,7 @@ esp_err_t SPI_MASTER_ATTR spi_device_queue_multi_trans(spi_device_handle_t handl esp_err_t SPI_MASTER_ATTR spi_device_get_multi_trans_result(spi_device_handle_t handle, spi_multi_transaction_t **seg_trans_desc, uint32_t ticks_to_wait) { SPI_CHECK(handle, "Invalid arguments.", ESP_ERR_INVALID_ARG); - SPI_CHECK(SOC_SPI_SCT_SUPPORTED_PERIPH(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG); + SPI_CHECK(SOC_SPI_SCT_SUPPORTED(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG); SPI_CHECK(handle->host->sct_mode_enabled == 1, "SCT mode isn't enabled", ESP_ERR_INVALID_STATE); spi_sct_trans_priv_t sct_desc = {}; @@ -1938,4 +1934,4 @@ esp_err_t SPI_MASTER_ATTR spi_device_get_multi_trans_result(spi_device_handle_t return ESP_OK; } -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c index 88fd1b2f273..3bec4d954a4 100644 --- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c @@ -81,14 +81,14 @@ static void check_spi_pre_n_for(int clk, int pre, int n) * Only test on SPI_CLK_SRC_DEFAULT here */ #define TEST_CLK_TIMES 8 -uint32_t clk_param_80m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} }; -uint32_t clk_param_160m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} }; +uint32_t clk_param_80m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} }; +uint32_t clk_param_160m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} }; #if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV -uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 4, 50}, {333333, 1, 60}, {800000, 1, 25}, {2000000, 1, 10}, {5000000, 1, 4}, {12000000, 1, 2}, {18000000, 1, 1} }; -uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 4, 60}, {333333, 2, 36}, {800000, 1, 30}, {5000000, 1, 5}, {12000000, 1, 2}, {18000000, 1, 2}, {24000000, 1, 1} }; +uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 4, 50}, {333333, 1, 60}, {800000, 1, 25}, {2000000, 1, 10}, {5000000, 1, 4}, {12000000, 1, 2}, {18000000, 1, 1} }; +uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 4, 60}, {333333, 2, 36}, {800000, 1, 30}, {5000000, 1, 5}, {12000000, 1, 2}, {18000000, 1, 2}, {24000000, 1, 1} }; #else -uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 8, 50}, {333333, 2, 60}, {800000, 1, 50}, {2000000, 1, 20}, {5000000, 1, 8}, {12000000, 1, 3}, {18000000, 1, 2} }; -uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 8, 60}, {333333, 3, 48}, {800000, 1, 60}, {5000000, 1, 10}, {12000000, 1, 4}, {18000000, 1, 3}, {26000000, 1, 2} }; +uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 8, 50}, {333333, 2, 60}, {800000, 1, 50}, {2000000, 1, 20}, {5000000, 1, 8}, {12000000, 1, 3}, {18000000, 1, 2} }; +uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 8, 60}, {333333, 3, 48}, {800000, 1, 60}, {5000000, 1, 10}, {12000000, 1, 4}, {18000000, 1, 3}, {26000000, 1, 2} }; #endif TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") @@ -154,11 +154,9 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]") #if CONFIG_IDF_TARGET_ESP32 devcfg.flags |= SPI_DEVICE_HALFDUPLEX; //esp32 half duplex to work on high freq #endif -#if SOC_SPI_SUPPORT_CLK_RC_FAST - if (devcfg.clock_source == SPI_CLK_SRC_RC_FAST) { + if ((soc_module_clk_t)devcfg.clock_source == SOC_MOD_CLK_RC_FAST) { devcfg.clock_speed_hz /= 2; //rc_fast have bad accuracy, test at low speed } -#endif TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle)); // one trans first to trigger lazy load TEST_ESP_OK(spi_device_polling_transmit(handle, &trans)); @@ -1543,6 +1541,7 @@ TEST_CASE("spi_speed", "[spi]") #endif // !(CONFIG_SPIRAM) || (CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL >= 16384) //****************************************spi master add device test************************************// +#define SPI_MAX_DEVICE_NUM SOC_SPI_PERIPH_CS_NUM(TEST_SPI_HOST) //add dummy devices first #if CONFIG_IDF_TARGET_ESP32 #define DUMMY_CS_PINS() {25, 26, 27} @@ -1559,8 +1558,8 @@ TEST_CASE("spi_speed", "[spi]") void test_add_device_master(void) { - spi_device_handle_t devs[SOC_SPI_MAX_CS_NUM] = {}; - uint8_t cs_pins[SOC_SPI_MAX_CS_NUM] = DUMMY_CS_PINS(); + spi_device_handle_t devs[SPI_MAX_DEVICE_NUM] = {}; + uint8_t cs_pins[SPI_MAX_DEVICE_NUM] = DUMMY_CS_PINS(); uint8_t master_sendbuf[TEST_TRANS_LEN] = {0}; uint8_t master_recvbuf[TEST_TRANS_LEN] = {0}; @@ -1574,7 +1573,7 @@ void test_add_device_master(void) .queue_size = 3, }; - for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { + for (uint8_t i = 0; i < SPI_MAX_DEVICE_NUM; i++) { dev_cfg.spics_io_num = cs_pins[i]; TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &devs[i])); } @@ -1584,7 +1583,7 @@ void test_add_device_master(void) trans.tx_buffer = master_sendbuf; trans.rx_buffer = master_recvbuf; - for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { + for (uint8_t i = 0; i < SPI_MAX_DEVICE_NUM; i++) { //1. add max dummy devices //2. replace devs[i] as a real device, than start a transaction //3. free devs[i] after transaction to release the real CS pin for using again by another dev, @@ -1610,7 +1609,7 @@ void test_add_device_master(void) TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &devs[i])); } - for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { + for (uint8_t i = 0; i < SPI_MAX_DEVICE_NUM; i++) { spi_bus_remove_device(devs[i]); } spi_bus_free(TEST_SPI_HOST); @@ -1635,7 +1634,7 @@ void test_add_device_slave(void) slave_trans.rx_buffer = slave_recvbuf; slave_trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO; - for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) { + for (uint8_t i = 0; i < SPI_MAX_DEVICE_NUM; i++) { memset(slave_recvbuf, 0, sizeof(slave_recvbuf)); test_fill_random_to_buffers_dualboard(21, slave_expect, slave_sendbuf, TEST_TRANS_LEN); diff --git a/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h index 8685e5312d4..9f89c03d345 100644 --- a/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ -// The LL layer for ESP32 SPI register operations - #pragma once #include @@ -40,8 +38,11 @@ extern "C" { #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len)) #define SPI_LL_GET_HW(ID) ((ID)==0? &SPI1:((ID)==1? &SPI2 : &SPI3)) +#define SPI_LL_DMA_CHANNEL_NUM (2) #define SPI_LL_DMA_MAX_BIT_LEN (1 << 24) //reg len: 24 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (8192) +#define SPI_LL_SUPPORT_CLK_AS_CS 1 //Output clock on CS line if CS is active #define SPI_LL_MOSI_FREE_LEVEL 0 //Default level after bus initialized // CS_WORKAROUND: SPI slave with using DMA, the rx dma suffers from unexpected transactions @@ -709,8 +710,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 8192) { - pre = 8192; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { diff --git a/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h index bd838e71e69..4b6218ab0e6 100644 --- a/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ -// The LL layer for SPI register operations - #pragma once #include //for abs() @@ -41,12 +39,10 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized +#define SPI_LL_MAX_PRE_DIV_NUM (16) +#define SPI_LL_MAX_SCT_CONF_LEN (0x3FFFA) //18 bits wide reg +#define SPI_LL_SCT_CONF_BUF_NUM (1 + 14) //1-word-bitmap + 14-word-regs according to TRM -/** - * The data structure holding calculated clock configuration. Since the - * calculation needs long time, it should be calculated during initialization and - * stored somewhere to be quickly used. - */ typedef uint32_t spi_ll_clock_val_t; typedef spi_dev_t spi_dma_dev_t; @@ -788,8 +784,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { @@ -1334,7 +1330,7 @@ static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) */ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_bitlen) { - if (conf_bitlen <= SOC_SPI_SCT_CONF_BITLEN_MAX) { + if (conf_bitlen <= SPI_LL_MAX_SCT_CONF_LEN) { hw->cmd.conf_bitlen = conf_bitlen; } } @@ -1346,7 +1342,7 @@ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_b * @param is_end Is this transaction the end of this segment. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t *conf_buffer) { //user reg: usr_conf_nxt if (is_end) { @@ -1363,7 +1359,7 @@ static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_e * @param line_mode line mode struct of each phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; @@ -1398,7 +1394,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod * @param setup CS setup time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t *conf_buffer) { //user reg: cs_setup if (setup) { @@ -1420,7 +1416,7 @@ static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t s * @param lsbfirst Whether LSB first * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_command if (cmdlen) { @@ -1449,7 +1445,7 @@ static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t c * @param lsbfirst whether the LSB first feature is enabled. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_addr if (addrlen) { @@ -1476,7 +1472,7 @@ static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t *conf_buffer) { //user reg: usr_dummy if (dummy_n) { @@ -1496,7 +1492,7 @@ static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dumm * @param bitlen output length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_mosi @@ -1520,7 +1516,7 @@ static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitle * @param bitlen input length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_miso @@ -1544,7 +1540,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen * @param setup CS hold time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t *conf_buffer) { //user reg: cs_hold if (hold) { @@ -1567,7 +1563,7 @@ static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, * @param conf_buffer Conf buffer to be updated. */ __attribute__((always_inline)) -static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr; diff --git a/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h index e1553d16d95..354619793f2 100644 --- a/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ -// The LL layer for SPI register operations - #pragma once #include //for abs() @@ -40,6 +38,9 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) +#define SPI_LL_MAX_SCT_CONF_LEN (0x3FFFA) //18 bits wide reg +#define SPI_LL_SCT_CONF_BUF_NUM (1 + 14) //1-word-bitmap + 14-word-regs according to TRM #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized /** @@ -788,8 +789,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { @@ -1248,7 +1249,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) */ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_bitlen) { - if (conf_bitlen <= SOC_SPI_SCT_CONF_BITLEN_MAX) { + if (conf_bitlen <= SPI_LL_MAX_SCT_CONF_LEN) { hw->cmd.conf_bitlen = conf_bitlen; } } @@ -1260,7 +1261,7 @@ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_b * @param is_end Is this transaction the end of this segment. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t *conf_buffer) { //user reg: usr_conf_nxt if (is_end) { @@ -1277,7 +1278,7 @@ static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_e * @param line_mode line mode struct of each phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; @@ -1312,7 +1313,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod * @param setup CS setup time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t *conf_buffer) { //user reg: cs_setup if (setup) { @@ -1334,7 +1335,7 @@ static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t s * @param lsbfirst Whether LSB first * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_command if (cmdlen) { @@ -1363,7 +1364,7 @@ static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t c * @param lsbfirst whether the LSB first feature is enabled. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_addr if (addrlen) { @@ -1390,7 +1391,7 @@ static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t *conf_buffer) { //user reg: usr_dummy if (dummy_n) { @@ -1410,7 +1411,7 @@ static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dumm * @param bitlen output length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_mosi @@ -1434,7 +1435,7 @@ static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitle * @param bitlen input length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_miso @@ -1458,7 +1459,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen * @param setup CS hold time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t *conf_buffer) { //user reg: cs_hold if (hold) { @@ -1481,7 +1482,7 @@ static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, * @param conf_buffer Conf buffer to be updated. */ __attribute__((always_inline)) -static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr; diff --git a/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h index 8ad078822cd..240fc013660 100644 --- a/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h @@ -6,8 +6,8 @@ /******************************************************************************* * NOTICE - * The LL layer for ESP32C5 SPI register operations - * It is NOT public api, don't use in application code. + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ #pragma once @@ -39,6 +39,7 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN SPI_MS_DATA_BITLEN #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral #define SPI_LL_SRC_PRE_DIV_MAX (PCR_SPI2_CLKM_DIV_NUM + 1) //source pre divider max @@ -789,8 +790,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { diff --git a/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h index 8e4212fa3a3..522f82f8bca 100644 --- a/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ -// The LL layer for SPI register operations - #pragma once #include //for abs() @@ -40,6 +38,9 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) +#define SPI_LL_MAX_SCT_CONF_LEN (0x3FFFA) //18 bits wide reg +#define SPI_LL_SCT_CONF_BUF_NUM (1 + 14) //1-word-bitmap + 14-word-regs according to TRM #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized /** @@ -773,8 +774,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { @@ -1233,7 +1234,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) */ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_bitlen) { - if (conf_bitlen <= SOC_SPI_SCT_CONF_BITLEN_MAX) { + if (conf_bitlen <= SPI_LL_MAX_SCT_CONF_LEN) { hw->cmd.conf_bitlen = conf_bitlen; } } @@ -1245,7 +1246,7 @@ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_b * @param is_end Is this transaction the end of this segment. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t *conf_buffer) { //user reg: usr_conf_nxt if (is_end) { @@ -1262,7 +1263,7 @@ static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_e * @param line_mode line mode struct of each phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; @@ -1297,7 +1298,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod * @param setup CS setup time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t *conf_buffer) { //user reg: cs_setup if (setup) { @@ -1319,7 +1320,7 @@ static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t s * @param lsbfirst Whether LSB first * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_command if (cmdlen) { @@ -1348,7 +1349,7 @@ static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t c * @param lsbfirst whether the LSB first feature is enabled. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_addr if (addrlen) { @@ -1375,7 +1376,7 @@ static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t *conf_buffer) { //user reg: usr_dummy if (dummy_n) { @@ -1395,7 +1396,7 @@ static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dumm * @param bitlen output length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_mosi @@ -1419,7 +1420,7 @@ static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitle * @param bitlen input length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_miso @@ -1443,7 +1444,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen * @param setup CS hold time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t *conf_buffer) { //user reg: cs_hold if (hold) { @@ -1466,7 +1467,7 @@ static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, * @param conf_buffer Conf buffer to be updated. */ __attribute__((always_inline)) -static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.usr_addr_value; diff --git a/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h index 404a2ce126b..8e8a4a5665c 100644 --- a/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h @@ -6,8 +6,8 @@ /******************************************************************************* * NOTICE - * The LL layer for ESP32C61 SPI register operations - * It is NOT public api, don't use in application code. + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ #pragma once @@ -39,6 +39,7 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN SPI_MS_DATA_BITLEN #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral #define SPI_LL_SRC_PRE_DIV_MAX (PCR_SPI2_CLKM_DIV_NUM + 1) //source pre divider max @@ -799,8 +800,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { diff --git a/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h index 9af0a43ea31..e8e11c98a54 100644 --- a/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ -// The LL layer for SPI register operations - #pragma once #include //for abs() @@ -42,6 +40,9 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) +#define SPI_LL_MAX_SCT_CONF_LEN (0x3FFFA) //18 bits wide reg +#define SPI_LL_SCT_CONF_BUF_NUM (1 + 14) //1-word-bitmap + 14-word-regs according to TRM #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized /** @@ -775,8 +776,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { @@ -1235,7 +1236,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) */ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_bitlen) { - if (conf_bitlen <= SOC_SPI_SCT_CONF_BITLEN_MAX) { + if (conf_bitlen <= SPI_LL_MAX_SCT_CONF_LEN) { hw->cmd.conf_bitlen = conf_bitlen; } } @@ -1247,7 +1248,7 @@ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_b * @param is_end Is this transaction the end of this segment. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t *conf_buffer) { //user reg: usr_conf_nxt if (is_end) { @@ -1264,7 +1265,7 @@ static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_e * @param line_mode line mode struct of each phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; @@ -1304,7 +1305,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod * @param setup CS setup time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t *conf_buffer) { //user reg: cs_setup if (setup) { @@ -1326,7 +1327,7 @@ static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t s * @param lsbfirst Whether LSB first * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_command if (cmdlen) { @@ -1355,7 +1356,7 @@ static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t c * @param lsbfirst whether the LSB first feature is enabled. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_addr if (addrlen) { @@ -1382,7 +1383,7 @@ static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t *conf_buffer) { //user reg: usr_dummy if (dummy_n) { @@ -1402,7 +1403,7 @@ static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dumm * @param bitlen output length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_mosi @@ -1426,7 +1427,7 @@ static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitle * @param bitlen input length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_miso @@ -1450,7 +1451,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen * @param setup CS hold time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t *conf_buffer) { //user reg: cs_hold if (hold) { @@ -1473,7 +1474,7 @@ static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, * @param conf_buffer Conf buffer to be updated. */ __attribute__((always_inline)) -static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.usr_addr_value; diff --git a/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h index 4ccbabfc2da..6911464a2f1 100644 --- a/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h @@ -6,8 +6,8 @@ /******************************************************************************* * NOTICE - * The LL layer for ESP32H21 SPI register operations - * It is NOT public api, don't use in application code. + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ #pragma once @@ -39,6 +39,9 @@ extern "C" { #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len)) #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) +#define SPI_LL_MAX_SCT_CONF_LEN (0x3FFFA) //18 bits wide reg +#define SPI_LL_SCT_CONF_BUF_NUM (1 + 14) //1-word-bitmap + 14-word-regs according to TRM #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized /** @@ -761,8 +764,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { @@ -1221,7 +1224,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) */ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_bitlen) { - if (conf_bitlen <= SOC_SPI_SCT_CONF_BITLEN_MAX) { + if (conf_bitlen <= SPI_LL_MAX_SCT_CONF_LEN) { hw->cmd.conf_bitlen = conf_bitlen; } } @@ -1233,7 +1236,7 @@ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_b * @param is_end Is this transaction the end of this segment. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t *conf_buffer) { //user reg: usr_conf_nxt if (is_end) { @@ -1250,7 +1253,7 @@ static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_e * @param line_mode line mode struct of each phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; @@ -1290,7 +1293,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod * @param setup CS setup time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t *conf_buffer) { //user reg: cs_setup if (setup) { @@ -1312,7 +1315,7 @@ static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t s * @param lsbfirst Whether LSB first * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_command if (cmdlen) { @@ -1341,7 +1344,7 @@ static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t c * @param lsbfirst whether the LSB first feature is enabled. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_addr if (addrlen) { @@ -1368,7 +1371,7 @@ static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t *conf_buffer) { //user reg: usr_dummy if (dummy_n) { @@ -1388,7 +1391,7 @@ static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dumm * @param bitlen output length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_mosi @@ -1412,7 +1415,7 @@ static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitle * @param bitlen input length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_miso @@ -1436,7 +1439,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen * @param setup CS hold time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t *conf_buffer) { //user reg: cs_hold if (hold) { @@ -1459,7 +1462,7 @@ static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, * @param conf_buffer Conf buffer to be updated. */ __attribute__((always_inline)) -static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.usr_addr_value; diff --git a/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h index 06d8a8fe75e..930a0bf2a96 100644 --- a/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h @@ -6,8 +6,8 @@ /******************************************************************************* * NOTICE - * The LL layer for ESP32H4 SPI register operations - * It is NOT public api, don't use in application code. + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ #pragma once @@ -39,6 +39,7 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN SPI_MS_DATA_BITLEN #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral #define SPI_LL_SRC_PRE_DIV_MAX (PCR_SPI2_CLKM_DIV_NUM + 1) //source pre divider max @@ -821,8 +822,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { diff --git a/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h index 2d2fdc78e37..30b689bd818 100644 --- a/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ -// The LL layer for SPI register operations - #pragma once #include //for abs() @@ -41,6 +39,7 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN SPI_MS_DATA_BITLEN #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral #define SPI_LL_SRC_PRE_DIV_MAX (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM + 1) //source pre divider max #define SPI_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider @@ -862,8 +861,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { diff --git a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h index 90a4d2fb383..165a25f7902 100644 --- a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ -// The LL layer for ESP32-S2 SPI register operations - #pragma once #include //for abs() @@ -45,8 +43,12 @@ extern "C" { #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len)) #define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : (((ID)==2) ? &GPSPI3 : NULL)) +#define SPI_LL_DMA_CHANNEL_NUM (3) #define SPI_LL_DMA_MAX_BIT_LEN (1 << 23) //reg len: 23 bits #define SPI_LL_CPU_MAX_BIT_LEN (18 * 32) //Fifo len: 18 words +#define SPI_LL_MAX_PRE_DIV_NUM (8192) +#define SPI_LL_MAX_SCT_CONF_LEN 0x7FFFFD //23 bit wide reg +#define SPI_LL_SCT_CONF_BUF_NUM (1 + 27) //1-word-bitmap + 27-word-regs according to TRM #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized #define SPI_LL_DMA_SHARED 1 //spi_dma shared with adc and dac on S2 @@ -780,8 +782,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 8192) { - pre = 8192; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { @@ -1591,7 +1593,7 @@ static inline void spi_ll_set_conf_base_bitslen(spi_dev_t *hw, uint8_t conf_base */ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_bitlen) { - if (conf_bitlen <= SOC_SPI_SCT_CONF_BITLEN_MAX) { + if (conf_bitlen <= SPI_LL_MAX_SCT_CONF_LEN) { hw->cmd.conf_bitlen = conf_bitlen; } } @@ -1602,10 +1604,10 @@ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_b * @param hw Beginning address of the peripheral registers. * @param conf_bitlen Value of field conf_bitslen in cmd reg. */ -static inline void spi_ll_format_conf_bitslen_buffer(spi_dev_t *hw, uint32_t conf_bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_conf_bitslen_buffer(spi_dev_t *hw, uint32_t conf_bitlen, uint32_t *conf_buffer) { //cmd reg: conf_bitlen - if (conf_bitlen <= SOC_SPI_SCT_CONF_BITLEN_MAX) { + if (conf_bitlen <= SPI_LL_MAX_SCT_CONF_LEN) { SPI_LL_CONF_BUF_SET_FIELD(conf_buffer[SPI_LL_CMD_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CONF_BITLEN, conf_bitlen); } } @@ -1617,7 +1619,7 @@ static inline void spi_ll_format_conf_bitslen_buffer(spi_dev_t *hw, uint32_t con * @param is_end Is this transaction the end of this segment. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t *conf_buffer) { //user reg: usr_conf_nxt if (is_end) { @@ -1634,7 +1636,7 @@ static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_e * @param line_mode line mode struct of each phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; @@ -1674,7 +1676,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod * @param setup CS setup time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t *conf_buffer) { //user reg: cs_setup if (setup) { @@ -1696,7 +1698,7 @@ static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t s * @param lsbfirst Whether LSB first * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_command if (cmdlen) { @@ -1725,7 +1727,7 @@ static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t c * @param lsbfirst whether the LSB first feature is enabled. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_addr if (addrlen) { @@ -1752,7 +1754,7 @@ static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t *conf_buffer) { //user reg: usr_dummy if (dummy_n) { @@ -1772,7 +1774,7 @@ static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dumm * @param bitlen output length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { //user reg: usr_mosi if (bitlen) { @@ -1792,7 +1794,7 @@ static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitle * @param bitlen input length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { //user reg: usr_miso if (bitlen) { @@ -1812,7 +1814,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen * @param setup CS hold time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t *conf_buffer) { //user reg: cs_hold if (hold) { @@ -1835,7 +1837,7 @@ static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, * @param conf_buffer Conf buffer to be updated. */ __attribute__((always_inline)) -static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFFFFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); conf_buffer[SPI_LL_CMD_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->cmd.val; diff --git a/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h index fe247a09972..3d1ac3e56cf 100644 --- a/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md + * The LL layer is not public api, don't use in application code. + * See readme.md in esp_hal_gpspi/readme.md ******************************************************************************/ -// The LL layer for ESP32-S3 SPI register operations - #pragma once #include //for abs() @@ -42,6 +40,9 @@ extern "C" { #define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words +#define SPI_LL_MAX_PRE_DIV_NUM (16) +#define SPI_LL_MAX_SCT_CONF_LEN (0x3FFFA) //18 bits wide reg +#define SPI_LL_SCT_CONF_BUF_NUM (1 + 14) //1-word-bitmap + 14-word-regs according to TRM #define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized /** @@ -811,8 +812,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ if (pre <= 0) { pre = 1; } - if (pre > 16) { - pre = 16; + if (pre > SPI_LL_MAX_PRE_DIV_NUM) { + pre = SPI_LL_MAX_PRE_DIV_NUM; } errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); if (bestn == -1 || errval <= besterr) { @@ -1274,7 +1275,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) */ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_bitlen) { - if (conf_bitlen <= SOC_SPI_SCT_CONF_BITLEN_MAX) { + if (conf_bitlen <= SPI_LL_MAX_SCT_CONF_LEN) { hw->cmd.conf_bitlen = conf_bitlen; } } @@ -1286,7 +1287,7 @@ static inline void spi_ll_set_conf_phase_bits_len(spi_dev_t *hw, uint32_t conf_b * @param is_end Is this transaction the end of this segment. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_end, uint32_t *conf_buffer) { //user reg: usr_conf_nxt if (is_end) { @@ -1303,7 +1304,7 @@ static inline void spi_ll_format_conf_phase_conf_buffer(spi_dev_t *hw, bool is_e * @param line_mode line mode struct of each phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mode_t line_mode, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK; @@ -1343,7 +1344,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod * @param setup CS setup time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t *conf_buffer) { //user reg: cs_setup if (setup) { @@ -1365,7 +1366,7 @@ static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t s * @param lsbfirst Whether LSB first * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_command if (cmdlen) { @@ -1394,7 +1395,7 @@ static inline void spi_ll_format_cmd_phase_conf_buffer(spi_dev_t *hw, uint16_t c * @param lsbfirst whether the LSB first feature is enabled. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t addr, int addrlen, bool lsbfirst, uint32_t *conf_buffer) { //user reg: usr_addr if (addrlen) { @@ -1421,7 +1422,7 @@ static inline void spi_ll_format_addr_phase_conf_buffer(spi_dev_t *hw, uint64_t * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dummy_n, uint32_t *conf_buffer) { //user reg: usr_dummy if (dummy_n) { @@ -1441,7 +1442,7 @@ static inline void spi_ll_format_dummy_phase_conf_buffer(spi_dev_t *hw, int dumm * @param bitlen output length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_mosi @@ -1465,7 +1466,7 @@ static inline void spi_ll_format_dout_phase_conf_buffer(spi_dev_t *hw, int bitle * @param bitlen input length, in bits. * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen, uint32_t *conf_buffer) { if (bitlen) { //user reg: usr_miso @@ -1489,7 +1490,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen * @param setup CS hold time * @param conf_buffer Conf buffer to be updated. */ -static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t *conf_buffer) { //user reg: cs_hold if (hold) { @@ -1512,7 +1513,7 @@ static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, * @param conf_buffer Conf buffer to be updated. */ __attribute__((always_inline)) -static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr; diff --git a/components/esp_hal_gpspi/include/hal/spi_hal.h b/components/esp_hal_gpspi/include/hal/spi_hal.h index 022880d4254..7479f82a2d0 100644 --- a/components/esp_hal_gpspi/include/hal/spi_hal.h +++ b/components/esp_hal_gpspi/include/hal/spi_hal.h @@ -120,14 +120,14 @@ typedef struct { uint32_t tx_lsbfirst : 1; ///< Whether LSB is sent first for TX data, device specific uint32_t rx_lsbfirst : 1; ///< Whether LSB is received first for RX data, device specific uint32_t no_compensate : 1; ///< No need to add dummy to compensate the timing, device specific -#if SOC_SPI_AS_CS_SUPPORTED +#if SPI_LL_SUPPORT_CLK_AS_CS uint32_t as_cs : 1; ///< Whether to toggle the CS while the clock toggles, device specific #endif uint32_t positive_cs : 1; ///< Whether the positive CS feature is enabled, device specific };//boolean configurations } spi_hal_dev_config_t; -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED /** * SCT mode required configurations, per segment */ @@ -152,7 +152,7 @@ typedef struct { /* DONE State */ int cs_hold; ///< Hold time of CS inactive edge after the last SPI clock } spi_hal_seg_config_t; -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED /** * Init the peripheral and the context. @@ -312,7 +312,7 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int */ int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns); -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED /*---------------------------------------------------------- * Segmented-Configure-Transfer (SCT) Mode * ---------------------------------------------------------*/ @@ -328,7 +328,7 @@ void spi_hal_sct_init(spi_hal_context_t *hal); * * @param hal Context of the HAL layer. */ -void spi_hal_sct_init_conf_buffer(spi_hal_context_t *hal, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]); +void spi_hal_sct_init_conf_buffer(spi_hal_context_t *hal, uint32_t *conf_buffer); /** * Format the conf buffer @@ -338,7 +338,7 @@ void spi_hal_sct_init_conf_buffer(spi_hal_context_t *hal, uint32_t conf_buffer[S * @param config Conf buffer configuration, per segment. See `spi_hal_seg_config_t` to know what can be configured * @param conf_buffer Conf buffer */ -void spi_hal_sct_format_conf_buffer(spi_hal_context_t *hal, const spi_hal_seg_config_t *config, const spi_hal_dev_config_t *dev, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]); +void spi_hal_sct_format_conf_buffer(spi_hal_context_t *hal, const spi_hal_seg_config_t *config, const spi_hal_dev_config_t *dev, uint32_t *conf_buffer); /** * Deinit SCT mode related registers and hal states @@ -354,7 +354,7 @@ void spi_hal_sct_set_conf_bits_len(spi_hal_context_t *hal, uint32_t conf_len); * Set conf_bitslen base to HW for sct, only supported on s2. */ #define spi_hal_sct_setup_conf_base(hal, conf_base) spi_ll_set_conf_base_bitslen((hal)->hw, conf_base) -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED #endif //#if SOC_GPSPI_SUPPORTED #ifdef __cplusplus diff --git a/components/esp_hal_gpspi/include/soc/spi_periph.h b/components/esp_hal_gpspi/include/soc/spi_periph.h index 834b920cfbb..5b03efc28df 100644 --- a/components/esp_hal_gpspi/include/soc/spi_periph.h +++ b/components/esp_hal_gpspi/include/soc/spi_periph.h @@ -49,7 +49,7 @@ typedef struct { const uint8_t spid6_in; const uint8_t spid7_in; #endif // SOC_SPI_SUPPORT_OCT - const uint8_t spics_out[SOC_SPI_MAX_CS_NUM]; // /CS GPIO output mux signals + const uint8_t spics_out[6]; // maximum 6 output mux signals const uint8_t spics_in; const uint8_t spidqs_out; const uint8_t spicd_out; diff --git a/components/esp_hal_gpspi/spi_hal.c b/components/esp_hal_gpspi/spi_hal.c index 1e653663695..f49feca0e73 100644 --- a/components/esp_hal_gpspi/spi_hal.c +++ b/components/esp_hal_gpspi/spi_hal.c @@ -45,7 +45,7 @@ void spi_hal_deinit(spi_hal_context_t *hal) } } -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED void spi_hal_sct_init(spi_hal_context_t *hal) { spi_ll_conf_state_enable(hal->hw, true); @@ -63,7 +63,7 @@ void spi_hal_sct_deinit(spi_hal_context_t *hal) spi_ll_clear_int_stat(hal->hw); spi_ll_enable_int(hal->hw); //recover trans_done intr } -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED int spi_hal_master_cal_clock(int fapb, int hz, int duty_cycle) { diff --git a/components/esp_hal_gpspi/spi_hal_iram.c b/components/esp_hal_gpspi/spi_hal_iram.c index 5ba8b577fc2..c22351f48de 100644 --- a/components/esp_hal_gpspi/spi_hal_iram.c +++ b/components/esp_hal_gpspi/spi_hal_iram.c @@ -20,7 +20,7 @@ void spi_hal_setup_device(spi_hal_context_t *hal, const spi_hal_dev_config_t *de { //Configure clock settings spi_dev_t *hw = hal->hw; -#if SOC_SPI_AS_CS_SUPPORTED +#if SPI_LL_SUPPORT_CLK_AS_CS spi_ll_master_set_cksel(hw, dev->cs_pin_id, dev->as_cs); #endif spi_ll_master_set_pos_cs(hw, dev->cs_pin_id, dev->positive_cs); @@ -264,7 +264,7 @@ void spi_hal_fetch_result(const spi_hal_context_t *hal) } } -#if SOC_SPI_SCT_SUPPORTED +#ifdef SOC_SPI_SCT_SUPPORTED /*------------------------------------------------------------------------------ * Segmented-Configure-Transfer *----------------------------------------------------------------------------*/ @@ -273,12 +273,12 @@ void spi_hal_sct_set_conf_bits_len(spi_hal_context_t *hal, uint32_t conf_len) spi_ll_set_conf_phase_bits_len(hal->hw, conf_len); } -void spi_hal_sct_init_conf_buffer(spi_hal_context_t *hal, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +void spi_hal_sct_init_conf_buffer(spi_hal_context_t *hal, uint32_t *conf_buffer) { spi_ll_init_conf_buffer(hal->hw, conf_buffer); } -void spi_hal_sct_format_conf_buffer(spi_hal_context_t *hal, const spi_hal_seg_config_t *config, const spi_hal_dev_config_t *dev, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX]) +void spi_hal_sct_format_conf_buffer(spi_hal_context_t *hal, const spi_hal_seg_config_t *config, const spi_hal_dev_config_t *dev, uint32_t *conf_buffer) { spi_ll_format_line_mode_conf_buff(hal->hw, hal->trans_config.line_mode, conf_buffer); spi_ll_format_prep_phase_conf_buffer(hal->hw, config->cs_setup, conf_buffer); @@ -294,4 +294,4 @@ void spi_hal_sct_format_conf_buffer(spi_hal_context_t *hal, const spi_hal_seg_co #endif } -#endif //#if SOC_SPI_SCT_SUPPORTED +#endif //#ifdef SOC_SPI_SCT_SUPPORTED diff --git a/components/esp_hal_mspi/spi_flash_hal_common.inc b/components/esp_hal_mspi/spi_flash_hal_common.inc index 81f2c229193..8a5931adfc1 100644 --- a/components/esp_hal_mspi/spi_flash_hal_common.inc +++ b/components/esp_hal_mspi/spi_flash_hal_common.inc @@ -85,8 +85,6 @@ esp_err_t spi_flash_hal_configure_host_io_mode( esp_flash_io_mode_t io_mode) { spi_dev_t *dev = get_spi_dev(host); - int host_id = spi_flash_ll_hw_get_id(dev); - uint32_t extra_bits = io_mode & 0xFFFF0000; io_mode = io_mode & 0xFFFF; @@ -98,12 +96,12 @@ esp_err_t spi_flash_hal_configure_host_io_mode( */ bool conf_required = ((extra_bits & SPI_FLASH_CONFIG_CONF_BITS) != 0); - if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) && io_mode > SPI_FLASH_FASTRD) { + if ((SOC_SPI_MAX_BITWIDTH(spi_flash_ll_hw_get_id(dev)) < 2) && io_mode > SPI_FLASH_FASTRD) { return ESP_ERR_NOT_SUPPORTED; } #ifndef GPSPI_BUILD -#if SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT +#if SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT // The CONTROL_DUMMY_OUTPUT feature is used to control M7-M0 bits. spi_flash_ll_set_dummy_out(dev, (conf_required ? 1 : 0), 1); #else diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 10a38fd5a21..e1b74b5a203 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -503,27 +503,11 @@ config SOC_RTCIO_WAKE_SUPPORTED bool default y -config SOC_SPI_HD_BOTH_INOUT_SUPPORTED - bool - default y - -config SOC_SPI_AS_CS_SUPPORTED - bool - default y - config SOC_SPI_PERIPH_NUM int default 3 -config SOC_SPI_DMA_CHAN_NUM - int - default 2 - -config SOC_SPI_MAX_CS_NUM - int - default 3 - -config SOC_SPI_SUPPORT_CLK_APB +config SOC_SPI_HD_BOTH_INOUT_SUPPORTED bool default y @@ -531,10 +515,6 @@ config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_MAX_PRE_DIVIDER - int - default 8192 - config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED bool default y diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 1d93174473d..c01308ab5d0 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -254,18 +254,12 @@ #define SOC_RTCIO_WAKE_SUPPORTED 1 /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode -#define SOC_SPI_AS_CS_SUPPORTED 1 //Support to toggle the CS while the clock toggles #define SOC_SPI_PERIPH_NUM 3 -#define SOC_SPI_DMA_CHAN_NUM 2 - #define SOC_SPI_PERIPH_CS_NUM(i) 3 -#define SOC_SPI_MAX_CS_NUM 3 - -#define SOC_SPI_SUPPORT_CLK_APB 1 +#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 -#define SOC_SPI_MAX_PRE_DIVIDER 8192 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: DIO, DOUT, QIO, or QOUT // Although ESP32 doesn't has memspi, but keep consistent with following chips.(This means SPI0/1) #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 @@ -273,9 +267,6 @@ #define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 -// Peripheral supports DIO, DOUT, QIO, or QOUT -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;}) - /*-------------------------- LP_TIMER CAPS ----------------------------------*/ #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 49d0c5864cf..b5a4c060fa9 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -443,70 +443,14 @@ config SOC_SPI_PERIPH_NUM int default 2 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_SUPPORT_CLK_PLL_F40M - bool - default y - -config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT - bool - default y - -config SOC_SPI_SCT_SUPPORTED - bool - default y - -config SOC_SPI_SCT_REG_NUM - int - default 14 - -config SOC_SPI_SCT_BUFFER_NUM_MAX - bool - default y - -config SOC_SPI_SCT_CONF_BITLEN_MAX - hex - default 0x3FFFA - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y @@ -535,6 +479,14 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y +config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT + bool + default y + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + config SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED bool default y diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index dee927e09b2..b463d53f70d 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -211,35 +211,13 @@ #define SOC_SHA_SUPPORT_SHA256 (1) /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 2 -#define SOC_SPI_PERIPH_CS_NUM(i) 6 -#define SOC_SPI_MAX_CS_NUM 6 +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 - -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 -#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 -#define SOC_SPI_SUPPORT_CLK_PLL_F40M 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -// Peripheral supports output given level during its "dummy phase" -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 - -#define SOC_SPI_SCT_SUPPORTED 1 -#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer -#define SOC_SPI_SCT_REG_NUM 14 -#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs -#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg - -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4 +#define SOC_SPI_SCT_SUPPORTED(host_id) ((host_id) == 1) /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) @@ -250,6 +228,9 @@ #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) +// Peripheral supports output given level during its "dummy phase" +#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1 +#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index bf4bcbb04eb..4109352e9e2 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -631,70 +631,14 @@ config SOC_SPI_PERIPH_NUM int default 2 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y -config SOC_SPI_SUPPORT_CLK_APB - bool - default y - -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT - bool - default y - -config SOC_SPI_SCT_SUPPORTED - bool - default y - -config SOC_SPI_SCT_REG_NUM - int - default 14 - -config SOC_SPI_SCT_BUFFER_NUM_MAX - bool - default y - -config SOC_SPI_SCT_CONF_BITLEN_MAX - hex - default 0x3FFFA - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y @@ -727,6 +671,14 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y +config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT + bool + default y + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED bool default y diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 8ad7c540dca..a396dc14ce9 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -286,35 +286,12 @@ #define SOC_SHA_SUPPORT_SHA256 (1) /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 2 -#define SOC_SPI_PERIPH_CS_NUM(i) 6 -#define SOC_SPI_MAX_CS_NUM 6 - -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 - -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -#define SOC_SPI_SUPPORT_CLK_APB 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -// Peripheral supports output given level during its "dummy phase" -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 - -#define SOC_SPI_SCT_SUPPORTED 1 -#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer -#define SOC_SPI_SCT_REG_NUM 14 -#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs -#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg - -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4 +#define SOC_SPI_SCT_SUPPORTED(host_id) ((host_id) == 1) /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) @@ -326,6 +303,9 @@ #define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) +// Peripheral supports output given level during its "dummy phase" +#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1 +#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1 diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 28a471b42b8..28dd83f9a3c 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -983,30 +983,10 @@ config SOC_SPI_PERIPH_NUM int default 2 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y @@ -1015,26 +995,6 @@ config SOC_SPI_SUPPORT_SLEEP_RETENTION bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_SUPPORT_CLK_PLL_F160M - bool - default y - -config SOC_SPI_SUPPORT_CLK_RC_FAST - bool - default y - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_SPIRAM_XIP_SUPPORTED bool default y @@ -1091,6 +1051,10 @@ config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY bool default y +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index a7eea9195fc..72907e646d9 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -406,27 +406,12 @@ #define SOC_ECDSA_SUPPORT_CURVE_SPECIFIC_KEY_PURPOSES (1) /*!< Support individual key purposes for different ECDSA curves (P192, P256, P384) */ /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 2 -#define SOC_SPI_PERIPH_CS_NUM(i) 6 -#define SOC_SPI_MAX_CS_NUM 6 -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 - -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 #define SOC_SPI_SUPPORT_SLEEP_RETENTION 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 -#define SOC_SPI_SUPPORT_CLK_PLL_F160M 1 -#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4 /*-------------------------- SPIRAM CAPS ----------------------------------------*/ #define SOC_SPIRAM_XIP_SUPPORTED 1 @@ -446,6 +431,7 @@ #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) +#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index c683e8f1014..7643be75b99 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -847,30 +847,10 @@ config SOC_SPI_PERIPH_NUM int default 2 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y @@ -879,42 +859,6 @@ config SOC_SPI_SUPPORT_SLEEP_RETENTION bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_SUPPORT_CLK_PLL_F80M - bool - default y - -config SOC_SPI_SUPPORT_CLK_RC_FAST - bool - default y - -config SOC_SPI_SCT_SUPPORTED - bool - default y - -config SOC_SPI_SCT_REG_NUM - int - default 14 - -config SOC_SPI_SCT_BUFFER_NUM_MAX - bool - default y - -config SOC_SPI_SCT_CONF_BITLEN_MAX - hex - default 0x3FFFA - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y @@ -943,6 +887,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 9b096b441ac..ae1d3b4085e 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -359,34 +359,13 @@ #define SOC_SHA_SUPPORT_SHA256 (1) /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 2 -#define SOC_SPI_PERIPH_CS_NUM(i) 6 -#define SOC_SPI_MAX_CS_NUM 6 - -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 - -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 #define SOC_SPI_SUPPORT_SLEEP_RETENTION 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 -#define SOC_SPI_SUPPORT_CLK_PLL_F80M 1 -#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -#define SOC_SPI_SCT_SUPPORTED 1 -#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer -#define SOC_SPI_SCT_REG_NUM 14 -#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs -#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg - -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4 +#define SOC_SPI_SCT_SUPPORTED(host_id) ((host_id) == 1) /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) @@ -397,6 +376,7 @@ #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) +#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index eef3647bb2e..1e496ece321 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -739,14 +739,6 @@ config SOC_SPI_PERIPH_NUM int default 2 -config SOC_SPI_MAX_CS_NUM - int - default 6 - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 @@ -759,22 +751,6 @@ config SOC_SPI_SUPPORT_SLEEP_RETENTION bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_SUPPORT_CLK_PLL - bool - default y - -config SOC_SPI_SUPPORT_CLK_RC_FAST - bool - default y - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - config SOC_SPIRAM_XIP_SUPPORTED bool default y @@ -823,6 +799,10 @@ config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY bool default y +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 2ea40ca685e..f6ca56ea5d4 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -313,20 +313,10 @@ /*-------------------------- SPI CAPS ----------------------------------------*/ #define SOC_SPI_PERIPH_NUM 2 #define SOC_SPI_PERIPH_CS_NUM(i) 6 -#define SOC_SPI_MAX_CS_NUM 6 -#define SOC_SPI_MAX_PRE_DIVIDER 16 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 - #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 #define SOC_SPI_SUPPORT_SLEEP_RETENTION 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 -#define SOC_SPI_SUPPORT_CLK_PLL 1 -#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) -#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4 /*-------------------------- SPIRAM CAPS ----------------------------------------*/ #define SOC_SPIRAM_XIP_SUPPORTED 1 @@ -344,6 +334,7 @@ #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) +#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 9cb5ceed035..35b7fca386e 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -847,30 +847,10 @@ config SOC_SPI_PERIPH_NUM int default 2 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y @@ -879,42 +859,6 @@ config SOC_SPI_SUPPORT_SLEEP_RETENTION bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_SUPPORT_CLK_PLL_F48M - bool - default y - -config SOC_SPI_SUPPORT_CLK_RC_FAST - bool - default y - -config SOC_SPI_SCT_SUPPORTED - bool - default y - -config SOC_SPI_SCT_REG_NUM - int - default 14 - -config SOC_SPI_SCT_BUFFER_NUM_MAX - bool - default y - -config SOC_SPI_SCT_CONF_BITLEN_MAX - hex - default 0x3FFFA - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y @@ -943,6 +887,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index c1d3f5c8ada..9f20f05507a 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -371,34 +371,13 @@ #define SOC_SHA_SUPPORT_SHA256 (1) /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 2 -#define SOC_SPI_PERIPH_CS_NUM(i) 6 -#define SOC_SPI_MAX_CS_NUM 6 - -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 - -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 #define SOC_SPI_SUPPORT_SLEEP_RETENTION 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 -#define SOC_SPI_SUPPORT_CLK_PLL_F48M 1 -#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -#define SOC_SPI_SCT_SUPPORTED 1 -#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer -#define SOC_SPI_SCT_REG_NUM 14 -#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs -#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg - -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4 +#define SOC_SPI_SCT_SUPPORTED(host_id) ((host_id) == 1) /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) @@ -409,6 +388,7 @@ #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) +#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1 diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index b0703d1b5dd..e774e2decfb 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -667,66 +667,14 @@ config SOC_SPI_PERIPH_NUM int default 2 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_SUPPORT_CLK_PLL_F48M - bool - default y - -config SOC_SPI_SUPPORT_CLK_RC_FAST - bool - default y - -config SOC_SPI_SCT_SUPPORTED - bool - default y - -config SOC_SPI_SCT_REG_NUM - int - default 14 - -config SOC_SPI_SCT_BUFFER_NUM_MAX - bool - default y - -config SOC_SPI_SCT_CONF_BITLEN_MAX - hex - default 0x3FFFA - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y @@ -755,6 +703,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32h21/include/soc/clk_tree_defs.h b/components/soc/esp32h21/include/soc/clk_tree_defs.h index d4d3433c382..609c175b52e 100644 --- a/components/soc/esp32h21/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h @@ -359,11 +359,7 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of SPI */ -#if SOC_CLK_TREE_SUPPORTED #define SOC_SPI_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL} -#else -#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL} -#endif /** * @brief Type of SPI clock source. diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 894385d1320..60cee00567c 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -350,32 +350,12 @@ #define SOC_ECC_CONSTANT_TIME_POINT_MUL 1 /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 2 -#define SOC_SPI_PERIPH_CS_NUM(i) 6 -#define SOC_SPI_MAX_CS_NUM 6 +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 -#if SOC_CLK_TREE_SUPPORTED //TODO: [ESP32H21] IDF-11521 -#define SOC_SPI_SUPPORT_CLK_PLL_F48M 1 -#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 -#endif - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -#define SOC_SPI_SCT_SUPPORTED 1 -#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer -#define SOC_SPI_SCT_REG_NUM 14 -#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs -#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg - -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4 +#define SOC_SPI_SCT_SUPPORTED(host_id) ((host_id) == 1) /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) @@ -385,6 +365,7 @@ #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) +#define SOC_MEMSPI_IS_INDEPENDENT 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 72fa57bb3f4..b58dfd51401 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -663,50 +663,14 @@ config SOC_SPI_PERIPH_NUM int default 3 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_SUPPORT_CLK_RC_FAST - bool - default y - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y @@ -735,6 +699,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 7eebfb1c3a3..81faf52d986 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -368,25 +368,11 @@ #define SOC_ECC_CONSTANT_TIME_POINT_MUL 1 /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 3 -#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) -#define SOC_SPI_MAX_CS_NUM 6 - -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_PERIPH_NUM 3 +#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 -#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_SPI_MAX_BITWIDTH(host_id) (4) // Supported line mode: SPI2: 1, 2, 4 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) @@ -396,6 +382,7 @@ #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) +#define SOC_MEMSPI_IS_INDEPENDENT 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 47100c26ade..f8a53d8d0a2 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1339,10 +1339,6 @@ config SOC_SPI_PERIPH_NUM int default 3 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 @@ -1355,42 +1351,10 @@ config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - config SOC_SPI_SUPPORT_OCT bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_SUPPORT_CLK_RC_FAST - bool - default y - -config SOC_MSPI_HAS_INDEPENT_IOMUX - bool - default y - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - config SOC_LP_SPI_MAXIMUM_BUFFER_SIZE int default 64 @@ -1443,7 +1407,15 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR bool default y -config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT +config SOC_MSPI_HAS_INDEPENT_IOMUX + bool + default y + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index dd4ce4b96bb..8f59501a53a 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -515,27 +515,13 @@ #define SOC_ECDSA_USES_MPI (1) /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 3 -#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) -#define SOC_SPI_MAX_CS_NUM 6 -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 - +#define SOC_SPI_PERIPH_NUM 3 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_SLEEP_RETENTION 1 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 #define SOC_SPI_SUPPORT_OCT 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 -#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -#define SOC_MSPI_HAS_INDEPENT_IOMUX 1 -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 +#define SOC_SPI_MAX_BITWIDTH(host_id) ((host_id == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8 /*-------------------------- LP SPI CAPS ----------------------------------------*/ #define SOC_LP_SPI_MAXIMUM_BUFFER_SIZE 64 @@ -557,7 +543,9 @@ #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1) +#define SOC_MSPI_HAS_INDEPENT_IOMUX 1 +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 448cbb008e4..3e98054eac5 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -547,55 +547,19 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT bool default y -config SOC_SPI_HD_BOTH_INOUT_SUPPORTED - bool - default y - config SOC_SPI_PERIPH_NUM int default 3 -config SOC_SPI_DMA_CHAN_NUM - int - default 3 - -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 72 -config SOC_SPI_MAX_PRE_DIVIDER - int - default 8192 - -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CLK_APB - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y -config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT +config SOC_SPI_HD_BOTH_INOUT_SUPPORTED bool default y @@ -603,22 +567,10 @@ config SOC_SPI_SUPPORT_OCT bool default y -config SOC_SPI_SCT_SUPPORTED +config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT bool default y -config SOC_SPI_SCT_REG_NUM - int - default 27 - -config SOC_SPI_SCT_BUFFER_NUM_MAX - bool - default y - -config SOC_SPI_SCT_CONF_BITLEN_MAX - hex - default 0x7FFFFD - config SOC_MEMSPI_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index d823db7386b..357ff3abee0 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -250,39 +250,19 @@ #define SOC_LP_IO_CLOCK_IS_INDEPENDENT 1 /*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode #define SOC_SPI_PERIPH_NUM 3 -#define SOC_SPI_DMA_CHAN_NUM 3 #define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) -#define SOC_SPI_MAX_CS_NUM 6 - #define SOC_SPI_MAXIMUM_BUFFER_SIZE 72 -#define SOC_SPI_MAX_PRE_DIVIDER 8192 - -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 -#define SOC_SPI_SUPPORT_CLK_APB 1 /// The SPI Slave half duplex mode has been updated greatly in ESP32-S2 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// VSPI (SPI3) only support 1-bit mode -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2) +#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode +#define SOC_SPI_SUPPORT_OCT 1 +#define SOC_SPI_MAX_BITWIDTH(host_id) ((host_id == 2) ? 1 : 8) // Supported line mode: SPI3: 1, SPI1/2: 1, 2, 4, 8 +#define SOC_SPI_SCT_SUPPORTED(host_id) ((host_id) == 1) // Peripheral supports output given level during its "dummy phase" // Only SPI1 supports this feature -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 - -#define SOC_SPI_SUPPORT_OCT 1 - -#define SOC_SPI_SCT_SUPPORTED 1 -#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) (((PERIPH_NUM==1) || (PERIPH_NUM==2)) ? 1 : 0) //Support Segmented-Configure-Transfer -#define SOC_SPI_SCT_REG_NUM 27 -#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 27-word-regs -#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x7FFFFD //23 bit wide reg - +#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1 #define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 9e5cc2492d7..2f44fa1cc53 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -675,43 +675,19 @@ config SOC_SPI_PERIPH_NUM int default 3 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - config SOC_SPI_SUPPORT_SLAVE_HD_VER2 bool default y -config SOC_SPI_SUPPORT_CLK_APB +config SOC_SPI_SUPPORT_OCT bool default y -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT +config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT bool default y @@ -719,30 +695,6 @@ config SOC_MEMSPI_IS_INDEPENDENT bool default y -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - -config SOC_SPI_SUPPORT_OCT - bool - default y - -config SOC_SPI_SCT_SUPPORTED - bool - default y - -config SOC_SPI_SCT_REG_NUM - int - default 14 - -config SOC_SPI_SCT_BUFFER_NUM_MAX - bool - default y - -config SOC_SPI_SCT_CONF_BITLEN_MAX - hex - default 0x3FFFA - config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED bool default y diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index e9a25cac404..75ea764374b 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -287,31 +287,15 @@ /*-------------------------- SPI CAPS ----------------------------------------*/ #define SOC_SPI_PERIPH_NUM 3 #define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) -#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -#define SOC_SPI_SUPPORT_CLK_APB 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) +#define SOC_SPI_SUPPORT_OCT 1 +#define SOC_SPI_MAX_BITWIDTH(host_id) ((host_id == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8 +#define SOC_SPI_SCT_SUPPORTED(host_id) ((host_id) == 1) // Peripheral supports output given level during its "dummy phase" -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 -#define SOC_SPI_SUPPORT_OCT 1 - -#define SOC_SPI_SCT_SUPPORTED 1 -#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer -#define SOC_SPI_SCT_REG_NUM 14 -#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs -#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg - +#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1 +#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 8925fc733ad..ff21d41b212 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -215,10 +215,6 @@ config SOC_SPI_PERIPH_NUM int default 3 -config SOC_SPI_MAX_CS_NUM - int - default 6 - config SOC_SPI_MAXIMUM_BUFFER_SIZE int default 64 @@ -231,7 +227,7 @@ config SOC_MEMSPI_IS_INDEPENDENT bool default y -config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT +config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index 27b2b046596..a1493b1337e 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -181,18 +181,13 @@ // TODO: [ESP32S31] IDF-14734 #define SOC_SPI_PERIPH_NUM 3 #define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) -#define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 +#define SOC_SPI_MAX_BITWIDTH(host_id) ((host_id == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8 -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -#define SOC_MSPI_HAS_INDEPENT_IOMUX 1 -#define SOC_MEMSPI_IS_INDEPENDENT 1 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ - -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT (1) +#define SOC_MSPI_HAS_INDEPENT_IOMUX 1 +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index 2ec9c1abaa9..228a65eff31 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -273,12 +273,9 @@ static uint32_t init_gpspi_clock(esp_flash_t *chip, const esp_flash_spi_device_c uint32_t clk_src_freq = 0; spi_clock_source_t clk_src = config->clock_source ? config->clock_source : SPI_CLK_SRC_DEFAULT; -#if SOC_SPI_SUPPORT_CLK_RC_FAST - if (config->clock_source == SPI_CLK_SRC_RC_FAST) { + if ((soc_module_clk_t)clk_src == SOC_MOD_CLK_RC_FAST) { periph_rtc_dig_clk8m_enable(); } -#endif - esp_clk_tree_enable_src(clk_src, true); esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq); @@ -346,12 +343,10 @@ static void deinit_gpspi_clock(esp_flash_t *chip) // Disable the clock source esp_clk_tree_enable_src(chip->clock_source, false); -#if SOC_SPI_SUPPORT_CLK_RC_FAST // Disable RC_FAST clock if it was used - if (chip->clock_source == SPI_CLK_SRC_RC_FAST) { + if ((soc_module_clk_t)chip->clock_source == SOC_MOD_CLK_RC_FAST) { periph_rtc_dig_clk8m_disable(); } -#endif #endif // !CONFIG_IDF_TARGET_ESP32 } diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c index ea1eace63c1..fb554291d82 100644 --- a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c +++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c @@ -614,8 +614,7 @@ void test_permutations_part(const flashtest_config_t* config, esp_partition_t* p //the io mode will switch frequently. esp_flash_io_mode_t io_mode = SPI_FLASH_READ_MODE_MIN; while (io_mode != SPI_FLASH_QIO + 1) { - if (io_mode > SPI_FLASH_FASTRD && - !SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(config->host_id)) { + if (io_mode > SPI_FLASH_FASTRD && (SOC_SPI_MAX_BITWIDTH(config->host_id) < 2)) { io_mode++; continue; }