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Merge branch 'fix/esp32c5_usj_console_stuck' into 'master'

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fix(esp32c5): Do not disable UART0 sclk when USB Serial/JTAG is primary console

Closes IDFGH-17050

See merge request espressif/esp-idf!45920
This commit is contained in:
Peter Dragun
2026-05-25 16:03:26 +08:00
parent 0b0c85cb3b 69d8b42adf
commit a2d6680477
4 changed files with 26 additions and 8 deletions
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4
components/esp_driver_usb_serial_jtag/test_apps/.build-test-rules.yml
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@@ -7,7 +7,7 @@ components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag:
temporary: true
reason: p4 rev3 migration # TODO: IDF-14364
disable_test:
- if: IDF_TARGET in ["esp32c5", "esp32h4", "esp32h21", "esp32s31"]
- if: IDF_TARGET in ["esp32h4", "esp32h21", "esp32s31"]
temporary: true
reason: No runners.
depends_components:
@@ -25,7 +25,7 @@ components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs:
temporary: true
reason: p4 rev3 migration # TODO: IDF-14364
disable_test:
- if: IDF_TARGET in ["esp32c5", "esp32h4", "esp32h21", "esp32s31"]
- if: IDF_TARGET in ["esp32h4", "esp32h21", "esp32s31"]
temporary: true
reason: No runners.
depends_components:

10
components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag/pytest_usb_serial_jtag.py
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@@ -1,4 +1,4 @@
# SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import pytest
from pytest_embedded import Dut
@@ -13,7 +13,9 @@ from pytest_embedded_idf.utils import idf_parametrize
],
indirect=True,
)
@idf_parametrize('target', ['esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c61', 'esp32p4'], indirect=['target'])
@idf_parametrize(
'target', ['esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c61', 'esp32p4', 'esp32c5'], indirect=['target']
)
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration')
def test_usb_serial_jtag_dev(dut: Dut) -> None: # type: ignore
dut.expect_exact('Press ENTER to see the list of tests')
@@ -36,7 +38,9 @@ def test_usb_serial_jtag_dev(dut: Dut) -> None: # type: ignore
],
indirect=True,
)
@idf_parametrize('target', ['esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c61', 'esp32p4'], indirect=['target'])
@idf_parametrize(
'target', ['esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c61', 'esp32p4', 'esp32c5'], indirect=['target']
)
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration')
def test_usb_serial_jtag_rom_dev(dut: Dut) -> None: # type: ignore
dut.expect_exact('Press ENTER to see the list of tests')

10
components/esp_driver_usb_serial_jtag/test_apps/usb_serial_jtag_vfs/pytest_usb_serial_jtag_vfs.py
View File

@@ -1,4 +1,4 @@
# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import pytest
from pytest_embedded import Dut
@@ -13,7 +13,9 @@ from pytest_embedded_idf.utils import idf_parametrize
],
indirect=True,
)
@idf_parametrize('target', ['esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c61', 'esp32p4'], indirect=['target'])
@idf_parametrize(
'target', ['esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c61', 'esp32p4', 'esp32c5'], indirect=['target']
)
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration')
def test_usj_vfs_select(dut: Dut) -> None:
test_message = 'test123456789!@#%^&*'
@@ -34,7 +36,9 @@ def test_usj_vfs_select(dut: Dut) -> None:
],
indirect=True,
)
@idf_parametrize('target', ['esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c61', 'esp32p4'], indirect=['target'])
@idf_parametrize(
'target', ['esp32s3', 'esp32c3', 'esp32c6', 'esp32h2', 'esp32c61', 'esp32p4', 'esp32c5'], indirect=['target']
)
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration')
def test_usj_vfs_read_return(dut: Dut) -> None:
test_message = '!(@*#&(!*@&#((SDasdkjhad\nce'

10
components/esp_system/port/soc/esp32c5/clk.c
View File

@@ -253,5 +253,15 @@ __attribute__((weak)) void esp_perip_clk_init(void)
clk_gate_config.disable_pvt_clk = true;
#endif
#if defined(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG) && CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
/* ESP32-C5 rev <= 1.0: Do not disable UART0 sclk when USB Serial/JTAG is primary console.
* Disabling it would cause the chip to end in infinite loop on reset (workaround for rom code issue).
* See: IDFGH-17050
*/
if (efuse_hal_chip_revision() <= 100) {
clk_gate_config.disable_uart0_clk = false;
}
#endif
periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config);
}