Merge branch 'fix/update_trng_workflow_for_esp32s31_v6.1' into 'release/v6.1'

fix(rng): fix esp_random failed beacuse do not enable RNG clock(v6.1)

See merge request espressif/esp-idf!52317

components/hal/esp32s31/include/hal/lp_clkrst_ll.h

@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/rng_ll.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * ESP32-S31 has no LP_CLKRST RNG clock gate. Reuse this hook so
+ * hw_random.c can enable the full RNG module without chip-specific ifdefs.
+ */
+static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
+{
+    if (en) {
+        rng_ll_enable();
+    } else {
+        rng_ll_disable();
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32s31/include/hal/rng_ll.h

@@ -6,9 +6,12 @@
 
 #pragma once
 
+#include <stdbool.h>
 #include <stdint.h>
 #include "soc/soc.h"
 #include "soc/trng_reg.h"
+#include "soc/trng_struct.h"
+#include "soc/lp_peri_clkrst_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -19,6 +22,80 @@ static inline uint32_t rng_ll_read_data(void)
     return REG_READ(TRNG_CRC_SYNC_DATA_REG);
 }
 
+/**
+ * @brief Enable LP RNG bus clock
+ */
+static inline void rng_ll_enable_bus_clock(bool enable)
+{
+    LP_PERI_CLKRST.rng_ctrl.lp_rng_clk_en = enable;
+}
+
+/**
+ * @brief Reset LP RNG bus clock
+ */
+static inline void rng_ll_reset(void)
+{
+    LP_PERI_CLKRST.rng_ctrl.lp_rng_rst_en = 1;
+    LP_PERI_CLKRST.rng_ctrl.lp_rng_rst_en = 0;
+}
+
+/**
+ * @brief Enable or disable RNG module clock
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void rng_ll_enable_clock(bool enable)
+{
+    LP_TRNG.date.clk_en = enable;
+}
+
+/**
+ * @brief Enable or disable RNG sampling
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void rng_ll_enable_sample(bool enable)
+{
+    LP_TRNG.conf.sample_enable = enable;
+}
+
+/**
+ * @brief Enable or disable CRC RNG source
+ *
+ * @param enable true to enable CRC RNG, false to disable
+ */
+static inline void rng_ll_enable_noise_crc(bool enable)
+{
+    LP_TRNG.conf.noise_crc_en = enable;
+}
+
+/**
+ * @brief Enable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_enable(void)
+{
+    rng_ll_enable_bus_clock(true);
+    rng_ll_enable_clock(true);
+    rng_ll_reset();
+    rng_ll_enable_sample(true);
+    rng_ll_enable_noise_crc(true);
+}
+
+/**
+ * @brief Disable RNG module
+ *
+ * TODO: unify in rng_hal.c
+ */
+static inline void rng_ll_disable(void)
+{
+    rng_ll_enable_noise_crc(false);
+    rng_ll_enable_sample(false);
+    rng_ll_enable_clock(false);
+    rng_ll_enable_bus_clock(false);
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s31/include/hal/trng_ll.h

@@ -80,8 +80,8 @@ static inline uint32_t trng_ll_read_data(void)
 static inline void trng_ll_enable(void)
 {
     trng_ll_enable_bus_clock(true);
-    trng_ll_reset();
     trng_ll_enable_clock(true);
+    trng_ll_reset();
     trng_ll_enable_sample(true);
     trng_ll_enable_noise_crc(true);
 }
@@ -93,8 +93,8 @@ static inline void trng_ll_enable(void)
  */
 static inline void trng_ll_disable(void)
 {
-    trng_ll_enable_sample(false);
     trng_ll_enable_noise_crc(false);
+    trng_ll_enable_sample(false);
     trng_ll_enable_clock(false);
     trng_ll_enable_bus_clock(false);
 }

components/soc/esp32s31/include/soc/Kconfig.soc_caps.in

@@ -1391,6 +1391,10 @@ config SOC_MODEM_CLOCK_WIFI_BB_80X1_AS_APB
     bool
     default y
 
+config SOC_RNG_CLOCK_IS_INDEPENDENT
+    bool
+    default y
+
 config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
     bool
     default y

components/soc/esp32s31/include/soc/soc_caps.h

@@ -519,6 +519,7 @@
 #define SOC_MODEM_APB_CLOCK_IS_INDEPENDENT        (1)
 #define SOC_MODEM_CLOCK_SOC_PLL_SOURCE_CG_SUPPORTED (1)
 #define SOC_MODEM_CLOCK_WIFI_BB_80X1_AS_APB       (1)
+#define SOC_RNG_CLOCK_IS_INDEPENDENT              (1)
 
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)