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feat(dma2d,ppa): Support flash encryption for DMA2D and PPA
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -245,23 +245,23 @@ static inline void dma2d_ll_rx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t
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* @brief Set 2D-DMA RX channel maximum burst reading data length in bytes
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*/
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__attribute__((always_inline))
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static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t channel, dma2d_data_burst_length_t length)
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static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t channel, uint32_t length)
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{
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uint32_t sel;
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switch (length) {
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case DMA2D_DATA_BURST_LENGTH_8:
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case 8:
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sel = 0;
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break;
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case DMA2D_DATA_BURST_LENGTH_16:
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case 16:
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sel = 1;
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break;
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case DMA2D_DATA_BURST_LENGTH_32:
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case 32:
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sel = 2;
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break;
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case DMA2D_DATA_BURST_LENGTH_64:
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case 64:
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sel = 3;
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break;
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case DMA2D_DATA_BURST_LENGTH_128:
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case 128:
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sel = 4;
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break;
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default:
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@@ -761,23 +761,23 @@ static inline void dma2d_ll_tx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t
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* @brief Set 2D-DMA TX channel maximum burst reading data length in bytes
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*/
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__attribute__((always_inline))
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static inline void dma2d_ll_tx_set_data_burst_length(dma2d_dev_t *dev, uint32_t channel, dma2d_data_burst_length_t length)
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static inline void dma2d_ll_tx_set_data_burst_length(dma2d_dev_t *dev, uint32_t channel, uint32_t length)
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{
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uint32_t sel;
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switch (length) {
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case DMA2D_DATA_BURST_LENGTH_8:
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case 8:
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sel = 0;
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break;
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case DMA2D_DATA_BURST_LENGTH_16:
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case 16:
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sel = 1;
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break;
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case DMA2D_DATA_BURST_LENGTH_32:
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case 32:
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sel = 2;
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break;
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case DMA2D_DATA_BURST_LENGTH_64:
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case 64:
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sel = 3;
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break;
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case DMA2D_DATA_BURST_LENGTH_128:
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case 128:
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sel = 4;
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break;
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default:
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@@ -58,7 +58,6 @@
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#define GDMA_LL_AHB_DESC_ALIGNMENT 4
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#define GDMA_LL_AXI_DESC_ALIGNMENT 8
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#define GDMA_LL_MAX_BURST_SIZE_PSRAM 128 // PSRAM controller doesn't support burst access with size > 128 bytes
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#define GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT 16 // The alignment of the memory and size when DMA accesses encrypted memory
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
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