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feat(adc): add always inline for adc ll functions called by bootloader

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gaoxu
2025-12-01 15:31:44 +08:00
committed by Gao Xu
parent 94679d0b0e
commit 9126d8c485
5 changed files with 55 additions and 0 deletions
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components/hal/esp32c6/include/hal/adc_ll.h
+11
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@@ -141,6 +141,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
*
* @param div Division factor.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_set_clk_div(uint32_t div)
{
/* ADC clock divided from digital controller clock clk */
@@ -190,6 +191,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
* @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 8.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{
APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -205,6 +207,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
* @param pattern_index Items index. Range: 0 ~ 7.
* @param pattern Stored conversion rules.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{
uint32_t tab;
@@ -277,6 +280,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
* @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
* @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
{
APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -285,6 +289,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
/**
* Enable digital controller timer to trigger the measurement.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_trigger_enable(void)
{
APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -293,6 +298,7 @@ static inline void adc_ll_digi_trigger_enable(void)
/**
* Disable digital controller timer to trigger the measurement.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_trigger_disable(void)
{
APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -306,6 +312,7 @@ static inline void adc_ll_digi_trigger_disable(void)
* @param div_b Division factor. Range: 1 ~ 63.
* @param div_a Division factor. Range: 0 ~ 63.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -318,6 +325,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
*
* @param clk_src clock source for ADC digital controller.
*/
__attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
@@ -572,6 +580,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
* @brief Enable the ADC clock
* @param enable true to enable, false to disable
*/
__attribute__((always_inline))
static inline void adc_ll_enable_bus_clock(bool enable)
{
PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -581,6 +590,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
* @brief Enable the ADC function clock
* @param enable true to enable, false to disable
*/
__attribute__((always_inline))
static inline void adc_ll_enable_func_clock(bool enable)
{
PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -589,6 +599,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
/**
* @brief Reset ADC module
*/
__attribute__((always_inline))
static inline void adc_ll_reset_register(void)
{
PCR.saradc_conf.saradc_rst_en = 1;