diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h
index aebb2557cff..0483dc9d8b2 100644
--- a/components/hal/esp32c5/include/hal/adc_ll.h
+++ b/components/hal/esp32c5/include/hal/adc_ll.h
@@ -142,6 +142,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -191,6 +192,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -206,6 +208,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -278,6 +281,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -286,6 +290,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -294,6 +299,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -307,6 +313,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -319,6 +326,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -573,6 +581,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC APB clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -582,6 +591,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -590,6 +600,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h
index 185fe69af49..7fe369d11f7 100644
--- a/components/hal/esp32c6/include/hal/adc_ll.h
+++ b/components/hal/esp32c6/include/hal/adc_ll.h
@@ -141,6 +141,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -190,6 +191,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -205,6 +207,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -277,6 +280,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -285,6 +289,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -293,6 +298,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -306,6 +312,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -318,6 +325,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -572,6 +580,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -581,6 +590,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -589,6 +599,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32c61/include/hal/adc_ll.h b/components/hal/esp32c61/include/hal/adc_ll.h
index 9e14aaf3a89..4b1b1addc9b 100644
--- a/components/hal/esp32c61/include/hal/adc_ll.h
+++ b/components/hal/esp32c61/include/hal/adc_ll.h
@@ -142,6 +142,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -191,6 +192,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     ADC.saradc_ctrl.saradc_sar_patt_len = patt_len - 1;
@@ -206,6 +208,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -280,6 +283,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     ADC.saradc_ctrl2.saradc_timer_target = cycle;
@@ -288,6 +292,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     ADC.saradc_ctrl2.saradc_timer_en = 1;
@@ -296,6 +301,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     ADC.saradc_ctrl2.saradc_timer_en = 0;
@@ -309,6 +315,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -321,6 +328,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -575,6 +583,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC APB clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -584,6 +593,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -592,6 +602,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index b0b47b913f5..3e2baaa7abe 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -142,6 +142,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -191,6 +192,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -206,6 +208,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -278,6 +281,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -286,6 +290,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -294,6 +299,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -307,6 +313,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -319,6 +326,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -573,6 +581,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -582,6 +591,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -590,6 +600,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;
diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h
index cf443e69957..f3c7487c1d8 100644
--- a/components/hal/esp32p4/include/hal/adc_ll.h
+++ b/components/hal/esp32p4/include/hal/adc_ll.h
@@ -150,6 +150,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -207,6 +208,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl23, reg_adc_clk_div_num, div_num);
@@ -219,6 +221,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -331,6 +334,7 @@ static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 16.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     if (adc_n == ADC_UNIT_1) {
@@ -350,6 +354,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 11.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -422,6 +427,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     ADC.ctrl2.timer_target = cycle;
@@ -466,6 +472,7 @@ static inline void adc_ll_digi_reset(void)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     ADC.ctrl2.timer_sel = 1;
@@ -475,6 +482,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     ADC.ctrl2.timer_en = 0;
@@ -532,6 +540,7 @@ static inline void _adc_ll_sar2_clock_force_en(bool enable)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void _adc_ll_enable_bus_clock(bool enable)
 {
     HP_SYS_CLKRST.soc_clk_ctrl2.reg_adc_apb_clk_en = enable;
@@ -543,6 +552,7 @@ static inline void _adc_ll_enable_bus_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void _adc_ll_reset_register(void)
 {
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_adc = 1;
@@ -559,6 +569,7 @@ static inline void _adc_ll_reset_register(void)
  * @param adc_n ADC unit.
  * @param manage Set ADC power status.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_power_manage(adc_unit_t adc_n, adc_ll_power_t manage)
 {
     if (adc_n == ADC_UNIT_1) {