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Merge branch 'fix/flash_32bit_addr_v6.1' into 'release/v6.1'

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fix(spi_flash): fix flash 32bit address operation on esp32s31

See merge request espressif/esp-idf!50295
This commit is contained in:
morris
2026-07-03 11:08:45 +08:00
parent dc9fc38bfe 57484d3a2f
commit 897347eb58
2 changed files with 19 additions and 7 deletions
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components/esp_hal_mspi/esp32s31/include/hal/spi_flash_ll.h
+5 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -35,6 +35,7 @@ extern "C" {
}\
dev_id; \
})
#define SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL (1)
// WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (8)
@@ -67,7 +68,8 @@ typedef union {
#define spi_flash_ll_set_dummy(dev, dummy) gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy)
#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) { /* Not supported on gpspi on ESP32-P4*/ }
#define spi_flash_ll_set_extra_address(dev, extra_addr) { /* Not supported on gpspi on ESP32-S31*/ }
#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enale) { /* Not supported on gpspi on ESP32-S31*/ }
#define spi_flash_ll_set_dummy_out(dev, en, lev) gpspi_flash_ll_set_dummy_out((spi_dev_t*)dev, en, lev)
#else
#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev)
@@ -98,6 +100,7 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enale) spimem_flash_ll_wb_mode_enable((spi_mem_dev_t*)dev, wb_mode_enale)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h
+14 -5
View File
@@ -607,10 +607,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
unsigned chip_version = efuse_hal_chip_revision();
if (ESP_CHIP_REV_ABOVE(chip_version, 1)) {
dev->cache_fctrl.cache_usr_addr_4byte = (bitlen == 32) ? 1 : 0;
}
dev->cache_fctrl.cache_usr_addr_4byte = (bitlen == 32) ? 1 : 0;
dev->user1.usr_addr_bitlen = (bitlen - 1);
dev->user.usr_addr = bitlen ? 1 : 0;
}
@@ -623,8 +620,20 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
*/
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.cache_usr_addr_4byte = 0;
// Fixed wb mode to 0x00, the bit length fixed to 8
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr);
dev->rd_status.wb_mode_bitlen = 7; // 8 - 1
}
/**
* Enable extra address for bits M0-M7 in DIO/QIO mode.
*
* @param dev Beginning address of the peripheral registers.
* @param wb_mode_enable true for enabling wb_mode
*/
static inline void spimem_flash_ll_wb_mode_enable(spi_mem_dev_t *dev, bool wb_mode_enable)
{
dev->rd_status.wb_mode_en = wb_mode_enable;
}
/**