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Merge branch 'refactor/clk_tree_acquire_release_api' into 'master'

Browse Source 
refactor(esp_clk_tree): rename esp_clk_tree_enable_src API

See merge request espressif/esp-idf!52736
This commit is contained in:
Chen Chen
2026-09-21 11:09:42 +08:00
parent 6adbabe700 4b85046a4a
commit 88b6548be8
79 changed files with 317 additions and 265 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/app_trace/port/port_uart.c
+2 -2
View File
@@ -227,7 +227,7 @@ static esp_err_t esp_apptrace_uart_init(void *hw_data, const esp_apptrace_config
uint32_t sclk_hz;
esp_clk_tree_src_get_freq_hz(UART_SCLK_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_hz);
/* Enable the default clock source */
esp_clk_tree_enable_src(UART_SCLK_DEFAULT, true);
esp_clk_tree_acquire_src(UART_SCLK_DEFAULT);
/* Initialize UART HAL (sets default 8N1 mode) */
uart_hal_init(&uart_data->hal_ctx, uart_config->uart_num);
@@ -297,7 +297,7 @@ static esp_err_t esp_apptrace_uart_init(void *hw_data, const esp_apptrace_config
err_alloc_msg_buff:
heap_caps_free(uart_data->tx_ring.buffer);
err_init_ring_buff:
esp_clk_tree_enable_src(UART_SCLK_DEFAULT, false);
esp_clk_tree_release_src(UART_SCLK_DEFAULT);
PERIPH_RCC_ATOMIC() {
uart_ll_sclk_disable(uart_data->hal_ctx.dev);
}
components/esp_adc/adc_continuous.c
+2 -2
View File
@@ -324,7 +324,7 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
}
#if !CONFIG_IDF_TARGET_ESP32
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal_digi_ctrlr_cfg.clk_src), true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src((soc_module_clk_t)(handle->hal_digi_ctrlr_cfg.clk_src)));
#endif
adc_hal_digi_init(&handle->hal);
adc_hal_digi_controller_config(&handle->hal, &handle->hal_digi_ctrlr_cfg);
@@ -370,7 +370,7 @@ esp_err_t adc_continuous_stop(adc_continuous_handle_t handle)
adc_hal_digi_deinit();
#if !CONFIG_IDF_TARGET_ESP32
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal_digi_ctrlr_cfg.clk_src), false));
ESP_ERROR_CHECK(esp_clk_tree_release_src((soc_module_clk_t)(handle->hal_digi_ctrlr_cfg.clk_src)));
#endif
if (handle->use_adc2) {
adc_lock_release(ADC_UNIT_2);
components/esp_adc/adc_oneshot.c
+6 -6
View File
@@ -161,7 +161,7 @@ esp_err_t adc_oneshot_new_unit(const adc_oneshot_unit_init_cfg_t *init_config, a
sar_periph_ctrl_adc_oneshot_power_acquire();
} else {
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(unit->hal.clk_src), true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)(unit->hal.clk_src)), err, TAG, "clock source enable failed");
#endif
#if SOC_LIGHT_SLEEP_SUPPORTED || SOC_DEEP_SLEEP_SUPPORTED
esp_sleep_sub_mode_config(ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE, true);
@@ -228,7 +228,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan,
portENTER_CRITICAL(&rtc_spinlock);
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src((soc_module_clk_t)(handle->hal.clk_src)));
#endif
ANALOG_CLOCK_ENABLE();
adc_oneshot_hal_setup(&(handle->hal), chan);
@@ -241,7 +241,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan,
valid = adc_oneshot_hal_convert(&(handle->hal), out_raw);
ANALOG_CLOCK_DISABLE();
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), false));
ESP_ERROR_CHECK(esp_clk_tree_release_src((soc_module_clk_t)(handle->hal.clk_src)));
#endif
portEXIT_CRITICAL(&rtc_spinlock);
@@ -259,7 +259,7 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c
portENTER_CRITICAL_SAFE(&rtc_spinlock);
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src((soc_module_clk_t)(handle->hal.clk_src)));
#endif
ANALOG_CLOCK_ENABLE();
adc_oneshot_hal_setup(&(handle->hal), chan);
@@ -271,7 +271,7 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c
bool valid = adc_oneshot_hal_convert(&(handle->hal), out_raw);
ANALOG_CLOCK_DISABLE();
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), false));
ESP_ERROR_CHECK(esp_clk_tree_release_src((soc_module_clk_t)(handle->hal.clk_src)));
#endif
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
@@ -302,7 +302,7 @@ esp_err_t adc_oneshot_del_unit(adc_oneshot_unit_handle_t handle)
#if SOC_LIGHT_SLEEP_SUPPORTED || SOC_DEEP_SLEEP_SUPPORTED
esp_sleep_sub_mode_config(ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE, false);
#endif
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), false));
ESP_ERROR_CHECK(esp_clk_tree_release_src((soc_module_clk_t)(handle->hal.clk_src)));
}
if (ADC_LL_NEED_APB_PERIPH_CLAIM(handle->unit_id)) {
components/esp_adc/linker.lf
-1
View File
@@ -8,7 +8,6 @@ entries:
archive: libesp_hw_support.a
entries:
if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y:
esp_clk_tree: esp_clk_tree_enable_src (noflash)
if IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32S31 = y:
esp_clk_tree: s_gated_ref_clks (noflash)
components/esp_driver_ana_cmpr/ana_cmpr.c
+3 -3
View File
@@ -146,7 +146,7 @@ static void ana_cmpr_destroy_unit(ana_cmpr_handle_t cmpr)
}
#endif
if (cmpr->clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(cmpr->clk_src, false);
esp_clk_tree_release_src(cmpr->clk_src);
}
free(cmpr);
@@ -330,7 +330,7 @@ esp_err_t ana_cmpr_new_unit(const ana_cmpr_config_t *config, ana_cmpr_handle_t *
// Set clock source (use default if not specified in config)
soc_module_clk_t clk_src = config->clk_src ? config->clk_src : ANA_CMPR_CLK_SRC_DEFAULT;
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(clk_src, true), err, TAG, "enable clock source failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src(clk_src), err, TAG, "enable clock source failed");
#if ANALOG_CMPR_LL_GET(IP_VERSION) > 1
analog_cmpr_ll_set_clk_src(unit_id, clk_src);
// Set clock divider to 1
@@ -343,7 +343,7 @@ esp_err_t ana_cmpr_new_unit(const ana_cmpr_config_t *config, ana_cmpr_handle_t *
ret = io_mux_acquire_clock_source(clk_src);
if (ret != ESP_OK) {
ESP_LOGE(TAG, "clock source conflicts with other IOMUX consumers");
esp_clk_tree_enable_src(clk_src, false);
esp_clk_tree_release_src(clk_src);
goto err;
}
ana_cmpr_hdl->io_mux_acquired = true;
components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c
+1 -1
View File
@@ -144,7 +144,7 @@ esp_err_t esp_cam_new_csi_ctlr(const esp_cam_ctlr_csi_config_t *config, esp_cam_
#endif
mipi_csi_phy_clock_source_t clk_src = !config->clk_src ? MIPI_CSI_PHY_CLK_SRC_DEFAULT : config->clk_src;
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), err, TAG, "clock source enable failed");
PERIPH_RCC_ATOMIC() {
// phy clock source setting
mipi_csi_ll_set_phy_clock_source(ctlr->csi_id, clk_src);
components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
+4 -4
View File
@@ -347,7 +347,7 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e
}
#if CONFIG_IDF_TARGET_ESP32S31
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)CAM_CORE_CLK_SRC_DEFAULT, true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src((soc_module_clk_t)CAM_CORE_CLK_SRC_DEFAULT));
#endif
PERIPH_RCC_ACQUIRE_ATOMIC(cam_periph_signals.buses[ctlr_id].module, ref_count) {
@@ -361,7 +361,7 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e
}
}
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src));
s_dvp_clk_src[ctlr_id] = (soc_module_clk_t)clk_src;
PERIPH_RCC_ATOMIC() {
cam_ll_enable_clk(ctlr_id, true);
@@ -468,12 +468,12 @@ esp_err_t esp_cam_ctlr_dvp_deinit(int ctlr_id)
}
if (s_dvp_clk_src[ctlr_id]) {
esp_clk_tree_enable_src(s_dvp_clk_src[ctlr_id], false);
esp_clk_tree_release_src(s_dvp_clk_src[ctlr_id]);
s_dvp_clk_src[ctlr_id] = 0;
}
#if CONFIG_IDF_TARGET_ESP32S31
esp_clk_tree_enable_src((soc_module_clk_t)CAM_CORE_CLK_SRC_DEFAULT, false);
esp_clk_tree_release_src((soc_module_clk_t)CAM_CORE_CLK_SRC_DEFAULT);
#endif
return ESP_OK;
components/esp_driver_dac/dac_cosine.c
+3 -3
View File
@@ -57,7 +57,7 @@ esp_err_t dac_cosine_new_channel(const dac_cosine_config_t *cos_cfg, dac_cosine_
/* Acquire the generator clock and resolve its frequency */
uint32_t clk_freq = 0;
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)handle->cfg.clk_src, true), err_handle, TAG, "enable clock failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)handle->cfg.clk_src), err_handle, TAG, "enable clock failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)handle->cfg.clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_freq),
err_clk, TAG, "get clock frequency failed");
@@ -101,7 +101,7 @@ esp_err_t dac_cosine_new_channel(const dac_cosine_config_t *cos_cfg, dac_cosine_
err_dereg:
dac_priv_channel_deregister(cos_cfg->chan_id);
err_clk:
esp_clk_tree_enable_src((soc_module_clk_t)handle->cfg.clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)handle->cfg.clk_src);
err_handle:
free(handle);
return ret;
@@ -118,7 +118,7 @@ esp_err_t dac_cosine_del_channel(dac_cosine_handle_t handle)
ESP_RETURN_ON_ERROR(dac_priv_channel_deregister(handle->cfg.chan_id), TAG,
"deregister dac channel %d failed", handle->cfg.chan_id);
ESP_RETURN_ON_ERROR(dac_priv_sintx_release(), TAG, "release dac sintx generator failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)handle->cfg.clk_src, false), TAG, "disable clock failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)handle->cfg.clk_src), TAG, "disable clock failed");
free(handle);
return ESP_OK;
components/esp_driver_dac/esp32/dac_dma.c
+2 -2
View File
@@ -147,7 +147,7 @@ esp_err_t dac_priv_dma_init(soc_periph_dac_digi_clk_src_t clk_src, uint32_t freq
ESP_GOTO_ON_ERROR(i2s_platform_acquire_occupation(I2S_CTLR_HP, DAC_DMA_PERIPH_I2S_NUM, "dac_dma"), err, TAG, "Failed to acquire DAC DMA peripheral");
s_ddp->periph_dev = (void *)I2S_LL_GET_HW(DAC_DMA_PERIPH_I2S_NUM);
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "enable DAC digital clock source failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), err, TAG, "enable DAC digital clock source failed");
s_ddp->clk_src = clk_src;
dac_ll_dma_clk_inv(true);
ESP_GOTO_ON_ERROR(s_dac_priv_dma_set_clock(clk_src, freq_hz), err, TAG, "Failed to set clock of DMA peripheral");
@@ -191,7 +191,7 @@ esp_err_t dac_priv_dma_deinit(void)
if (s_ddp->clk_src) {
dac_ll_dma_clk_inv(false);
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)s_ddp->clk_src, false), TAG, "disable DAC digital clock source failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)s_ddp->clk_src), TAG, "disable DAC digital clock source failed");
s_ddp->clk_src = 0;
}
components/esp_driver_dac/esp32s2/dac_dma.c
+2 -2
View File
@@ -164,7 +164,7 @@ esp_err_t dac_priv_dma_init(soc_periph_dac_digi_clk_src_t clk_src, uint32_t freq
s_ddp->periph_dev = (void *)SPI_LL_GET_HW(DAC_DMA_PERIPH_SPI_HOST);
/* Configure clock source and frequency */
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "enable DAC digital clock source failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), err, TAG, "enable DAC digital clock source failed");
s_ddp->clk_src = clk_src;
/* When transmit alternately, twice frequency is needed to guarantee the convert frequency in one channel */
uint32_t trans_freq_hz = freq_hz * (is_alternate ? 2 : 1);
@@ -212,7 +212,7 @@ esp_err_t dac_priv_dma_deinit(void)
if (s_ddp->clk_src) {
dac_ll_dma_clk_inv(false);
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)s_ddp->clk_src, false), TAG, "disable DAC digital clock source failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)s_ddp->clk_src), TAG, "disable DAC digital clock source failed");
s_ddp->clk_src = 0;
}
components/esp_driver_gpio/src/gpio_flex_glitch_filter.c
+2 -2
View File
@@ -83,7 +83,7 @@ static esp_err_t gpio_filter_destroy(gpio_flex_glitch_filter_t *filter)
io_mux_release_clock_source(filter->clk_src);
}
if (filter->clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(filter->clk_src, false);
esp_clk_tree_release_src(filter->clk_src);
}
free(filter);
@@ -150,7 +150,7 @@ esp_err_t gpio_new_flex_glitch_filter(const gpio_flex_glitch_filter_config_t *co
int filter_id = filter->filter_id;
soc_module_clk_t clk_src = config->clk_src ? config->clk_src : GLITCH_FILTER_CLK_SRC_DEFAULT;
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(clk_src, true), err, TAG, "enable IOMUX clock source failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src(clk_src), err, TAG, "enable IOMUX clock source failed");
filter->clk_src = clk_src;
ESP_GOTO_ON_ERROR(io_mux_acquire_clock_source(clk_src), err, TAG, "acquire IOMUX clock source failed");
filter->io_mux_clk_acquired = true;
components/esp_driver_gpio/src/gpio_pin_glitch_filter.c
+2 -2
View File
@@ -35,7 +35,7 @@ static esp_err_t gpio_filter_destroy(gpio_pin_glitch_filter_t *filter)
io_mux_release_clock_source(filter->clk_src);
}
if (filter->clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(filter->clk_src, false);
esp_clk_tree_release_src(filter->clk_src);
}
#if CONFIG_PM_ENABLE
@@ -103,7 +103,7 @@ esp_err_t gpio_new_pin_glitch_filter(const gpio_pin_glitch_filter_config_t *conf
filter->io_mux_clk_acquired = false;
soc_module_clk_t clk_src = config->clk_src ? config->clk_src : GLITCH_FILTER_CLK_SRC_DEFAULT;
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(clk_src, true), err, TAG, "enable IOMUX clock source failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src(clk_src), err, TAG, "enable IOMUX clock source failed");
filter->clk_src = clk_src;
ESP_GOTO_ON_ERROR(io_mux_acquire_clock_source(clk_src), err, TAG, "acquire IOMUX clock source failed");
filter->io_mux_clk_acquired = true;
components/esp_driver_gptimer/src/gptimer.c
+1 -1
View File
@@ -117,7 +117,7 @@ static void gptimer_unregister_from_group(gptimer_t *timer)
static esp_err_t gptimer_destroy(gptimer_t *timer)
{
if (timer->clk_src) {
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(timer->clk_src), false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)(timer->clk_src)), TAG, "clock source disable failed");
}
#if CONFIG_PM_ENABLE
if (timer->pm_lock) {
components/esp_driver_gptimer/src/gptimer_common.c
+1 -1
View File
@@ -91,7 +91,7 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
uint32_t counter_src_hz = 0;
int timer_id = timer->timer_id;
int group_id = timer->group->group_id;
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(src_clk, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src(src_clk), TAG, "clock source enable failed");
timer->clk_src = src_clk;
// get clock source frequency
components/esp_driver_i2c/i2c_common.c
+2 -2
View File
@@ -210,7 +210,7 @@ esp_err_t i2c_release_bus_handle(i2c_bus_handle_t i2c_bus)
i2c_bus->pm_lock = NULL;
}
#endif
esp_clk_tree_enable_src(clk_src, false);
esp_clk_tree_release_src(clk_src);
#if I2C_USE_RETENTION_LINK
if (i2c_bus->is_lp_i2c == false) {
if (i2c_bus->retention_link_created) {
@@ -266,7 +266,7 @@ esp_err_t i2c_select_periph_clock(i2c_bus_handle_t handle, soc_module_clk_t clk_
ESP_RETURN_ON_FALSE(!clock_selection_conflict, ESP_ERR_INVALID_STATE, TAG,
"group clock conflict, already is %d but attempt to %d", handle->clk_src, clk_src);
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(clk_src, true), TAG, "clock source clock enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src(clk_src), TAG, "clock source clock enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &periph_src_clk_hz), TAG, "i2c get clock frequency error");
components/esp_driver_i2s/i2s_common.c
+3 -3
View File
@@ -1521,7 +1521,7 @@ esp_err_t i2s_del_channel(i2s_chan_handle_t handle)
#endif
// since the enum value of default clock on some chips may be 0, we use mode to check if the clock is enabled
if (handle->mode != I2S_COMM_MODE_NONE) {
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)clk_src);
}
#if CONFIG_PM_ENABLE
@@ -1901,9 +1901,9 @@ esp_err_t i2s_channel_tune_rate(i2s_chan_handle_t handle, const i2s_tuning_confi
xSemaphoreTake(handle->mutex, portMAX_DELAY);
#if SOC_I2S_SUPPORTS_APLL
if (handle->clk_src == I2S_CLK_SRC_APLL) {
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, false), err, TAG, "APLL disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src(SOC_MOD_CLK_APLL), err, TAG, "APLL disable failed");
handle->sclk_hz = i2s_set_get_apll_freq(new_mclk);
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, true), err, TAG, "APLL enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src(SOC_MOD_CLK_APLL), err, TAG, "APLL enable failed");
}
#endif
/* Calculate the new divider */
components/esp_driver_i2s/i2s_pdm.c
+8 -8
View File
@@ -88,7 +88,7 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
i2s_hal_clock_info_t clk_info;
// Calculate clock parameters before enabling clock source
ESP_RETURN_ON_ERROR(i2s_pdm_tx_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), TAG, "clock source enable failed");
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
@@ -120,7 +120,7 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
return ret;
err:
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)clk_src);
return ret;
}
@@ -301,7 +301,7 @@ esp_err_t i2s_channel_reconfig_pdm_tx_clock(i2s_chan_handle_t handle, const i2s_
ESP_GOTO_ON_ERROR(i2s_pdm_tx_set_clock(handle, clk_cfg), err, TAG, "update clock failed");
// disable old clock source after new clock is successfully configured
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false), err, TAG, "clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)old_clk_src), err, TAG, "clock source disable failed");
#ifdef CONFIG_PM_ENABLE
// Create/Re-create power management lock
if (old_clk_src != clk_cfg->clk_src) {
@@ -359,7 +359,7 @@ esp_err_t i2s_channel_reconfig_pdm_tx_slot(i2s_chan_handle_t handle, const i2s_p
#endif
ESP_GOTO_ON_ERROR(i2s_pdm_tx_set_clock(handle, &pdm_tx_cfg->clk_cfg), err, TAG, "update clock failed");
// disable old clock source after new clock is successfully configured
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false), err, TAG, "clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)old_clk_src), err, TAG, "clock source disable failed");
}
xSemaphoreGive(handle->mutex);
@@ -461,7 +461,7 @@ static esp_err_t i2s_pdm_rx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_rx
* can be set while ref_cnt is still < 2 (which is the threshold for freq change) */
ESP_RETURN_ON_ERROR(i2s_pdm_rx_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), TAG, "clock source enable failed");
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
@@ -488,7 +488,7 @@ static esp_err_t i2s_pdm_rx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_rx
return ret;
err:
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)clk_src);
return ret;
}
@@ -670,7 +670,7 @@ esp_err_t i2s_channel_reconfig_pdm_rx_clock(i2s_chan_handle_t handle, const i2s_
ESP_GOTO_ON_ERROR(i2s_pdm_rx_set_clock(handle, clk_cfg), err, TAG, "update clock failed");
// disable old clock source after new clock is successfully configured
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false), err, TAG, "clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)old_clk_src), err, TAG, "clock source disable failed");
#ifdef CONFIG_PM_ENABLE
// Create/Re-create power management lock
if (old_clk_src != clk_cfg->clk_src) {
@@ -728,7 +728,7 @@ esp_err_t i2s_channel_reconfig_pdm_rx_slot(i2s_chan_handle_t handle, const i2s_p
#endif
ESP_GOTO_ON_ERROR(i2s_pdm_rx_set_clock(handle, &pdm_rx_cfg->clk_cfg), err, TAG, "update clock failed");
// disable old clock source after new clock is successfully configured
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false), err, TAG, "clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)old_clk_src), err, TAG, "clock source disable failed");
}
xSemaphoreGive(handle->mutex);
components/esp_driver_i2s/i2s_std.c
+4 -4
View File
@@ -98,7 +98,7 @@ static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_c
i2s_hal_clock_info_t clk_info;
// Calculate clock parameters before enabling clock source
ESP_RETURN_ON_ERROR(i2s_std_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), TAG, "clock source enable failed");
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
@@ -128,7 +128,7 @@ static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_c
return ret;
err:
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)clk_src);
return ret;
}
@@ -415,7 +415,7 @@ esp_err_t i2s_channel_reconfig_std_clock(i2s_chan_handle_t handle, const i2s_std
ESP_GOTO_ON_ERROR(i2s_std_set_clock(handle, clk_cfg), err, TAG, "update clock failed");
// disable old clock source after new clock is successfully configured
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false), err, TAG, "clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)old_clk_src), err, TAG, "clock source disable failed");
#ifdef CONFIG_PM_ENABLE
// Create/Re-create power management lock
@@ -473,7 +473,7 @@ esp_err_t i2s_channel_reconfig_std_slot(i2s_chan_handle_t handle, const i2s_std_
#endif
ESP_GOTO_ON_ERROR(i2s_std_set_clock(handle, &std_cfg->clk_cfg), err, TAG, "update clock failed");
// disable old clock source after new clock is successfully configured
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false), err, TAG, "clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)old_clk_src), err, TAG, "clock source disable failed");
}
xSemaphoreGive(handle->mutex);
components/esp_driver_i2s/i2s_tdm.c
+4 -4
View File
@@ -96,7 +96,7 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c
i2s_hal_clock_info_t clk_info;
// Calculate clock parameters before enabling clock source
ESP_RETURN_ON_ERROR(i2s_tdm_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), TAG, "clock source enable failed");
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
@@ -126,7 +126,7 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c
return ret;
err:
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)clk_src);
return ret;
}
@@ -394,7 +394,7 @@ esp_err_t i2s_channel_reconfig_tdm_clock(i2s_chan_handle_t handle, const i2s_tdm
ESP_GOTO_ON_ERROR(i2s_tdm_set_clock(handle, clk_cfg), err, TAG, "update clock failed");
// disable old clock source after new clock is successfully configured
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false), err, TAG, "clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)old_clk_src), err, TAG, "clock source disable failed");
#ifdef CONFIG_PM_ENABLE
// Create/Re-create power management lock
@@ -453,7 +453,7 @@ esp_err_t i2s_channel_reconfig_tdm_slot(i2s_chan_handle_t handle, const i2s_tdm_
#endif
ESP_GOTO_ON_ERROR(i2s_tdm_set_clock(handle, &tdm_cfg->clk_cfg), err, TAG, "update clock failed");
// disable old clock source after new clock is successfully configured
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false), err, TAG, "clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)old_clk_src), err, TAG, "clock source disable failed");
}
/* Reset queue (skip when no GDMA path is in use) */
components/esp_driver_i3c/i3c_master.c
+2 -2
View File
@@ -478,7 +478,7 @@ static esp_err_t i3c_master_bus_destroy(i3c_master_bus_handle_t bus_handle)
}
if (bus_handle->clock_source) {
esp_clk_tree_enable_src((soc_module_clk_t)bus_handle->clock_source, false);
esp_clk_tree_release_src((soc_module_clk_t)bus_handle->clock_source);
}
#if CONFIG_PM_ENABLE
@@ -743,7 +743,7 @@ esp_err_t i3c_new_master_bus(const i3c_master_bus_config_t *bus_config, i3c_mast
uint32_t periph_src_clk_hz = 0;
i3c_master_handle->clock_source = bus_config->clock_source;
esp_clk_tree_enable_src((soc_module_clk_t)i3c_master_handle->clock_source, true);
esp_clk_tree_acquire_src((soc_module_clk_t)i3c_master_handle->clock_source);
PERIPH_RCC_ATOMIC() {
i3c_master_ll_set_source_clk(i3c_master_handle->hal.dev, i3c_master_handle->clock_source);
}
components/esp_driver_isp/src/isp_core.c
+2 -2
View File
@@ -128,7 +128,7 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_
if (out_clk_freq_hz != proc_config->clk_hz) {
ESP_LOGW(TAG, "precision loss, real output frequency: %"PRIu32"Hz", out_clk_freq_hz);
}
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), err, TAG, "clock source enable failed");
PERIPH_RCC_ATOMIC() {
isp_ll_select_clk_source(clk_src);
isp_ll_set_clock_div(&clk_div);
@@ -241,7 +241,7 @@ esp_err_t esp_isp_del_processor(isp_proc_handle_t proc)
#if SOC_ISP_SHARE_CSI_BRG
ESP_RETURN_ON_ERROR(mipi_csi_brg_declaim(proc->csi_brg_id), TAG, "declaim csi bridge fail");
#endif
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(proc->clk_src), false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)(proc->clk_src)), TAG, "clock source disable failed");
if (proc->intr_hdl) {
esp_isp_deregister_isr(proc, ISP_SUBMODULE_GENERAL);
}
components/esp_driver_ledc/src/ledc.c
+2 -2
View File
@@ -700,7 +700,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
if (p_ledc_obj[speed_mode]->glb_clk != glb_clk) {
// TODO: release old glb_clk (if not UNINIT), and acquire new glb_clk [clk_tree]
p_ledc_obj[speed_mode]->glb_clk = glb_clk;
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)glb_clk, true), LEDC_TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)glb_clk), LEDC_TAG, "clock source enable failed");
PERIPH_RCC_ATOMIC() {
ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk);
}
@@ -900,7 +900,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
else if (new_speed_mode_ctx_created) {
portENTER_CRITICAL(&ledc_spinlock);
if (p_ledc_obj[speed_mode]->glb_clk == LEDC_SLOW_CLK_UNINIT) {
esp_clk_tree_enable_src((soc_module_clk_t)LEDC_LL_GLOBAL_CLK_DEFAULT, true);
esp_clk_tree_acquire_src((soc_module_clk_t)LEDC_LL_GLOBAL_CLK_DEFAULT);
ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), LEDC_LL_GLOBAL_CLK_DEFAULT);
}
portEXIT_CRITICAL(&ledc_spinlock);
components/esp_driver_mcpwm/src/mcpwm_com.c
+3 -3
View File
@@ -144,7 +144,7 @@ void mcpwm_release_group_handle(mcpwm_group_t *group)
}
// release the group clock source acquired in mcpwm_select_periph_clock_unsafe()
if (group->clk_src) {
esp_clk_tree_enable_src(group->clk_src, false);
esp_clk_tree_release_src(group->clk_src);
}
#if CONFIG_PM_ENABLE
if (group->pm_lock) {
@@ -180,7 +180,7 @@ static esp_err_t mcpwm_select_periph_clock_unsafe(mcpwm_group_t *group, soc_modu
}
group->clk_src = clk_src;
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true),
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src),
err, TAG, "clock source enable failed");
#if CONFIG_PM_ENABLE
// to make the mcpwm works reliable, the source clock must stay alive and unchanged
@@ -200,7 +200,7 @@ static esp_err_t mcpwm_select_periph_clock_unsafe(mcpwm_group_t *group, soc_modu
#if CONFIG_PM_ENABLE
err_clock_enabled:
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)clk_src);
#endif
err:
group->clk_src = 0;
components/esp_driver_parlio/src/parlio_rx.c
+2 -2
View File
@@ -598,7 +598,7 @@ static esp_err_t parlio_destroy_rx_unit(parlio_rx_unit_handle_t rx_unit)
parlio_unregister_unit_from_group(&rx_unit->base);
}
if (rx_unit->clk_src) {
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)rx_unit->clk_src, false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)rx_unit->clk_src), TAG, "clock source disable failed");
}
/* Free the RX unit */
free(rx_unit);
@@ -673,7 +673,7 @@ esp_err_t parlio_new_rx_unit(const parlio_rx_unit_config_t *config, parlio_rx_un
}
parlio_ll_rx_start(hal->regs, false);
/* parlio_ll_clock_source_t and parlio_clock_source_t are binary compatible if the clock source is from internal */
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(config->clk_src), true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)(config->clk_src)), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(parlio_select_periph_clock(unit, config), err, TAG, "set clock source failed");
/* Set the data width */
parlio_ll_rx_set_bus_width(hal->regs, config->data_width);
components/esp_driver_parlio/src/parlio_tx.c
+2 -2
View File
@@ -84,7 +84,7 @@ static esp_err_t parlio_destroy_tx_unit(parlio_tx_unit_t *tx_unit)
}
}
if (tx_unit->clk_src) {
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)tx_unit->clk_src, false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)tx_unit->clk_src), TAG, "clock source disable failed");
}
free(tx_unit);
return ESP_OK;
@@ -301,7 +301,7 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
parlio_group_t *group = unit->base.group;
parlio_hal_context_t *hal = &group->hal;
// select the clock source
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(config->clk_src), true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)(config->clk_src)), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(parlio_select_periph_clock(unit, config), err, TAG, "set clock source failed");
// install interrupt service
components/esp_driver_pcnt/src/pulse_cnt.c
+2 -2
View File
@@ -248,7 +248,7 @@ esp_err_t pcnt_new_unit(const pcnt_unit_config_t *config, pcnt_unit_handle_t *re
pcnt_clock_source_t pcnt_clk_src = config->clk_src ? config->clk_src : PCNT_CLK_SRC_DEFAULT;
ESP_GOTO_ON_ERROR(pcnt_select_periph_clock(unit, pcnt_clk_src), err, TAG, "select periph clock failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)group->clk_src, true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)group->clk_src), err, TAG, "clock source enable failed");
// to accumulate count value, we should install the interrupt handler first, and in the ISR we do the accumulation
bool to_install_isr = (config->flags.accum_count == 1);
@@ -333,7 +333,7 @@ esp_err_t pcnt_del_unit(pcnt_unit_handle_t unit)
ESP_LOGD(TAG, "del unit (%d,%d)", group_id, unit_id);
// disable clock source
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)group->clk_src, false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)group->clk_src), TAG, "clock source disable failed");
// recycle memory resource
ESP_RETURN_ON_ERROR(pcnt_destroy(unit), TAG, "destroy pcnt unit failed");
return ESP_OK;
components/esp_driver_rmt/src/rmt_common.c
+2 -2
View File
@@ -201,7 +201,7 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t
ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed");
#endif // CONFIG_PM_ENABLE
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), TAG, "clock source enable failed");
uint32_t real_div;
#if RMT_LL_GET(CHANNEL_CLK_INDEPENDENT)
uint32_t periph_src_clk_hz = 0;
@@ -233,7 +233,7 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t
return ret;
err:
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)clk_src);
return ret;
}
components/esp_driver_rmt/src/rmt_rx.c
+1 -1
View File
@@ -324,7 +324,7 @@ static esp_err_t rmt_del_rx_channel(rmt_channel_handle_t channel)
// recycle memory resource
ESP_RETURN_ON_ERROR(rmt_rx_destroy(rx_chan), TAG, "destroy rx channel failed");
// disable the clock source at last
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(clk_src, false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src(clk_src), TAG, "clock source disable failed");
return ESP_OK;
}
components/esp_driver_rmt/src/rmt_tx.c
+1 -1
View File
@@ -383,7 +383,7 @@ static esp_err_t rmt_del_tx_channel(rmt_channel_handle_t channel)
// recycle memory resource
ESP_RETURN_ON_ERROR(rmt_tx_destroy(tx_chan), TAG, "destroy tx channel failed");
// disable the clock source at last
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(clk_src, false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src(clk_src), TAG, "clock source disable failed");
return ESP_OK;
}
components/esp_driver_sdm/src/sdm.c
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -172,7 +172,7 @@ static esp_err_t sdm_group_install(sdm_group_t *group, soc_module_clk_t clk_src)
}
#endif // SDM_USE_RETENTION_LINK
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(clk_src, true), err, TAG, "enable clock source failed for group %d", group_id);
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src(clk_src), err, TAG, "enable clock source failed for group %d", group_id);
group->clk_src = clk_src;
// SDM clock comes from IO MUX, but IO MUX clock might be shared with other submodules as well
ESP_GOTO_ON_ERROR(io_mux_acquire_clock_source(clk_src), err, TAG, "acquire IO MUX clock source failed for group %d", group_id);
@@ -212,7 +212,7 @@ err:
group->io_mux_clk_acquired = false;
}
if (group->clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(group->clk_src, false);
esp_clk_tree_release_src(group->clk_src);
group->clk_src = SOC_MOD_CLK_INVALID;
}
_lock_release(&s_platform.mutex);
@@ -231,7 +231,7 @@ static void sdm_group_uninstall(sdm_group_t *group)
group->io_mux_clk_acquired = false;
}
if (group->clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(group->clk_src, false);
esp_clk_tree_release_src(group->clk_src);
group->clk_src = SOC_MOD_CLK_INVALID;
}
components/esp_driver_sdmmc/src/sd_host_sdmmc.c
+3 -3
View File
@@ -113,7 +113,7 @@ esp_err_t sd_host_create_sdmmc_controller(const sd_host_sdmmc_cfg_t *config, sd_
#endif //CONFIG_PM_ENABLE
sdmmc_hal_init(&ctlr->hal);
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(SDMMC_CLK_SRC_DEFAULT, true), err, TAG, "failed to acquire clk");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src(SDMMC_CLK_SRC_DEFAULT), err, TAG, "failed to acquire clk");
uint32_t src_freq_hz = 0;
esp_clk_tree_src_get_freq_hz(SDMMC_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_freq_hz);
ESP_EARLY_LOGI(TAG, "src_freq_hz: %d", src_freq_hz);
@@ -441,7 +441,7 @@ static esp_err_t sd_host_del_sdmmc_controller(sd_host_ctlr_handle_t ctlr)
#endif
#if SDMMC_LL_MPLL_SUPPORTED
esp_clk_tree_enable_src(SOC_MOD_CLK_MPLL, false);
esp_clk_tree_release_src(SOC_MOD_CLK_MPLL);
#endif
if (ctlr_ctx->mutex) {
@@ -1096,7 +1096,7 @@ static esp_err_t sd_host_reset(sd_host_sdmmc_ctlr_t *ctlr)
*/
static void sd_host_set_clk_div(sd_host_sdmmc_ctlr_t *ctlr, soc_periph_sdmmc_clk_src_t src, int div)
{
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)src, true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src((soc_module_clk_t)src));
PERIPH_RCC_ATOMIC() {
sdmmc_ll_set_clock_div(ctlr->hal.dev, div);
sdmmc_ll_select_clk_source(ctlr->hal.dev, src);
components/esp_driver_spi/src/gpspi/spi_master.c
+2 -2
View File
@@ -459,7 +459,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
uint32_t clock_source_hz = 0;
uint32_t clock_source_div = 1;
spi_clock_source_t clk_src = dev_config->clock_source ? dev_config->clock_source : SPI_CLK_SRC_DEFAULT;
SPI_CHECK(esp_clk_tree_enable_src(clk_src, true) == ESP_OK, "clock source enable failed", ESP_ERR_INVALID_STATE);
SPI_CHECK(esp_clk_tree_acquire_src(clk_src) == ESP_OK, "clock source enable failed", ESP_ERR_INVALID_STATE);
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz);
#if SPI_LL_SRC_PRE_DIV_MAX
clock_source_div = s_spi_find_clock_src_pre_div(clock_source_hz, dev_config->clock_speed_hz, dev_config->input_delay_ns > 0);
@@ -621,7 +621,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
spi_device_release_bus(handle);
}
}
SPI_CHECK(esp_clk_tree_enable_src(handle->hal_dev.timing_conf.clock_source, false) == ESP_OK, "clock source disable failed", ESP_ERR_INVALID_STATE);
SPI_CHECK(esp_clk_tree_release_src(handle->hal_dev.timing_conf.clock_source) == ESP_OK, "clock source disable failed", ESP_ERR_INVALID_STATE);
//return
int spics_io_num = handle->cfg.spics_io_num;
components/esp_driver_tsens/src/temperature_sensor.c
+2 -2
View File
@@ -241,7 +241,7 @@ esp_err_t temperature_sensor_enable(temperature_sensor_handle_t tsens)
ESP_RETURN_ON_FALSE((tsens != NULL), ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(tsens->fsm == TEMP_SENSOR_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "tsens not in init state");
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(tsens->clk_src, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src(tsens->clk_src), TAG, "clock source enable failed");
#if SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
temperature_sensor_ll_wakeup_enable(true);
@@ -268,7 +268,7 @@ esp_err_t temperature_sensor_disable(temperature_sensor_handle_t tsens)
tsens->fsm = TEMP_SENSOR_FSM_INIT;
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(tsens->clk_src, false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src(tsens->clk_src), TAG, "clock source disable failed");
return ESP_OK;
}
components/esp_driver_twai/esp_twai_onchip.c
+2 -2
View File
@@ -389,7 +389,7 @@ static esp_err_t _node_delete(twai_node_handle_t node)
twai_hal_deinit(twai_ctx->hal);
_twai_rcc_clock_ctrl(twai_ctx->ctrlr_id, false);
// curr_clk_src must not NULL as we already set to Default in twai_new_node_onchip
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(twai_ctx->curr_clk_src, false), TAG, "disable clock source failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src(twai_ctx->curr_clk_src), TAG, "disable clock source failed");
_node_destroy(twai_ctx);
return ESP_OK;
}
@@ -779,7 +779,7 @@ esp_err_t twai_new_node_onchip(const twai_onchip_node_config_t *node_config, twa
#endif //CONFIG_PM_ENABLE
// Set clock source, enable bus clock and reset controller
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(node->curr_clk_src, true), err, TAG, "enable clock source failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src(node->curr_clk_src), err, TAG, "enable clock source failed");
ESP_LOGD(TAG, "set clock source to %d, freq: %ld Hz", node->curr_clk_src, node->src_freq_hz);
_twai_rcc_clock_sel(node->ctrlr_id, node->curr_clk_src);
_twai_rcc_clock_ctrl(ctrlr_id, true);
components/esp_driver_uart/src/uart.c
+7 -7
View File
@@ -1091,7 +1091,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "invalid src_clk");
// Enable the newly selected clock source
esp_clk_tree_enable_src(uart_sclk_sel, true);
esp_clk_tree_acquire_src(uart_sclk_sel);
bool success = false;
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
@@ -1123,12 +1123,12 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
uart_hal_txfifo_rst(&(uart_context[uart_num].hal));
// Disable the previously selected clock source, and update the new source in context
soc_module_clk_t uart_old_sclk_sel = uart_context[uart_num].sclk_sel;
esp_clk_tree_enable_src(uart_old_sclk_sel, false);
esp_clk_tree_release_src(uart_old_sclk_sel);
if (success) {
uart_context[uart_num].sclk_sel = uart_sclk_sel;
} else {
uart_context[uart_num].sclk_sel = -1;
esp_clk_tree_enable_src(uart_sclk_sel, false);
esp_clk_tree_release_src(uart_sclk_sel);
ESP_LOGE(UART_TAG, "baud rate unachievable");
return ESP_FAIL;
}
@@ -2090,7 +2090,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
default_sclk = LP_UART_SCLK_DEFAULT;
}
#endif
esp_clk_tree_enable_src(default_sclk, true);
esp_clk_tree_acquire_src(default_sclk);
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_num < SOC_UART_HP_NUM) {
PERIPH_RCC_ATOMIC() {
@@ -2143,7 +2143,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
p_uart_obj[uart_num] = NULL;
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false);
esp_clk_tree_release_src(uart_context[uart_num].sclk_sel);
uart_context[uart_num].sclk_sel = -1;
}
@@ -2344,7 +2344,7 @@ esp_err_t uart_detect_bitrate_start(uart_port_t uart_num, const uart_bitrate_det
uart_sclk_sel = (soc_module_clk_t)((config->source_clk) ? config->source_clk : UART_SCLK_DEFAULT); // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock
uint32_t sclk_freq = 0;
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), err, UART_TAG, "invalid source_clk");
esp_clk_tree_enable_src(uart_sclk_sel, true);
esp_clk_tree_acquire_src(uart_sclk_sel);
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
PERIPH_RCC_ATOMIC() {
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
@@ -2427,7 +2427,7 @@ esp_err_t uart_detect_bitrate_stop(uart_port_t uart_num, bool deinit, uart_bitra
if (deinit) { // release the port
uart_release_pin(uart_num, true, true, true, true, true, true);
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false);
esp_clk_tree_release_src(uart_context[uart_num].sclk_sel);
uart_context[uart_num].sclk_sel = -1;
}
uart_module_disable(uart_num);
components/esp_eth/src/mac/esp_eth_mac_esp.c
+4 -4
View File
@@ -294,7 +294,7 @@ static esp_err_t emac_enable_ref_out_clock(emac_esp32_t *emac, const emac_clk_in
#if !SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
static esp_err_t emac_config_phy_ref_clk_clock(emac_esp32_t *emac, soc_module_clk_t phy_ref_src, soc_module_clk_t upstream_src)
{
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(phy_ref_src, true), TAG, "PHY_REF_CLK enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src(phy_ref_src), TAG, "PHY_REF_CLK enable failed");
esp_err_t up_ret = esp_clk_tree_src_select_upstream(phy_ref_src, upstream_src);
if (up_ret == ESP_ERR_INVALID_STATE) {
ESP_LOGW(TAG, "PHY_REF_CLK upstream is already selected by another peripheral; reusing existing routing");
@@ -337,13 +337,13 @@ static esp_err_t emac_config_pll_clock(emac_esp32_t *emac, const emac_clk_info_t
}
ESP_LOGD(TAG, "info->clk_id: %i, info->clk_name: %s, pll_expt_freq: %" PRIu32 " Hz", info->clk_id, info->clk_name, pll_expt_freq);
ESP_RETURN_ON_FALSE(pll_expt_freq > 0, ESP_ERR_NOT_SUPPORTED, TAG, "No %s on %" PRIi32 " Hz grid divides %" PRIu32 " Hz", info->clk_name, info->step_hz, *freq_hz);
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(info->clk_id, true), TAG, "%s enable failed", info->clk_name);
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src(info->clk_id), TAG, "%s enable failed", info->clk_name);
esp_err_t ret = esp_clk_tree_src_set_freq_hz(info->clk_id, pll_expt_freq, &real_freq);
ESP_LOGD(TAG, "Clock set frequency: %" PRIu32 " Hz", real_freq);
if (ret == ESP_ERR_INVALID_STATE) {
ESP_LOGW(TAG, "%s is occupied already, it is working at %" PRIu32 " Hz", info->clk_name, real_freq);
} else if (ret != ESP_OK) {
esp_clk_tree_enable_src(info->clk_id, false);
esp_clk_tree_release_src(info->clk_id);
ESP_RETURN_ON_ERROR(ret, TAG, "Set %s clock failed", info->clk_name);
}
*freq_hz = real_freq;
@@ -833,7 +833,7 @@ static void emac_esp_free_driver_obj(emac_esp32_t *emac)
for (int32_t i = 0; i < EMAC_USED_PLL_CLK_MAX_COUNT; i++) {
if (emac->pll_clk_used[i] != EMAC_UNDEFINED_PLL_CLK) {
esp_clk_tree_enable_src(emac->pll_clk_used[i], false);
esp_clk_tree_release_src(emac->pll_clk_used[i]);
}
}
components/esp_eth/test_apps/test_app_driver/main/esp_eth_test_esp_emac.c
+10 -10
View File
@@ -645,37 +645,37 @@ TEST_CASE("internal emac MPLL shared with PSRAM", "[esp_emac_clk_out][skip_setup
// PSRAM default speed: MPLL at 400 MHz — EMAC divider 8 gives exactly 50 MHz
ESP_LOGI(TAG, "Verify MPLL at 400 MHz (simulating PSRAM default)");
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_MPLL, true));
TEST_ESP_OK(esp_clk_tree_acquire_src(SOC_MOD_CLK_MPLL));
TEST_ESP_OK(esp_clk_tree_src_set_freq_hz(SOC_MOD_CLK_MPLL, 400 * 1000000, &real_freq));
ESP_LOGI(TAG, "MPLL set to %" PRIu32 " Hz", real_freq);
mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config);
TEST_ASSERT_NOT_NULL(mac);
TEST_ESP_OK(mac->del(mac));
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_MPLL, false));
TEST_ESP_OK(esp_clk_tree_release_src(SOC_MOD_CLK_MPLL));
// PSRAM 250M speed: MPLL at 500 MHz — EMAC divider 10 gives exactly 50 MHz
ESP_LOGI(TAG, "Verify MPLL at 500 MHz (simulating PSRAM @ 250M speed)");
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_MPLL, true));
TEST_ESP_OK(esp_clk_tree_acquire_src(SOC_MOD_CLK_MPLL));
TEST_ESP_OK(esp_clk_tree_src_set_freq_hz(SOC_MOD_CLK_MPLL, 500 * 1000000, &real_freq));
ESP_LOGI(TAG, "MPLL set to %" PRIu32 " Hz", real_freq);
mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config);
TEST_ASSERT_NOT_NULL(mac);
TEST_ESP_OK(mac->del(mac));
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_MPLL, false));
TEST_ESP_OK(esp_clk_tree_release_src(SOC_MOD_CLK_MPLL));
// PSRAM 80M speed: MPLL at 320 MHz — no integer divider can produce 50 MHz within tolerance,
// see AP_HEX_PSRAM_MPLL_DEFAULT_FREQ_MHZ for reference
// Best candidate: 320/6 = 53.33 MHz (error ~3.33 MHz >> 2500 Hz tolerance)
ESP_LOGI(TAG, "Verify MPLL at 320 MHz (simulating PSRAM @ 80M speed) — expected to fail");
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_MPLL, true));
TEST_ESP_OK(esp_clk_tree_acquire_src(SOC_MOD_CLK_MPLL));
TEST_ESP_OK(esp_clk_tree_src_set_freq_hz(SOC_MOD_CLK_MPLL, 320 * 1000000, &real_freq));
ESP_LOGI(TAG, "MPLL set to %" PRIu32 " Hz", real_freq);
mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config);
TEST_ASSERT_NULL(mac);
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_MPLL, false));
TEST_ESP_OK(esp_clk_tree_release_src(SOC_MOD_CLK_MPLL));
}
#endif // SOC_EMAC_REF_CLK_FROM_MPLL
@@ -699,24 +699,24 @@ TEST_CASE("internal emac APLL shared with I2S", "[esp_emac_clk_out][skip_setup_t
// Another peripheral has APLL at 50 MHz — exact RMII clock match, EMAC should succeed
ESP_LOGI(TAG, "Verify APLL at 50 MHz (exact RMII clock match)");
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, true));
TEST_ESP_OK(esp_clk_tree_acquire_src(SOC_MOD_CLK_APLL));
TEST_ESP_OK(esp_clk_tree_src_set_freq_hz(SOC_MOD_CLK_APLL, 50 * 1000000, &real_freq));
ESP_LOGI(TAG, "APLL set to %" PRIu32 " Hz", real_freq);
mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config);
TEST_ASSERT_NOT_NULL(mac);
TEST_ESP_OK(mac->del(mac));
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, false));
TEST_ESP_OK(esp_clk_tree_release_src(SOC_MOD_CLK_APLL));
// I2S typical frequency: APLL at ~12.288 MHz (48 kHz * 256) — far from 50 MHz, EMAC should fail
ESP_LOGI(TAG, "Verify APLL at ~12.288 MHz (simulating I2S @ 48 kHz) — expected to fail");
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, true));
TEST_ESP_OK(esp_clk_tree_acquire_src(SOC_MOD_CLK_APLL));
TEST_ESP_OK(esp_clk_tree_src_set_freq_hz(SOC_MOD_CLK_APLL, 12288000, &real_freq));
ESP_LOGI(TAG, "APLL set to %" PRIu32 " Hz", real_freq);
mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config);
TEST_ASSERT_NULL(mac);
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, false));
TEST_ESP_OK(esp_clk_tree_release_src(SOC_MOD_CLK_APLL));
}
#endif // SOC_EMAC_REF_CLK_FROM_APLL
components/esp_hal_regi2c/test_apps/main/test_regi2c.c
+2 -2
View File
@@ -20,7 +20,7 @@ TEST_CASE("regi2c basic read/write test", "[regi2c]")
#if CONFIG_IDF_TARGET_ESP32
// For ESP32, we need to enable the APLL clock before accessing the APLL regi2c registers
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, true));
TEST_ESP_OK(esp_clk_tree_acquire_src(SOC_MOD_CLK_APLL));
#endif
/* ---- Part 1: full-register read / write ---- */
@@ -92,6 +92,6 @@ TEST_CASE("regi2c basic read/write test", "[regi2c]")
#if CONFIG_IDF_TARGET_ESP32
// Disable APLL clock
TEST_ESP_OK(esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, false));
TEST_ESP_OK(esp_clk_tree_release_src(SOC_MOD_CLK_APLL));
#endif
}
components/esp_hal_security/test_apps/tee/components/pms_and_cpu_intr/src/cpu_intr/test_interrupt.c
+1 -1
View File
@@ -108,7 +108,7 @@ static void test_timer_init(int mode, int priority, test_intr_args_ctx_t *arg)
// Select clock source and enable module clock
// Enable the default clock source PLL_F80M
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F80M, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F80M);
TIMER_RCC_ATOMIC() {
timer_ll_set_clock_source(group_id, timer_id, GPTIMER_CLK_SRC_DEFAULT);
timer_ll_enable_clock(group_id, timer_id, true);
components/esp_hw_support/clk_ctrl_os.c
+6 -6
View File
@@ -11,7 +11,7 @@
bool periph_rtc_dig_clk8m_enable(void)
{
return esp_clk_tree_enable_src(SOC_MOD_CLK_RC_FAST, true) == ESP_OK;
return esp_clk_tree_acquire_src(SOC_MOD_CLK_RC_FAST) == ESP_OK;
}
uint32_t periph_rtc_dig_clk8m_get_freq(void)
@@ -25,18 +25,18 @@ uint32_t periph_rtc_dig_clk8m_get_freq(void)
void periph_rtc_dig_clk8m_disable(void)
{
(void)esp_clk_tree_enable_src(SOC_MOD_CLK_RC_FAST, false);
(void)esp_clk_tree_release_src(SOC_MOD_CLK_RC_FAST);
}
#if SOC_CLK_APLL_SUPPORTED
void periph_rtc_apll_acquire(void)
{
(void)esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, true);
(void)esp_clk_tree_acquire_src(SOC_MOD_CLK_APLL);
}
void periph_rtc_apll_release(void)
{
(void)esp_clk_tree_enable_src(SOC_MOD_CLK_APLL, false);
(void)esp_clk_tree_release_src(SOC_MOD_CLK_APLL);
}
esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz)
@@ -48,13 +48,13 @@ esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz
#if SOC_CLK_MPLL_SUPPORTED
esp_err_t IRAM_ATTR periph_rtc_mpll_acquire(void)
{
// For IRAM compatibility, we do not use esp_clk_tree_enable_src here
// For IRAM compatibility, we do not use esp_clk_tree_acquire_src here
return esp_clk_tree_mpll_acquire();
}
void periph_rtc_mpll_release(void)
{
// For IRAM compatibility, we do not use esp_clk_tree_enable_src here
// For IRAM compatibility, we do not use esp_clk_tree_release_src here
(void)esp_clk_tree_mpll_release();
}
components/esp_hw_support/etm/esp_etm.c
+3 -3
View File
@@ -276,7 +276,7 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch
if (clk_src == 0) {
clk_src = ETM_CLK_SRC_DEFAULT;
}
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), err, TAG, "clock source enable failed");
chan->clk_src = clk_src;
etm_ll_set_clock_source(group_id, clk_src);
#endif
@@ -298,7 +298,7 @@ err:
if (chan) {
#if ETM_LL_SUPPORT(CLOCK_SRC)
if (chan->clk_src != 0) {
esp_clk_tree_enable_src((soc_module_clk_t)chan->clk_src, false);
esp_clk_tree_release_src((soc_module_clk_t)chan->clk_src);
}
#endif
etm_chan_destroy(chan);
@@ -324,7 +324,7 @@ esp_err_t esp_etm_del_channel(esp_etm_channel_handle_t chan)
#if ETM_LL_SUPPORT(CLOCK_SRC)
// Back to hardware default clock selection, otherwise it might get stuck when stopping the bus during sleep process.
etm_ll_set_clock_source(group_id, ETM_CLK_SRC_XTAL);
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)chan->clk_src, false), TAG, "clock source disable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)chan->clk_src), TAG, "clock source disable failed");
#endif
// recycle memory resource
ESP_RETURN_ON_ERROR(etm_chan_destroy(chan), TAG, "destroy etm channel failed");
components/esp_hw_support/include/clk_ctrl_os.h
+6 -6
View File
@@ -21,7 +21,7 @@ extern "C" {
*
* @return true: success for enable the RC_FAST clock, false: RC_FAST clock enable failed
*/
bool periph_rtc_dig_clk8m_enable(void) __attribute__((deprecated("Please use esp_clk_tree_enable_src instead")));
bool periph_rtc_dig_clk8m_enable(void) __attribute__((deprecated("Please use esp_clk_tree_acquire_src instead")));
/**
* @brief This function is used to disable the digital RC_FAST clock, which should be called
@@ -30,7 +30,7 @@ bool periph_rtc_dig_clk8m_enable(void) __attribute__((deprecated("Please use esp
* @note If this function is called a number of times, the `periph_rtc_dig_clk8m_disable`
* function needs to be called same times to disable.
*/
void periph_rtc_dig_clk8m_disable(void) __attribute__((deprecated("Please use esp_clk_tree_enable_src instead")));
void periph_rtc_dig_clk8m_disable(void) __attribute__((deprecated("Please use esp_clk_tree_release_src instead")));
/**
* @brief This function is used to get the real clock frequency value of RC_FAST clock
@@ -43,12 +43,12 @@ uint32_t periph_rtc_dig_clk8m_get_freq(void) __attribute__((deprecated("Please u
/**
* @brief Enable APLL power if it has not enabled
*/
void periph_rtc_apll_acquire(void) __attribute__((deprecated("Please use esp_clk_tree_enable_src instead")));
void periph_rtc_apll_acquire(void) __attribute__((deprecated("Please use esp_clk_tree_acquire_src instead")));
/**
* @brief Shut down APLL power if no peripherals using APLL
*/
void periph_rtc_apll_release(void) __attribute__((deprecated("Please use esp_clk_tree_enable_src instead")));
void periph_rtc_apll_release(void) __attribute__((deprecated("Please use esp_clk_tree_release_src instead")));
/**
* @brief Calculate and set APLL coefficients by given frequency
@@ -76,12 +76,12 @@ esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz
/**
* @brief Enable MPLL power if it has not enabled
*/
esp_err_t periph_rtc_mpll_acquire(void) __attribute__((deprecated("Please use esp_clk_tree_enable_src instead")));
esp_err_t periph_rtc_mpll_acquire(void) __attribute__((deprecated("Please use esp_clk_tree_acquire_src instead")));
/**
* @brief Shut down MPLL power if no peripherals using APLL
*/
void periph_rtc_mpll_release(void) __attribute__((deprecated("Please use esp_clk_tree_enable_src instead")));
void periph_rtc_mpll_release(void) __attribute__((deprecated("Please use esp_clk_tree_release_src instead")));
/**
* @brief Configure MPLL frequency
components/esp_hw_support/include/esp_private/esp_clk_tree_common.h
+45 -10
View File
@@ -8,6 +8,7 @@
#include <stdbool.h>
#include <stdint.h>
#include "esp_attr.h"
#include "esp_clk_tree.h"
#include "soc/soc_caps.h"
@@ -81,19 +82,53 @@ uint32_t esp_clk_tree_lp_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision);
/**
* @brief Enable / Disable the clock gate of the clock source
* @brief Increment or decrement a clock source reference count
*
* @note The clock enable status is maintained by reference counter and
* its status is not reset after software restart.
* The source is enabled on the 0→1 transition and disabled on the 1→0
* transition. Callers should use `esp_clk_tree_acquire_src` and
* `esp_clk_tree_release_src`.
*
* @param[in] clk_src Clock source available to modules, in soc_module_clk_t
* @param[in] enable Enable / Disable the clock gate
* @param[in] acquire true to acquire, false to release
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable);
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire);
/**
* @brief Acquire a clock source
*
* @note The clock source is enabled on the first acquisition. Acquisitions
* must be balanced by calls to `esp_clk_tree_release_src`.
*
* @param[in] clk_src Clock source available to modules, in soc_module_clk_t
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
FORCE_INLINE_ATTR esp_err_t esp_clk_tree_acquire_src(soc_module_clk_t clk_src)
{
return esp_clk_tree_manage_src(clk_src, true);
}
/**
* @brief Release a clock source
*
* @note The clock source is disabled after its final reference is released.
*
* @param[in] clk_src Clock source available to modules, in soc_module_clk_t
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
FORCE_INLINE_ATTR esp_err_t esp_clk_tree_release_src(soc_module_clk_t clk_src)
{
return esp_clk_tree_manage_src(clk_src, false);
}
/**
* @brief Initialize clock circuit power and clock gating
@@ -135,14 +170,14 @@ bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit);
/**
* @brief Enable APLL power if it has not enabled
*
* @note Do not use this function in applications or drivers, please use `esp_clk_tree_enable_src` instead.
* @note Do not use this function in applications or drivers, please use `esp_clk_tree_acquire_src` instead.
*/
void esp_clk_tree_apll_acquire(void);
/**
* @brief Shut down APLL power if no peripherals using APLL
*
* @note Do not use this function in applications or drivers, please use `esp_clk_tree_enable_src` instead.
* @note Do not use this function in applications or drivers, please use `esp_clk_tree_release_src` instead.
*/
void esp_clk_tree_apll_release(void);
@@ -172,7 +207,7 @@ esp_err_t esp_clk_tree_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_
*
* Programs the upstream-mux of `clk_src` (e.g. `SOC_MOD_CLK_PLL_F50M`) to
* source from `upstream` (e.g. `SOC_MOD_CLK_MPLL`, `SOC_MOD_CLK_CPLL`). The
* clock must already be acquired via `esp_clk_tree_enable_src(clk_src, true)`.
* clock must already be acquired via `esp_clk_tree_acquire_src(clk_src)`.
*
* Use `esp_clk_tree_src_set_freq_hz()` afterwards to choose the divider for
* the desired output frequency. If `select_upstream` is not called before
@@ -210,14 +245,14 @@ esp_err_t esp_clk_tree_src_select_upstream(soc_module_clk_t clk_src,
/**
* @brief Enable MPLL power if it has not enabled
*
* @note Do not use this function in applications or drivers, please use `esp_clk_tree_enable_src` instead.
* @note Do not use this function in applications or drivers, please use `esp_clk_tree_acquire_src` instead.
*/
esp_err_t esp_clk_tree_mpll_acquire(void);
/**
* @brief Shut down MPLL power if no peripherals using MPLL
*
* @note Do not use this function in applications or drivers, please use `esp_clk_tree_enable_src` instead.
* @note Do not use this function in applications or drivers, please use `esp_clk_tree_release_src` instead.
*/
void esp_clk_tree_mpll_release(void);
components/esp_hw_support/include/esp_private/esp_clk_tree_derived.h
+2 -2
View File
@@ -86,7 +86,7 @@ const esp_clk_tree_derived_clk_desc_t *esp_clk_tree_get_derived_clk_desc(soc_mod
* @brief Acquire a derived clock (refcount-based)
*
* Increments the descriptor's reference counter and enables the gate on the
* first acquire. Public callers should use `esp_clk_tree_enable_src(clk, true)`
* first acquire. Public callers should use `esp_clk_tree_acquire_src(clk)`
* which dispatches here for any clock with a registered descriptor.
*/
esp_err_t esp_clk_tree_derived_clk_acquire(soc_module_clk_t clk_src);
@@ -95,7 +95,7 @@ esp_err_t esp_clk_tree_derived_clk_acquire(soc_module_clk_t clk_src);
* @brief Release a derived clock previously acquired
*
* Decrements the descriptor's reference counter and disables the gate on the
* last release. Public callers should use `esp_clk_tree_enable_src(clk, false)`.
* last release. Public callers should use `esp_clk_tree_release_src(clk)`.
*/
esp_err_t esp_clk_tree_derived_clk_release(soc_module_clk_t clk_src);
components/esp_hw_support/include/esp_private/regi2c_ctrl.h
+5 -1
View File
@@ -33,7 +33,11 @@ extern "C" {
static inline __attribute__((always_inline)) void ANA_I2C_SRC_CLOCK_ENABLE(bool enable) {
#if SOC_CLK_ANA_I2C_MST_DEPENDS_ON_MODEM_APB
esp_clk_tree_enable_src(SOC_MOD_CLK_MODEM_APB, enable);
if (enable) {
esp_clk_tree_acquire_src(SOC_MOD_CLK_MODEM_APB);
} else {
esp_clk_tree_release_src(SOC_MOD_CLK_MODEM_APB);
}
#endif
}
components/esp_hw_support/linker.lf
+1 -1
View File
@@ -13,7 +13,7 @@ entries:
cpu: esp_cpu_compare_and_set (noflash)
esp_memory_utils (noflash)
clk_utils (noflash)
esp_clk_tree: esp_clk_tree_enable_src (noflash)
esp_clk_tree: esp_clk_tree_manage_src (noflash)
esp_clk_tree:esp_clk_tree_port_is_power_on (noflash)
esp_clk_tree_common:esp_clk_tree_is_power_on (noflash)
if RTC_CLK_FUNC_IN_IRAM = y:
components/esp_hw_support/modem/modem_clock.c
+1 -1
View File
@@ -48,7 +48,7 @@ modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(voi
modem_clock_hal.syscon_dev = &MODEM_SYSCON;
modem_clock_hal.lpcon_dev = &MODEM_LPCON;
#if SOC_CLOCK_TREE_MANAGEMENT_SUPPORTED
ESP_ERROR_CHECK(esp_clk_tree_enable_src(SOC_MOD_CLK_MODEM_APB, true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src(SOC_MOD_CLK_MODEM_APB));
#endif
}
return &modem_clock_context;
components/esp_hw_support/modem/port/esp32s31/modem_clock_impl.c
+2 -2
View File
@@ -215,11 +215,11 @@ static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, boo
static void IRAM_ATTR modem_clock_soc_pll_source_cg_configure(modem_clock_context_t *ctx, bool enable)
{
if (enable) {
ESP_ERROR_CHECK(esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F160M));
}
modem_clock_hal_enable_soc_pll_source_cg(ctx->hal, enable);
if (!enable) {
ESP_ERROR_CHECK(esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, false));
ESP_ERROR_CHECK(esp_clk_tree_release_src(SOC_MOD_CLK_PLL_F160M));
}
}
#endif
components/esp_hw_support/port/esp32/esp_clk_tree.c
+5 -5
View File
@@ -111,7 +111,7 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
return false; // TODO: PM-653
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
@@ -120,7 +120,7 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
// APLL has its own reference counting
if (clk_src == SOC_MOD_CLK_APLL) {
if (enable) {
if (acquire) {
esp_clk_tree_apll_acquire();
} else {
esp_clk_tree_apll_release();
@@ -129,7 +129,7 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -139,10 +139,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST:
enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
break;
default:
break;
components/esp_hw_support/port/esp32c2/esp_clk_tree.c
+4 -4
View File
@@ -91,7 +91,7 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
return false; // TODO: PM-653
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
@@ -99,7 +99,7 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -109,10 +109,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST:
enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
break;
default:
break;
components/esp_hw_support/port/esp32c3/esp_clk_tree.c
+4 -4
View File
@@ -91,7 +91,7 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
return false; // TODO: PM-653
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
@@ -99,7 +99,7 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -109,10 +109,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST:
enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
break;
default:
break;
components/esp_hw_support/port/esp32c5/esp_clk_tree.c
+13 -13
View File
@@ -129,7 +129,7 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
clk_src_en_func(enable); \
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
@@ -140,7 +140,7 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -150,18 +150,18 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST: enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable(); break;
case SOC_MOD_CLK_PLL_F12M: ENABLE_CLK_GATE(clk_gate_ll_ref_12m_clk_en, enable); break;
case SOC_MOD_CLK_PLL_F20M: ENABLE_CLK_GATE(clk_gate_ll_ref_20m_clk_en, enable); break;
case SOC_MOD_CLK_PLL_F40M: ENABLE_CLK_GATE(clk_gate_ll_ref_40m_clk_en, enable); break;
case SOC_MOD_CLK_PLL_F48M: ENABLE_CLK_GATE(clk_gate_ll_ref_48m_clk_en, enable); break;
case SOC_MOD_CLK_PLL_F60M: ENABLE_CLK_GATE(clk_gate_ll_ref_60m_clk_en, enable); break;
case SOC_MOD_CLK_PLL_F80M: ENABLE_CLK_GATE(clk_gate_ll_ref_80m_clk_en, enable); break;
case SOC_MOD_CLK_PLL_F120M: ENABLE_CLK_GATE(clk_gate_ll_ref_120m_clk_en, enable); break;
case SOC_MOD_CLK_PLL_F160M: ENABLE_CLK_GATE(clk_gate_ll_ref_160m_clk_en, enable); break;
case SOC_MOD_CLK_PLL_F240M: ENABLE_CLK_GATE(clk_gate_ll_ref_240m_clk_en, enable); break;
case SOC_MOD_CLK_RC_FAST: acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable(); break;
case SOC_MOD_CLK_PLL_F12M: ENABLE_CLK_GATE(clk_gate_ll_ref_12m_clk_en, acquire); break;
case SOC_MOD_CLK_PLL_F20M: ENABLE_CLK_GATE(clk_gate_ll_ref_20m_clk_en, acquire); break;
case SOC_MOD_CLK_PLL_F40M: ENABLE_CLK_GATE(clk_gate_ll_ref_40m_clk_en, acquire); break;
case SOC_MOD_CLK_PLL_F48M: ENABLE_CLK_GATE(clk_gate_ll_ref_48m_clk_en, acquire); break;
case SOC_MOD_CLK_PLL_F60M: ENABLE_CLK_GATE(clk_gate_ll_ref_60m_clk_en, acquire); break;
case SOC_MOD_CLK_PLL_F80M: ENABLE_CLK_GATE(clk_gate_ll_ref_80m_clk_en, acquire); break;
case SOC_MOD_CLK_PLL_F120M: ENABLE_CLK_GATE(clk_gate_ll_ref_120m_clk_en, acquire); break;
case SOC_MOD_CLK_PLL_F160M: ENABLE_CLK_GATE(clk_gate_ll_ref_160m_clk_en, acquire); break;
case SOC_MOD_CLK_PLL_F240M: ENABLE_CLK_GATE(clk_gate_ll_ref_240m_clk_en, acquire); break;
default: break;
}
}
components/esp_hw_support/port/esp32c5/rtc_clk.c
+4 -3
View File
@@ -24,6 +24,7 @@
#include "soc/chip_revision.h"
#include "esp_attr.h"
#include "esp_private/esp_pmu.h"
#include "esp_private/esp_clk_tree_common.h"
ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk");
@@ -331,7 +332,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_start(soc_cpu_clk_src_
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ);
}
#ifndef BOOTLOADER_BUILD
esp_clk_tree_enable_src((new_src == SOC_CPU_CLK_SRC_PLL_F240M) ? SOC_MOD_CLK_PLL_F240M : SOC_MOD_CLK_PLL_F160M, true);
esp_clk_tree_acquire_src((new_src == SOC_CPU_CLK_SRC_PLL_F240M) ? SOC_MOD_CLK_PLL_F240M : SOC_MOD_CLK_PLL_F160M);
#endif
}
}
@@ -340,7 +341,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_end(soc_cpu_clk_src_t
{
if ((old_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_src == SOC_CPU_CLK_SRC_PLL_F240M)) {
#ifndef BOOTLOADER_BUILD
esp_clk_tree_enable_src((old_src == SOC_CPU_CLK_SRC_PLL_F240M) ? SOC_MOD_CLK_PLL_F240M : SOC_MOD_CLK_PLL_F160M, false);
esp_clk_tree_release_src((old_src == SOC_CPU_CLK_SRC_PLL_F240M) ? SOC_MOD_CLK_PLL_F240M : SOC_MOD_CLK_PLL_F160M);
#endif
if ((new_src != SOC_CPU_CLK_SRC_PLL_F160M) && (new_src != SOC_CPU_CLK_SRC_PLL_F240M) && !s_bbpll_digi_consumers_ref_count && !fast_switching) {
// We don't turn off the bbpll if some consumers depend on bbpll
@@ -459,7 +460,7 @@ FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
#ifndef BOOTLOADER_BUILD
if (old_cpu_clk_src != SOC_MOD_CLK_XTAL) {
esp_clk_tree_enable_src(old_cpu_clk_src, false);
esp_clk_tree_release_src(old_cpu_clk_src);
}
#endif
s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
components/esp_hw_support/port/esp32c6/esp_clk_tree.c
+4 -4
View File
@@ -91,7 +91,7 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
return false; // TODO: PM-653
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
@@ -99,7 +99,7 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -109,10 +109,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST:
enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
break;
default:
break;
components/esp_hw_support/port/esp32c61/esp_clk_tree.c
+4 -4
View File
@@ -91,14 +91,14 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
return false; // TODO: PM-653
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
return ESP_OK;
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -108,10 +108,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST:
enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
break;
default:
break;
components/esp_hw_support/port/esp32h2/esp_clk_tree.c
+4 -4
View File
@@ -88,14 +88,14 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
return false; // TODO: PM-653
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
return ESP_OK;
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -105,10 +105,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST:
enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
break;
default:
break;
components/esp_hw_support/port/esp32h21/esp_clk_tree.c
+8 -8
View File
@@ -203,15 +203,15 @@ void esp_clk_tree_initialize(void)
s_clk_tree_initialized = true;
#if CONFIG_USJ_ENABLE_USB_SERIAL_JTAG || CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
/* Bootloader / USJ may keep PLL_F48M on; declare a permanent hold. */
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F48M, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F48M);
#endif
/* Flash + CPU: sync clk_tree refs with HW already selected at boot.
* Flash uses gated F64M; CPU holds the ungated XTAL_X2 / PLL root, not the F64M / F96M gates. */
esp_clk_tree_enable_src(SOC_MOD_CLK_XTAL_X2_F64M, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_XTAL_X2_F64M);
if (cpu_src == SOC_CPU_CLK_SRC_PLL) {
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_BBPLL);
} else if (cpu_src == SOC_CPU_CLK_SRC_XTAL_X2) {
esp_clk_tree_enable_src(SOC_MOD_CLK_XTAL_X2, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_XTAL_X2);
}
}
@@ -312,7 +312,7 @@ FORCE_INLINE_ATTR esp_err_t esp_clk_tree_enable_gated_clk(const esp_clk_tree_gat
return ESP_OK;
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID || clk_src == SOC_MOD_CLK_XTAL) {
/* Not managed by esp_clk_tree */
@@ -326,10 +326,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_clk_tree_gated_clk_id_t gated_clk_id;
switch (clk_src) {
case SOC_MOD_CLK_XTAL_X2:
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, acquire);
return ESP_OK;
case SOC_MOD_CLK_BBPLL:
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, enable);
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, acquire);
return ESP_OK;
// case SOC_MOD_CLK_RC_FAST: gated_clk_id = ESP_CLK_TREE_GATED_CLK_RC_FAST; break;
case SOC_MOD_CLK_PLL_F48M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F48M; break;
@@ -338,5 +338,5 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
default:
return ESP_OK;
}
return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], enable);
return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], acquire);
}
components/esp_hw_support/port/esp32h21/rtc_clk.c
+4 -4
View File
@@ -288,7 +288,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_start(soc_cpu_clk_src_
bool need_configure = false;
if (!s_is_pll_acquired) {
need_configure = !esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL);
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_BBPLL);
s_is_pll_acquired = true;
}
if (need_configure || (s_cur_pll_freq != (int)new_src_freq_mhz)) {
@@ -296,7 +296,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_start(soc_cpu_clk_src_
}
} else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) {
if (!s_is_xtal_x2_acquired) {
esp_clk_tree_enable_src(SOC_MOD_CLK_XTAL_X2, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_XTAL_X2);
s_is_xtal_x2_acquired = true;
}
}
@@ -308,14 +308,14 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_end(soc_cpu_clk_src_t
{
if ((old_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
assert(s_is_pll_acquired);
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, false);
esp_clk_tree_release_src(SOC_MOD_CLK_BBPLL);
s_is_pll_acquired = false;
if (!esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL)) {
s_cur_pll_freq = 0;
}
} else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) {
assert(s_is_xtal_x2_acquired);
esp_clk_tree_enable_src(SOC_MOD_CLK_XTAL_X2, false);
esp_clk_tree_release_src(SOC_MOD_CLK_XTAL_X2);
s_is_xtal_x2_acquired = false;
}
}
components/esp_hw_support/port/esp32h4/esp_clk_tree.c
+8 -8
View File
@@ -206,15 +206,15 @@ void esp_clk_tree_initialize(void)
s_clk_tree_initialized = true;
#if CONFIG_USJ_ENABLE_USB_SERIAL_JTAG || CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
/* Bootloader / USJ may keep PLL_F48M on; declare a permanent hold. */
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F48M, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F48M);
#endif
/* Flash + CPU: sync clk_tree refs with HW already selected at boot.
* Flash uses gated F64M; CPU holds the ungated XTAL_X2 / PLL root, not the F64M / F96M gates. */
esp_clk_tree_enable_src(SOC_MOD_CLK_XTAL_X2_F64M, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_XTAL_X2_F64M);
if (cpu_src == SOC_CPU_CLK_SRC_PLL) {
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_BBPLL);
} else if (cpu_src == SOC_CPU_CLK_SRC_XTAL_X2) {
esp_clk_tree_enable_src(SOC_MOD_CLK_XTAL_X2, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_XTAL_X2);
}
}
@@ -317,7 +317,7 @@ FORCE_INLINE_ATTR esp_err_t esp_clk_tree_enable_gated_clk(const esp_clk_tree_gat
return ESP_OK;
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID || clk_src == SOC_MOD_CLK_XTAL) {
/* Not managed by esp_clk_tree */
@@ -331,10 +331,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_clk_tree_gated_clk_id_t gated_clk_id;
switch (clk_src) {
case SOC_MOD_CLK_XTAL_X2:
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, acquire);
return ESP_OK;
case SOC_MOD_CLK_BBPLL:
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, enable);
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, acquire);
return ESP_OK;
// case SOC_MOD_CLK_RC_FAST: gated_clk_id = ESP_CLK_TREE_GATED_CLK_RC_FAST; break;
case SOC_MOD_CLK_XTAL_X2_F32M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_XTAL_X2_F32M; break;
@@ -344,5 +344,5 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
default:
return ESP_OK;
}
return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], enable);
return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], acquire);
}
components/esp_hw_support/port/esp32h4/rtc_clk.c
+4 -4
View File
@@ -288,7 +288,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_start(soc_cpu_clk_src_
bool need_configure = false;
if (!s_is_pll_acquired) {
need_configure = !esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL);
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_BBPLL);
s_is_pll_acquired = true;
}
if (need_configure || (s_cur_pll_freq != (int)new_src_freq_mhz)) {
@@ -296,7 +296,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_start(soc_cpu_clk_src_
}
} else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) {
if (!s_is_xtal_x2_acquired) {
esp_clk_tree_enable_src(SOC_MOD_CLK_XTAL_X2, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_XTAL_X2);
s_is_xtal_x2_acquired = true;
}
}
@@ -308,14 +308,14 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_end(soc_cpu_clk_src_t
{
if ((old_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
assert(s_is_pll_acquired);
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, false);
esp_clk_tree_release_src(SOC_MOD_CLK_BBPLL);
s_is_pll_acquired = false;
if (!esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL)) {
s_cur_pll_freq = 0;
}
} else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) {
assert(s_is_xtal_x2_acquired);
esp_clk_tree_enable_src(SOC_MOD_CLK_XTAL_X2, false);
esp_clk_tree_release_src(SOC_MOD_CLK_XTAL_X2);
s_is_xtal_x2_acquired = false;
}
}
components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+5 -5
View File
@@ -285,7 +285,7 @@ FORCE_INLINE_ATTR esp_err_t esp_clk_tree_enable_gated_clk(const esp_clk_tree_gat
return ESP_OK;
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID || clk_src == SOC_MOD_CLK_XTAL) {
/* Not managed by esp_clk_tree */
@@ -300,14 +300,14 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
// these clock sources have their own reference counting
switch (clk_src) {
case SOC_MOD_CLK_APLL:
if (enable) {
if (acquire) {
esp_clk_tree_apll_acquire();
} else {
esp_clk_tree_apll_release();
}
return ESP_OK;
case SOC_MOD_CLK_MPLL:
if (enable) {
if (acquire) {
return esp_clk_tree_mpll_acquire();
} else {
esp_clk_tree_mpll_release();
@@ -328,10 +328,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
// refcount/lock engine route through that engine instead of the
// global s_pll_src_cg_ref_cnt array below.
if (esp_clk_tree_get_derived_clk_desc(clk_src) != NULL) {
return enable ? esp_clk_tree_derived_clk_acquire(clk_src)
return acquire ? esp_clk_tree_derived_clk_acquire(clk_src)
: esp_clk_tree_derived_clk_release(clk_src);
}
return ESP_OK;
}
return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], enable);
return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], acquire);
}
components/esp_hw_support/port/esp32s2/esp_clk_tree.c
+5 -5
View File
@@ -109,7 +109,7 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
return false; // TODO: PM-653
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
@@ -118,7 +118,7 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
// APLL has its own reference counting
if (clk_src == SOC_MOD_CLK_APLL) {
if (enable) {
if (acquire) {
esp_clk_tree_apll_acquire();
} else {
esp_clk_tree_apll_release();
@@ -127,7 +127,7 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -137,10 +137,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST:
enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
break;
default:
break;
components/esp_hw_support/port/esp32s3/esp_clk_tree.c
+4 -4
View File
@@ -101,14 +101,14 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
return false; // TODO: PM-653
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) {
// some conditions is legal, e.g. -1 means external clock source
return ESP_OK;
}
int16_t prev_ref_cnt = 0;
if (enable) {
if (acquire) {
prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1);
} else {
prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1);
@@ -118,10 +118,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
return ESP_OK;
}
}
if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) {
if ((prev_ref_cnt == 0 && acquire) || (prev_ref_cnt == 1 && !acquire)) {
switch (clk_src) {
case SOC_MOD_CLK_RC_FAST:
enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
acquire ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable();
break;
default:
break;
components/esp_hw_support/port/esp32s31/esp_clk_tree.c
+12 -12
View File
@@ -404,17 +404,17 @@ void esp_clk_tree_initialize(void)
s_clk_tree_initialized = true;
#if CONFIG_USJ_ENABLE_USB_SERIAL_JTAG || CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
/* Bootloader / USJ may keep BBPLL 480M on; declare a permanent hold. */
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_BBPLL);
#endif
#if CONFIG_ESP_ENABLE_PVT
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_BBPLL);
#endif
/* Flash + CPU: sync clk_tree refs with HW already selected at boot. */
esp_clk_tree_enable_src((soc_module_clk_t)flash_clk_src, true);
esp_clk_tree_acquire_src((soc_module_clk_t)flash_clk_src);
if (cpu_src == SOC_CPU_CLK_SRC_CPLL) {
esp_clk_tree_enable_src(SOC_MOD_CLK_CPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_CPLL);
} else if (cpu_src == SOC_CPU_CLK_SRC_PLL_F240M) {
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F240M);
}
}
@@ -539,7 +539,7 @@ FORCE_INLINE_ATTR esp_err_t esp_clk_tree_enable_gated_clk(const esp_clk_tree_gat
return ESP_OK;
}
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
esp_err_t esp_clk_tree_manage_src(soc_module_clk_t clk_src, bool acquire)
{
if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID || clk_src == SOC_MOD_CLK_XTAL) {
/* Not managed by esp_clk_tree*/
@@ -554,24 +554,24 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
// these clock sources have their own reference counting
switch (clk_src) {
case SOC_MOD_CLK_APLL:
if (enable) {
if (acquire) {
esp_clk_tree_apll_acquire();
} else {
esp_clk_tree_apll_release();
}
return ESP_OK;
case SOC_MOD_CLK_MPLL:
if (enable) {
if (acquire) {
return esp_clk_tree_mpll_acquire();
} else {
esp_clk_tree_mpll_release();
return ESP_OK;
}
case SOC_MOD_CLK_BBPLL:
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, enable);
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, acquire);
return ESP_OK;
case SOC_MOD_CLK_CPLL:
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_CPLL, enable);
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_CPLL, acquire);
return ESP_OK;
case SOC_MOD_CLK_RC_FAST: gated_clk_id = ESP_CLK_TREE_GATED_CLK_RC_FAST; break;
case SOC_MOD_CLK_PLL_F20M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F20M; break;
@@ -582,10 +582,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
default:
// Derived PLL clocks (PLL_F25M/F50M/F80M) use the shared derived-clk engine.
if (esp_clk_tree_get_derived_clk_desc(clk_src) != NULL) {
return enable ? esp_clk_tree_derived_clk_acquire(clk_src)
return acquire ? esp_clk_tree_derived_clk_acquire(clk_src)
: esp_clk_tree_derived_clk_release(clk_src);
}
return ESP_OK;
}
return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], enable);
return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], acquire);
}
components/esp_hw_support/port/esp32s31/pmu_pvt.c
+3 -2
View File
@@ -17,6 +17,7 @@
#include "pmu_param.h"
#include "esp_rom_sys.h"
#include "esp_private/esp_pmu.h"
#include "esp_private/esp_clk_tree_common.h"
#include "soc/regi2c_dig_reg.h"
#include "regi2c_ctrl.h"
#include "soc/rtc.h"
@@ -162,7 +163,7 @@ void pvt_auto_dbias_enable(bool enable)
if (pvt_enable_flag == true) {
return;
}
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_BBPLL);
pvt_auto_dbias_init();
charge_pump_init();
pvt_func_enable(true);
@@ -174,7 +175,7 @@ void pvt_auto_dbias_enable(bool enable)
}
charge_pump_enable(false);
pvt_func_enable(false);
esp_clk_tree_enable_src(SOC_MOD_CLK_BBPLL, false);
esp_clk_tree_release_src(SOC_MOD_CLK_BBPLL);
pvt_enable_flag = false;
}
}
components/esp_hw_support/port/esp32s31/rtc_clk.c
+4 -4
View File
@@ -352,7 +352,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_start(soc_cpu_clk_src_
bool need_configure = false;
if (!s_is_cpll_acquired) {
need_configure = !esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_CPLL);
esp_clk_tree_enable_src(SOC_MOD_CLK_CPLL, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_CPLL);
s_is_cpll_acquired = true;
}
if (need_configure || (s_cur_cpll_freq != (int)new_src_freq_mhz)) {
@@ -360,7 +360,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_start(soc_cpu_clk_src_
}
} else if (new_src == SOC_CPU_CLK_SRC_PLL_F240M) {
if (!s_is_pll_f240m_acquired) {
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F240M);
s_is_pll_f240m_acquired = true;
}
s_cur_bbpll_freq = CLK_LL_PLL_480M_FREQ_MHZ;
@@ -385,7 +385,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_end(soc_cpu_clk_src_t
}
if (old_src == SOC_CPU_CLK_SRC_CPLL) {
assert(s_is_cpll_acquired);
esp_clk_tree_enable_src(SOC_MOD_CLK_CPLL, false);
esp_clk_tree_release_src(SOC_MOD_CLK_CPLL);
s_is_cpll_acquired = false;
if (!esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_CPLL)) {
s_cur_cpll_freq = 0;
@@ -393,7 +393,7 @@ static void rtc_clk_update_pll_state_on_cpu_src_switching_end(soc_cpu_clk_src_t
} else if (old_src == SOC_CPU_CLK_SRC_PLL_F240M) {
assert(s_is_pll_f240m_acquired);
s_is_pll_f240m_acquired = false;
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, false);
esp_clk_tree_release_src(SOC_MOD_CLK_PLL_F240M);
if (!esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL)) {
s_cur_bbpll_freq = 0;
}
components/esp_hw_support/port/esp_clk_tree_common.c
+1 -1
View File
@@ -402,7 +402,7 @@ end:
* change.
*
* Public API entry points:
* - `esp_clk_tree_enable_src(clk, true/false)` -> acquire / release
* - `esp_clk_tree_acquire_src/release(clk)` -> acquire / release
* - `esp_clk_tree_src_select_upstream(clk, src)` -> mux selection
* - `esp_clk_tree_src_set_freq_hz(clk, hz, &real)` -> divider selection
* The engine functions below are the internal targets the per-target
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c
+2 -2
View File
@@ -144,7 +144,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
rtc_clk_cpu_freq_set_config(&new_config);
esp_clk_tree_enable_src((soc_module_clk_t)UART_SCLK_DEFAULT, true);
esp_clk_tree_acquire_src((soc_module_clk_t)UART_SCLK_DEFAULT);
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT);
uint32_t sclk_freq;
@@ -161,7 +161,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
// return old freq.
esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
rtc_clk_cpu_freq_set_config(&old_config);
esp_clk_tree_enable_src((soc_module_clk_t)UART_SCLK_DEFAULT, true);
esp_clk_tree_acquire_src((soc_module_clk_t)UART_SCLK_DEFAULT);
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT);
uint32_t sclk_freq;
components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c
+4 -4
View File
@@ -49,11 +49,11 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc
phy_clk_src = MIPI_DSI_PHY_PLLREF_CLK_SRC_DEFAULT;
#endif
}
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)phy_clk_src, true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)phy_clk_src), err, TAG, "clock source enable failed");
dsi_bus->phy_pllref_clk_src = (soc_module_clk_t)phy_clk_src;
// always use the default clock source for the DSI PHY configuration
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)MIPI_DSI_PHY_CFG_CLK_SRC_DEFAULT, true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)MIPI_DSI_PHY_CFG_CLK_SRC_DEFAULT), err, TAG, "clock source enable failed");
dsi_bus->phy_cfg_clk_src = (soc_module_clk_t)MIPI_DSI_PHY_CFG_CLK_SRC_DEFAULT;
// enable the clock source for DSI PHY
@@ -151,11 +151,11 @@ esp_err_t esp_lcd_del_dsi_bus(esp_lcd_dsi_bus_handle_t bus)
mipi_dsi_ll_enable_phy_config_clock(bus_id, false);
}
if (bus->phy_pllref_clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(bus->phy_pllref_clk_src, false);
esp_clk_tree_release_src(bus->phy_pllref_clk_src);
bus->phy_pllref_clk_src = SOC_MOD_CLK_INVALID;
}
if (bus->phy_cfg_clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(bus->phy_cfg_clk_src, false);
esp_clk_tree_release_src(bus->phy_cfg_clk_src);
bus->phy_cfg_clk_src = SOC_MOD_CLK_INVALID;
}
// disable the APB clock for accessing the DSI peripheral registers
components/esp_lcd/dsi/esp_lcd_panel_dpi.c
+2 -2
View File
@@ -262,7 +262,7 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_
// divide the source clock to get the final DPI clock
float dpi_clk_src_freq_mhz = (float)dpi_clk_src_freq_hz / 1000.0f / 1000.0f;
uint32_t dpi_div = mipi_dsi_hal_host_dpi_calculate_divider(hal, dpi_clk_src_freq_mhz, panel_config->dpi_clock_freq_mhz);
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)dpi_clk_src, true), err, TAG, "clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)dpi_clk_src), err, TAG, "clock source enable failed");
dpi_panel->clk_src = (soc_module_clk_t)dpi_clk_src;
// set the clock source, set the divider, and enable the dpi clock
PERIPH_RCC_ATOMIC() {
@@ -377,7 +377,7 @@ static esp_err_t dpi_panel_del(esp_lcd_panel_t *panel)
mipi_dsi_ll_enable_dpi_clock(bus_id, false);
}
if (dpi_panel->clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(dpi_panel->clk_src, false);
esp_clk_tree_release_src(dpi_panel->clk_src);
dpi_panel->clk_src = SOC_MOD_CLK_INVALID;
}
// disable the DSI bridge
components/esp_lcd/i80/esp_lcd_panel_io_i80.c
+6 -6
View File
@@ -189,7 +189,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc
// initialize HAL layer, so we can call LL APIs later
lcd_hal_init(&bus->hal, bus_id);
#if CONFIG_IDF_TARGET_ESP32S31
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT, true), err, TAG, "core clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT), err, TAG, "core clock source enable failed");
core_clk_enabled = true;
#endif
PERIPH_RCC_ATOMIC() {
@@ -272,12 +272,12 @@ err:
free(bus->format_buffer);
}
if (bus->clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(bus->clk_src, false);
esp_clk_tree_release_src(bus->clk_src);
bus->clk_src = SOC_MOD_CLK_INVALID;
}
#if CONFIG_IDF_TARGET_ESP32S31
if (core_clk_enabled) {
esp_clk_tree_enable_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT, false);
esp_clk_tree_release_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT);
}
#endif
#if CONFIG_PM_ENABLE
@@ -300,11 +300,11 @@ esp_err_t esp_lcd_del_i80_bus(esp_lcd_i80_bus_handle_t bus)
lcd_ll_enable_clock(bus->hal.dev, false);
}
if (bus->clk_src != SOC_MOD_CLK_INVALID) {
esp_clk_tree_enable_src(bus->clk_src, false);
esp_clk_tree_release_src(bus->clk_src);
bus->clk_src = SOC_MOD_CLK_INVALID;
}
#if CONFIG_IDF_TARGET_ESP32S31
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT, false), err, TAG, "core clock source disable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_release_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT), err, TAG, "core clock source disable failed");
#endif
#if I80_USE_RETENTION_LINK
const periph_retention_module_t module_id = lcd_i80_reg_retention_info[bus_id].retention_module;
@@ -651,7 +651,7 @@ static void lcd_i80_create_retention_module(esp_lcd_i80_bus_t *bus)
static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_clock_source_t clk_src)
{
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), TAG, "clock source enable failed");
bus->clk_src = (soc_module_clk_t)clk_src;
// get clock source frequency
uint32_t src_clk_hz = 0;
components/esp_lcd/rgb/esp_lcd_panel_rgb.c
+4 -4
View File
@@ -253,12 +253,12 @@ static esp_err_t lcd_rgb_panel_destroy(esp_rgb_panel_t *rgb_panel)
}
#if CONFIG_IDF_TARGET_ESP32S31
if (rgb_panel->flags.core_clk_enabled) {
esp_clk_tree_enable_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT, false);
esp_clk_tree_release_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT);
rgb_panel->flags.core_clk_enabled = 0;
}
#endif
if (rgb_panel->clk_src) {
esp_clk_tree_enable_src(rgb_panel->clk_src, false);
esp_clk_tree_release_src(rgb_panel->clk_src);
}
// force power off LCD trans buffer power
lcd_ll_mem_force_low_power(rgb_panel->hal.dev);
@@ -416,7 +416,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
lcd_hal_context_t *hal = &rgb_panel->hal;
// enable clock
#if CONFIG_IDF_TARGET_ESP32S31
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT, true), err, TAG, "core clock source enable failed");
ESP_GOTO_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)LCD_CORE_CLK_SRC_DEFAULT), err, TAG, "core clock source enable failed");
rgb_panel->flags.core_clk_enabled = 1;
#endif
PERIPH_RCC_ATOMIC() {
@@ -1124,7 +1124,7 @@ static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *rgb_panel, lcd_
{
// get clock source frequency
uint32_t src_clk_hz = 0;
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_acquire_src((soc_module_clk_t)clk_src), TAG, "clock source enable failed");
rgb_panel->clk_src = clk_src;
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz),
TAG, "get clock source frequency failed");
components/esp_pm/pm_impl.c
+1 -1
View File
@@ -1282,7 +1282,7 @@ void esp_pm_impl_init(void)
;
}
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_source, true));
ESP_ERROR_CHECK(esp_clk_tree_acquire_src((soc_module_clk_t)clk_source));
/* When DFS is enabled, override system setting and use REFTICK as UART clock source */
PERIPH_RCC_ATOMIC() {
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
components/esp_security/src/esp32h21/esp_crypto_clk.c
+5 -1
View File
@@ -25,7 +25,11 @@ DEFINE_CRIT_SECTION_LOCK_STATIC(s_crypto_common_clk_mux);
static void esp_crypto_pll_f96m_enable(bool enable)
{
#if !NON_OS_BUILD
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F96M, enable);
if (enable) {
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F96M);
} else {
esp_clk_tree_release_src(SOC_MOD_CLK_PLL_F96M);
}
#else
/* Bootloader: no esp_clk_tree; toggle the ref gate directly. */
_clk_gate_ll_ref_96m_clk_en(enable);
components/esp_security/src/esp32h4/esp_crypto_clk.c
+5 -1
View File
@@ -25,7 +25,11 @@ DEFINE_CRIT_SECTION_LOCK_STATIC(s_crypto_common_clk_mux);
static void esp_crypto_pll_f96m_enable(bool enable)
{
#if !NON_OS_BUILD
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F96M, enable);
if (enable) {
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F96M);
} else {
esp_clk_tree_release_src(SOC_MOD_CLK_PLL_F96M);
}
#else
/* Bootloader: no esp_clk_tree; toggle the ref gate directly. */
_clk_gate_ll_ref_96m_clk_en(enable);
components/esp_security/src/esp32p4/esp_crypto_clk.h
+1 -1
View File
@@ -16,6 +16,6 @@ void esp_crypto_common_clk_enable(bool enable);
static inline void esp_crypto_clk_init(void)
{
// Set crypto clock (`clk_sec`) to use 240M PLL clock
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true);
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F240M);
sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F240M);
}
components/esp_security/src/esp32s31/esp_crypto_clk.c
+5 -1
View File
@@ -27,7 +27,11 @@ DEFINE_CRIT_SECTION_LOCK_STATIC(s_crypto_common_clk_mux);
static void esp_crypto_pll_f240m_enable(bool enable)
{
#if !NON_OS_BUILD
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, enable);
if (enable) {
esp_clk_tree_acquire_src(SOC_MOD_CLK_PLL_F240M);
} else {
esp_clk_tree_release_src(SOC_MOD_CLK_PLL_F240M);
}
#else
/* Bootloader: BBPLL is already on; no esp_clk_tree in NON_OS. */
_clk_gate_ll_ref_240m_clk_en(enable);
components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
+1 -1
View File
@@ -184,7 +184,7 @@ TEST_CASE("light sleep and frequency switching", "[lightsleep]")
#elif SOC_UART_SUPPORT_XTAL_CLK
clk_source = UART_SCLK_XTAL;
#endif
esp_clk_tree_enable_src((soc_module_clk_t)clk_source, true);
esp_clk_tree_acquire_src((soc_module_clk_t)clk_source);
PERIPH_RCC_ATOMIC() {
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
}
components/spi_flash/esp_flash_spi_init.c
+2 -2
View File
@@ -289,7 +289,7 @@ static uint32_t init_gpspi_clock(esp_flash_t *chip, const esp_flash_spi_device_c
uint32_t clk_src_freq = 0;
spi_clock_source_t clk_src = config->clock_source ? config->clock_source : SPI_CLK_SRC_DEFAULT;
esp_clk_tree_enable_src(clk_src, true);
esp_clk_tree_acquire_src(clk_src);
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq);
// Enable GPSPI clock
@@ -354,7 +354,7 @@ static void deinit_gpspi_clock(esp_flash_t *chip)
}
// Disable the clock source
esp_clk_tree_enable_src(chip->clock_source, false);
esp_clk_tree_release_src(chip->clock_source);
#endif // !CONFIG_IDF_TARGET_ESP32
}