Merge branch 'bugfix/timer_group_sleep_retention_esp32s31' into 'master'

fix(drivers): fixed the gptimer/MCPWM sleep retention driver support on esp32s31 Closes IDFGH-17654, IDF-15651, IDF-15647, IDF-15641, IDF-14746, IDF-15644, IDF-15646, and IDF-15649 See merge request espressif/esp-idf!48394
2026-06-04 20:26:38 +03:00 · 2026-05-13 15:56:22 +08:00
parent b7db0a4708 3d452de7a3
commit 7ff718a988
15 changed files with 320 additions and 155 deletions
--- a/components/esp_driver_gptimer/src/gptimer.c
+++ b/components/esp_driver_gptimer/src/gptimer.c
@@ -9,7 +9,6 @@
 #include "driver/gptimer.h"
 #include "gptimer_priv.h"
 #include "esp_memory_utils.h"
-#include "esp_sleep.h"

 static void gptimer_default_isr(void *args);

@@ -156,10 +155,6 @@ esp_err_t gptimer_new_timer(const gptimer_config_t *config, gptimer_handle_t *re
 #if GPTIMER_USE_RETENTION_LINK
        gptimer_create_retention_module(timer);
 #endif // GPTIMER_USE_RETENTION_LINK
-    } else {
-#if !SOC_TIMER_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
-        esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15641
-#endif
    }

    // initialize HAL layer
--- a/components/esp_driver_mcpwm/src/mcpwm_cap.c
+++ b/components/esp_driver_mcpwm/src/mcpwm_cap.c
@@ -10,7 +10,6 @@
 #include "esp_memory_utils.h"
 #include "driver/mcpwm_cap.h"
 #include "driver/gpio.h"
-#include "esp_sleep.h"
 #include "esp_private/gpio.h"

 static void mcpwm_capture_default_isr(void *args);
@@ -74,9 +73,6 @@ esp_err_t mcpwm_new_capture_timer(const mcpwm_capture_timer_config_t *config, mc

 #if !SOC_MCPWM_SUPPORT_SLEEP_RETENTION
    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "register back up is not supported");
-#if SOC_PM_SUPPORT_TOP_PD
-    esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15644
-#endif
 #endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION

    cap_timer = heap_caps_calloc(1, sizeof(mcpwm_cap_timer_t), MCPWM_MEM_ALLOC_CAPS);
--- a/components/esp_driver_mcpwm/src/mcpwm_timer.c
+++ b/components/esp_driver_mcpwm/src/mcpwm_timer.c
@@ -8,7 +8,6 @@
 #include "esp_memory_utils.h"
 #include "hal/mcpwm_ll.h"
 #include "driver/mcpwm_timer.h"
-#include "esp_sleep.h"
 #include "esp_private/mcpwm.h"

 static void mcpwm_timer_default_isr(void *args);
@@ -84,9 +83,6 @@ esp_err_t mcpwm_new_timer(const mcpwm_timer_config_t *config, mcpwm_timer_handle

 #if !SOC_MCPWM_SUPPORT_SLEEP_RETENTION
    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "register back up is not supported");
-#if SOC_PM_SUPPORT_TOP_PD
-    esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15644
-#endif
 #endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION

    timer = heap_caps_calloc(1, sizeof(mcpwm_timer_t), MCPWM_MEM_ALLOC_CAPS);
--- a/components/esp_driver_rmt/src/rmt_rx.c
+++ b/components/esp_driver_rmt/src/rmt_rx.c
@@ -10,7 +10,6 @@
 #include "driver/gpio.h"
 #include "driver/rmt_rx.h"
 #include "rmt_private.h"
-#include "esp_sleep.h"

 static esp_err_t rmt_del_rx_channel(rmt_channel_handle_t channel);
 static esp_err_t rmt_rx_demodulate_carrier(rmt_channel_handle_t channel, const rmt_carrier_config_t *config);
@@ -207,9 +206,6 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_

 #if !SOC_RMT_SUPPORT_SLEEP_RETENTION
    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep");
-#if SOC_PM_SUPPORT_TOP_PD
-    esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15646
-#endif
 #endif // SOC_RMT_SUPPORT_SLEEP_RETENTION

    // allocate channel memory from internal memory because it contains atomic variable
--- a/components/esp_driver_rmt/src/rmt_tx.c
+++ b/components/esp_driver_rmt/src/rmt_tx.c
@@ -11,7 +11,6 @@
 #include "driver/gpio.h"
 #include "driver/rmt_tx.h"
 #include "rmt_private.h"
-#include "esp_sleep.h"

 struct rmt_sync_manager_t {
    rmt_group_t *group;    // which group the synchro belongs to
@@ -274,9 +273,6 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_

 #if !SOC_RMT_SUPPORT_SLEEP_RETENTION
    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep");
-#if SOC_PM_SUPPORT_TOP_PD
-    esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15646
-#endif
 #endif // SOC_RMT_SUPPORT_SLEEP_RETENTION

    // allocate channel memory from internal memory because it contains atomic variable
--- a/components/esp_driver_sdm/src/sdm.c
+++ b/components/esp_driver_sdm/src/sdm.c
@@ -18,7 +18,6 @@
 #include "esp_err.h"
 #include "esp_heap_caps.h"
 #include "esp_log.h"
-#include "esp_sleep.h"
 #include "esp_check.h"
 #include "esp_pm.h"
 #include "esp_clk_tree.h"
@@ -277,9 +276,6 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_
    [[maybe_unused]] bool allow_pd = config->flags.allow_pd == 1;
 #if !SOC_SDM_SUPPORT_SLEEP_RETENTION
    ESP_RETURN_ON_FALSE(allow_pd == false, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep");
-#if SOC_PM_SUPPORT_TOP_PD
-    esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15647
-#endif
 #endif // SOC_SDM_SUPPORT_SLEEP_RETENTION

    // allocate channel memory from internal memory because it contains atomic variable
--- a/components/esp_driver_twai/esp_twai_onchip.c
+++ b/components/esp_driver_twai/esp_twai_onchip.c
@@ -12,7 +12,6 @@
 #include "twai_private.h"
 #include "hal/twai_periph.h"
 #include "hal/twai_hal.h"
-#include "esp_sleep.h"
 #if SOC_HAS(TWAI_FD)
 #include "hal/twaifd_ll.h"
 #endif
@@ -658,9 +657,6 @@ esp_err_t twai_new_node_onchip(const twai_onchip_node_config_t *node_config, twa
    ESP_RETURN_ON_FALSE(!node_config->intr_priority || (BIT(node_config->intr_priority) & ESP_INTR_FLAG_LOWMED), ESP_ERR_INVALID_ARG, TAG, "Invalid intr_priority level");
 #if !SOC_TWAI_SUPPORT_SLEEP_RETENTION
    ESP_RETURN_ON_FALSE(!node_config->flags.sleep_allow_pd, ESP_ERR_NOT_SUPPORTED, TAG, "sleep retention is not supported on this target");
-#if SOC_PM_SUPPORT_TOP_PD
-    esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15649
-#endif
 #endif
    // Allocate TWAI node from internal memory because it contains atomic variable
    twai_onchip_ctx_t *node = heap_caps_calloc(1, sizeof(twai_onchip_ctx_t) + twai_hal_get_mem_requirment(), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
--- a/components/esp_hw_support/debug_probe/debug_probe.c
+++ b/components/esp_hw_support/debug_probe/debug_probe.c
@@ -16,10 +16,8 @@
 #include "soc/soc_caps.h"
 #include "soc/debug_probe_periph.h"
 #include "soc/io_mux_reg.h"
-#if SOC_DEBUG_PROBE_NUM_UNIT >= 2 && SOC_LP_GPIO_MATRIX_SUPPORTED
 #include "driver/rtc_io.h"
 #include "driver/lp_io.h"
-#endif
 #include "hal/debug_probe_ll.h"
 #include "esp_private/debug_probe.h"
 #include "esp_private/gpio.h"
@@ -50,26 +48,17 @@ typedef struct debug_probe_platform_t {

 static debug_probe_platform_t s_platform; // singleton platform

-static esp_err_t connect_probe_out_to_pin(debug_probe_unit_id_t unit_id, int pin, unsigned sig_idx, bool out_inv)
+static esp_err_t connect_probe_out_to_pin(debug_probe_unit_id_t unit_id, int pin, int sig_idx, bool out_inv)
 {
+    uint32_t sig_index = debug_probe_periph_signals.units[unit_id].out_sig[sig_idx];
    if (unit_id == DEBUG_PROBE_UNIT_HP) {
-        esp_err_t ret = gpio_func_sel((gpio_num_t)pin, PIN_FUNC_GPIO);
-        if (ret != ESP_OK) {
-            return ret;
-        }
-        esp_rom_gpio_connect_out_signal(pin, debug_probe_periph_signals.units[0].out_sig[sig_idx], out_inv, false);
-        return ESP_OK;
+        return gpio_matrix_output(pin, sig_index, out_inv, false);
+    } else if (unit_id == DEBUG_PROBE_UNIT_LP) {
+        ESP_RETURN_ON_ERROR(rtc_gpio_init(pin), TAG, "init RTC GPIO %d failed", pin);
+        return lp_gpio_matrix_output(pin, sig_index, out_inv, false);
+    } else {
+        return ESP_ERR_NOT_SUPPORTED;
    }
-#if SOC_DEBUG_PROBE_NUM_UNIT >= 2
-    if (!rtc_gpio_is_valid_gpio((gpio_num_t)pin)) {
-        return ESP_ERR_INVALID_ARG;
-    }
-    esp_err_t ret = rtc_gpio_init((gpio_num_t)pin);
-    return (ret == ESP_OK) ? lp_gpio_connect_out_signal((gpio_num_t)pin,
-            debug_probe_periph_signals.units[1].out_sig[sig_idx], out_inv, false) : ret;
-#else
-    return ESP_ERR_NOT_SUPPORTED;
-#endif
 }

 static esp_err_t debug_probe_unit_destroy(debug_probe_unit_t *unit)
@@ -84,13 +73,11 @@ static esp_err_t debug_probe_unit_destroy(debug_probe_unit_t *unit)
    // disable the probe output
    debug_probe_ll_enable_unit(unit_id, false);
    esp_gpio_revoke(unit->pin_bit_mask);
-#if SOC_DEBUG_PROBE_NUM_UNIT >= 2
    if (unit_id == DEBUG_PROBE_UNIT_LP) {
        for (uint64_t m = unit->pin_bit_mask; m; m &= m - 1) {
            rtc_gpio_deinit((gpio_num_t)(__builtin_ffsll(m) - 1));
        }
    }
-#endif
    // free the memory
    free(unit);
    return ESP_OK;
@@ -135,7 +122,7 @@ esp_err_t debug_probe_new_unit(const debug_probe_unit_config_t *config, debug_pr
        int pin = config->probe_out_gpio_nums[i];
        if (pin >= 0) {
            bool out_inv = !!(config->probe_out_inv_mask & BIT(i));
-            ret = connect_probe_out_to_pin(unit_id, pin, (unsigned)i, out_inv);
+            ret = connect_probe_out_to_pin(unit_id, pin, i, out_inv);
            if (ret != ESP_OK) {
                ESP_LOGE(TAG, "Probe out pin %d failed: %s", pin, esp_err_to_name(ret));
                break;
@@ -218,8 +205,8 @@ esp_err_t debug_probe_new_channel(debug_probe_unit_handle_t unit, const debug_pr

    // one channel can only monitor one target module
    uint8_t target_module = (unit_id == DEBUG_PROBE_UNIT_HP)
-                      ? (uint8_t)config->target_module.hp_target
-                      : (uint8_t)config->target_module.lp_target;
+                            ? (uint8_t)config->target_module.hp_target
+                            : (uint8_t)config->target_module.lp_target;
    debug_probe_ll_channel_set_target_module(unit_id, chan_id, target_module);
    debug_probe_ll_enable_channel(unit_id, chan_id, true);

--- a/components/esp_hw_support/etm/esp_etm.c
+++ b/components/esp_hw_support/etm/esp_etm.c
@@ -18,7 +18,6 @@
 #include "freertos/task.h"
 #include "hal/etm_periph.h"
 #include "esp_log.h"
-#include "esp_sleep.h"
 #include "esp_check.h"
 #include "esp_heap_caps.h"
 #include "esp_etm.h"
@@ -247,9 +246,6 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch
    [[maybe_unused]] bool allow_pd = config->flags.allow_pd == 1;
 #if !SOC_ETM_SUPPORT_SLEEP_RETENTION
    ESP_RETURN_ON_FALSE(allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep");
-#if SOC_PM_SUPPORT_TOP_PD
-    esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15651
-#endif
 #endif // SOC_ETM_SUPPORT_SLEEP_RETENTION

    // allocate channel memory from internal memory because it contains atomic variable
--- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
@@ -759,6 +759,10 @@ config SOC_TIMER_SUPPORT_ETM
    bool
    default y

+config SOC_TIMER_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MWDT_SUPPORT_XTAL
    bool
    default y
@@ -1259,6 +1263,10 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
    bool
    default y

+config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_JPEG_DECODE_SUPPORTED
    bool
    default y
--- a/components/soc/esp32s31/include/soc/soc.h
+++ b/components/soc/esp32s31/include/soc/soc.h
@@ -17,7 +17,6 @@
 #define PRO_CPU_NUM (0)

 #define REG_UART_BASE(i)                        (DR_REG_UART_BASE + (i) * 0x1000)        // UART0 and UART1
-#define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1

 //Registers Operation {{
 #define ETS_UNCACHED_ADDR(addr) (addr)
--- a/components/soc/esp32s31/include/soc/soc_caps.h
+++ b/components/soc/esp32s31/include/soc/soc_caps.h
@@ -306,7 +306,7 @@

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
 #define SOC_TIMER_SUPPORT_ETM             (1)
-// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) // TODO: [ESP32S31] IDF-14746
+#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)

 /*--------------------------- WATCHDOG CAPS ---------------------------------------*/
 #define SOC_MWDT_SUPPORT_XTAL              (1)
@@ -497,7 +497,7 @@
 #define SOC_MCPWM_SUPPORT_ETM                (1)    ///< Support ETM (Event Task Matrix)
 #define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR   (1)    ///< Support event comparator (based on ETM)
 #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP     (1)    ///< Capture timer shares clock with other PWM timers
-// #define SOC_MCPWM_SUPPORT_SLEEP_RETENTION    (1)    ///< Support back up registers before sleep
+#define SOC_MCPWM_SUPPORT_SLEEP_RETENTION    (1)    ///< Support back up registers before sleep

 /*--------------------------- JPEG --------------------------------*/
 #define SOC_JPEG_DECODE_SUPPORTED                 (1)
--- a/components/soc/esp32s31/register/soc/mcpwm_reg.h
+++ b/components/soc/esp32s31/register/soc/mcpwm_reg.h
@@ -1,22 +1,24 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0 OR MIT
 */
+
 #pragma once

-#include "soc/soc.h"
-
-#define REG_MCPWM_BASE(i)       (DR_REG_MCPWM0_BASE + (i) * 0x1000)
+#include "soc/reg_base.h"

 #ifdef __cplusplus
 extern "C" {
 #endif

+// MCPWM base address macro for multi-group support
+#define REG_MCPWM_BASE(i)     (DR_REG_MCPWM0_BASE + (i) * 0x1000)
+
 /** MCPWM_TIMER0_CFG0_REG register
 *  PWM timer0 period and update method configuration register.
 */
-#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x0)
+#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0)
 /** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
 *  Configures the prescaler value of timer0, so that the period of PT0_clk = Period of
 *  PWM_clk * (PWM_TIMER0_PRESCALE + 1)
@@ -48,7 +50,7 @@ extern "C" {
 /** MCPWM_TIMER0_CFG1_REG register
 *  PWM timer0 working mode and start/stop control register.
 */
-#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x4)
+#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x4)
 /** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
 *  Configures whether or not to start/stop PWM timer0.
 *  0: If PWM timer0 starts, then stops at TEZ
@@ -77,7 +79,7 @@ extern "C" {
 /** MCPWM_TIMER0_SYNC_REG register
 *  PWM timer0 sync function configuration register.
 */
-#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0x8)
+#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x8)
 /** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable timer0 reloading with phase on sync input event
 *  is enabled.
@@ -127,7 +129,7 @@ extern "C" {
 /** MCPWM_TIMER0_STATUS_REG register
 *  PWM timer0 status register.
 */
-#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0xc)
+#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xc)
 /** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
 *  Represents current PWM timer0 counter value.
 */
@@ -148,7 +150,7 @@ extern "C" {
 /** MCPWM_TIMER1_CFG0_REG register
 *  PWM timer1 period and update method configuration register.
 */
-#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x10)
+#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x10)
 /** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
 *  Configures the prescaler value of timer1, so that the period of PT0_clk = Period of
 *  PWM_clk * (PWM_TIMER1_PRESCALE + 1)
@@ -180,7 +182,7 @@ extern "C" {
 /** MCPWM_TIMER1_CFG1_REG register
 *  PWM timer1 working mode and start/stop control register.
 */
-#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x14)
+#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x14)
 /** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
 *  Configures whether or not to start/stop PWM timer1.
 *  0: If PWM timer1 starts, then stops at TEZ
@@ -209,7 +211,7 @@ extern "C" {
 /** MCPWM_TIMER1_SYNC_REG register
 *  PWM timer1 sync function configuration register.
 */
-#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x18)
+#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x18)
 /** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable timer1 reloading with phase on sync input event
 *  is enabled.
@@ -259,7 +261,7 @@ extern "C" {
 /** MCPWM_TIMER1_STATUS_REG register
 *  PWM timer1 status register.
 */
-#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x1c)
+#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x1c)
 /** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
 *  Represents current PWM timer1 counter value.
 */
@@ -280,7 +282,7 @@ extern "C" {
 /** MCPWM_TIMER2_CFG0_REG register
 *  PWM timer2 period and update method configuration register.
 */
-#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x20)
+#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x20)
 /** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
 *  Configures the prescaler value of timer2, so that the period of PT0_clk = Period of
 *  PWM_clk * (PWM_TIMER2_PRESCALE + 1)
@@ -312,7 +314,7 @@ extern "C" {
 /** MCPWM_TIMER2_CFG1_REG register
 *  PWM timer2 working mode and start/stop control register.
 */
-#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x24)
+#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x24)
 /** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
 *  Configures whether or not to start/stop PWM timer2.
 *  0: If PWM timer2 starts, then stops at TEZ
@@ -341,7 +343,7 @@ extern "C" {
 /** MCPWM_TIMER2_SYNC_REG register
 *  PWM timer2 sync function configuration register.
 */
-#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x28)
+#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x28)
 /** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable timer2 reloading with phase on sync input event
 *  is enabled.
@@ -391,7 +393,7 @@ extern "C" {
 /** MCPWM_TIMER2_STATUS_REG register
 *  PWM timer2 status register.
 */
-#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x2c)
+#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x2c)
 /** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
 *  Represents current PWM timer2 counter value.
 */
@@ -412,7 +414,7 @@ extern "C" {
 /** MCPWM_TIMER_SYNCI_CFG_REG register
 *  Synchronization input selection register for PWM timers.
 */
-#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x30)
+#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x30)
 /** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
 *  Configures the selection of sync input for PWM timer0.
 *  1: PWM timer0 sync_out
@@ -486,7 +488,7 @@ extern "C" {
 /** MCPWM_OPERATOR_TIMERSEL_REG register
 *  PWM operator's timer select register
 */
-#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x34)
+#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x34)
 /** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
 *  Configures which PWM timer will be the timing reference for PWM operator0.
 *  0: Timer0
@@ -524,7 +526,7 @@ extern "C" {
 /** MCPWM_GEN0_STMP_CFG_REG register
 *  Generator0 time stamp registers A and B transfer status and update method register
 */
-#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x38)
+#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x38)
 /** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures the update method for PWM generator 0 time stamp A's active register.
 *  0: Immediately
@@ -571,7 +573,7 @@ extern "C" {
 /** MCPWM_GEN0_TSTMP_A_REG register
 *  Generator0 time stamp A's shadow register
 */
-#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x3c)
+#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x3c)
 /** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
 *  Configures the value of PWM generator 0 time stamp A's shadow register.
 */
@@ -583,7 +585,7 @@ extern "C" {
 /** MCPWM_GEN0_TSTMP_B_REG register
 *  Generator0 time stamp B's shadow register
 */
-#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x40)
+#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x40)
 /** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
 *  Configures the value of PWM generator 0 time stamp B's shadow register.
 */
@@ -595,7 +597,7 @@ extern "C" {
 /** MCPWM_GEN0_CFG0_REG register
 *  Generator0 fault event T0 and T1 configuration register
 */
-#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x44)
+#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x44)
 /** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures update method for PWM generator 0's active register.
 *  0: Immediately
@@ -636,7 +638,7 @@ extern "C" {
 /** MCPWM_GEN0_FORCE_REG register
 *  Generator0 output signal force mode register.
 */
-#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x48)
+#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x48)
 /** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
 *  Configures update method for continuous software force of PWM generator0.
 *  0: Immediately
@@ -716,7 +718,7 @@ extern "C" {
 /** MCPWM_GEN0_A_REG register
 *  PWM0 output signal A actions configuration register
 */
-#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x4c)
+#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x4c)
 /** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
 *  Configures action on PWM0 A triggered by event TEZ when timer increasing.
 *  0: No change
@@ -853,7 +855,7 @@ extern "C" {
 /** MCPWM_GEN0_B_REG register
 *  PWM0 output signal B actions configuration register
 */
-#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x50)
+#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x50)
 /** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
 *  Configures action on PWM0 B triggered by event TEZ when timer increasing.
 *  0: No change
@@ -990,7 +992,7 @@ extern "C" {
 /** MCPWM_DT0_CFG_REG register
 *  Dead time configuration register
 */
-#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x54)
+#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x54)
 /** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures update method for FED (Falling edge delay) active register.
 *  0: Immediate
@@ -1093,7 +1095,7 @@ extern "C" {
 /** MCPWM_DT0_FED_CFG_REG register
 *  Falling edge delay (FED) shadow register
 */
-#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x58)
+#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58)
 /** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
 *  Configures shadow register for FED.
 */
@@ -1105,7 +1107,7 @@ extern "C" {
 /** MCPWM_DT0_RED_CFG_REG register
 *  Rising edge delay (RED) shadow register
 */
-#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c)
+#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c)
 /** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
 *  Configures shadow register for RED.
 */
@@ -1117,7 +1119,7 @@ extern "C" {
 /** MCPWM_CARRIER0_CFG_REG register
 *  Carrier0 configuration register
 */
-#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x60)
+#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60)
 /** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable carrier0.
 *  0: Bypassed
@@ -1173,7 +1175,7 @@ extern "C" {
 /** MCPWM_FH0_CFG0_REG register
 *  PWM0 A and PWM0 B trip events actions configuration register
 */
-#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x64)
+#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x64)
 /** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable software force cycle-by-cycle mode action.
 *  0: Disable
@@ -1346,7 +1348,7 @@ extern "C" {
 /** MCPWM_FH0_CFG1_REG register
 *  Software triggers for fault handler actions configuration register
 */
-#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x68)
+#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x68)
 /** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
 *  Configures the generation of software one-shot mode action clear. A toggle
 *  (software negate its value) triggers a clear for on going one-shot mode action.
@@ -1385,7 +1387,7 @@ extern "C" {
 /** MCPWM_FH0_STATUS_REG register
 *  Fault events status register
 */
-#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x6c)
+#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x6c)
 /** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
 *  Represents whether or not an cycle-by-cycle mode action is on going.
 *  0:No action
@@ -1408,7 +1410,7 @@ extern "C" {
 /** MCPWM_GEN1_STMP_CFG_REG register
 *  Generator1 time stamp registers A and B transfer status and update method register
 */
-#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x70)
+#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x70)
 /** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures the update method for PWM generator 1 time stamp A's active register.
 *  0: Immediately
@@ -1455,7 +1457,7 @@ extern "C" {
 /** MCPWM_GEN1_TSTMP_A_REG register
 *  Generator1 time stamp A's shadow register
 */
-#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x74)
+#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x74)
 /** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
 *  Configures the value of PWM generator 1 time stamp A's shadow register.
 */
@@ -1467,7 +1469,7 @@ extern "C" {
 /** MCPWM_GEN1_TSTMP_B_REG register
 *  Generator1 time stamp B's shadow register
 */
-#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x78)
+#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x78)
 /** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
 *  Configures the value of PWM generator 1 time stamp B's shadow register.
 */
@@ -1479,7 +1481,7 @@ extern "C" {
 /** MCPWM_GEN1_CFG0_REG register
 *  Generator1 fault event T0 and T1 configuration register
 */
-#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x7c)
+#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x7c)
 /** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures update method for PWM generator 1's active register.
 *  0: Immediately
@@ -1520,7 +1522,7 @@ extern "C" {
 /** MCPWM_GEN1_FORCE_REG register
 *  Generator1 output signal force mode register.
 */
-#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x80)
+#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x80)
 /** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
 *  Configures update method for continuous software force of PWM generator1.
 *  0: Immediately
@@ -1600,7 +1602,7 @@ extern "C" {
 /** MCPWM_GEN1_A_REG register
 *  PWM1 output signal A actions configuration register
 */
-#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x84)
+#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x84)
 /** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
 *  Configures action on PWM1 A triggered by event TEZ when timer increasing.
 *  0: No change
@@ -1737,7 +1739,7 @@ extern "C" {
 /** MCPWM_GEN1_B_REG register
 *  PWM1 output signal B actions configuration register
 */
-#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x88)
+#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x88)
 /** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
 *  Configures action on PWM1 B triggered by event TEZ when timer increasing.
 *  0: No change
@@ -1874,7 +1876,7 @@ extern "C" {
 /** MCPWM_DT1_CFG_REG register
 *  Dead time configuration register
 */
-#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x8c)
+#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x8c)
 /** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures update method for FED (Falling edge delay) active register.
 *  0: Immediate
@@ -1977,7 +1979,7 @@ extern "C" {
 /** MCPWM_DT1_FED_CFG_REG register
 *  Falling edge delay (FED) shadow register
 */
-#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x90)
+#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90)
 /** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
 *  Configures shadow register for FED.
 */
@@ -1989,7 +1991,7 @@ extern "C" {
 /** MCPWM_DT1_RED_CFG_REG register
 *  Rising edge delay (RED) shadow register
 */
-#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x94)
+#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94)
 /** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
 *  Configures shadow register for RED.
 */
@@ -2001,7 +2003,7 @@ extern "C" {
 /** MCPWM_CARRIER1_CFG_REG register
 *  Carrier1 configuration register
 */
-#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x98)
+#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98)
 /** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable carrier1.
 *  0: Bypassed
@@ -2057,7 +2059,7 @@ extern "C" {
 /** MCPWM_FH1_CFG0_REG register
 *  PWM1 A and PWM1 B trip events actions configuration register
 */
-#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0x9c)
+#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x9c)
 /** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable software force cycle-by-cycle mode action.
 *  0: Disable
@@ -2230,7 +2232,7 @@ extern "C" {
 /** MCPWM_FH1_CFG1_REG register
 *  Software triggers for fault handler actions configuration register
 */
-#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa0)
+#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa0)
 /** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
 *  Configures the generation of software one-shot mode action clear. A toggle
 *  (software negate its value) triggers a clear for on going one-shot mode action.
@@ -2269,7 +2271,7 @@ extern "C" {
 /** MCPWM_FH1_STATUS_REG register
 *  Fault events status register
 */
-#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa4)
+#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa4)
 /** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
 *  Represents whether or not an cycle-by-cycle mode action is on going.
 *  0:No action
@@ -2292,7 +2294,7 @@ extern "C" {
 /** MCPWM_GEN2_STMP_CFG_REG register
 *  Generator2 time stamp registers A and B transfer status and update method register
 */
-#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xa8)
+#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xa8)
 /** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures the update method for PWM generator 2 time stamp A's active register.
 *  0: Immediately
@@ -2339,7 +2341,7 @@ extern "C" {
 /** MCPWM_GEN2_TSTMP_A_REG register
 *  Generator2 time stamp A's shadow register
 */
-#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xac)
+#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xac)
 /** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
 *  Configures the value of PWM generator 2 time stamp A's shadow register.
 */
@@ -2351,7 +2353,7 @@ extern "C" {
 /** MCPWM_GEN2_TSTMP_B_REG register
 *  Generator2 time stamp B's shadow register
 */
-#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb0)
+#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb0)
 /** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
 *  Configures the value of PWM generator 2 time stamp B's shadow register.
 */
@@ -2363,7 +2365,7 @@ extern "C" {
 /** MCPWM_GEN2_CFG0_REG register
 *  Generator2 fault event T0 and T1 configuration register
 */
-#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb4)
+#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb4)
 /** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures update method for PWM generator 2's active register.
 *  0: Immediately
@@ -2404,7 +2406,7 @@ extern "C" {
 /** MCPWM_GEN2_FORCE_REG register
 *  Generator2 output signal force mode register.
 */
-#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xb8)
+#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xb8)
 /** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
 *  Configures update method for continuous software force of PWM generator2.
 *  0: Immediately
@@ -2484,7 +2486,7 @@ extern "C" {
 /** MCPWM_GEN2_A_REG register
 *  PWM2 output signal A actions configuration register
 */
-#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xbc)
+#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xbc)
 /** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
 *  Configures action on PWM2 A triggered by event TEZ when timer increasing.
 *  0: No change
@@ -2621,7 +2623,7 @@ extern "C" {
 /** MCPWM_GEN2_B_REG register
 *  PWM2 output signal B actions configuration register
 */
-#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc0)
+#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc0)
 /** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
 *  Configures action on PWM2 B triggered by event TEZ when timer increasing.
 *  0: No change
@@ -2758,7 +2760,7 @@ extern "C" {
 /** MCPWM_DT2_CFG_REG register
 *  Dead time configuration register
 */
-#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc4)
+#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc4)
 /** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
 *  Configures update method for FED (Falling edge delay) active register.
 *  0: Immediate
@@ -2861,7 +2863,7 @@ extern "C" {
 /** MCPWM_DT2_FED_CFG_REG register
 *  Falling edge delay (FED) shadow register
 */
-#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xc8)
+#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8)
 /** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
 *  Configures shadow register for FED.
 */
@@ -2873,7 +2875,7 @@ extern "C" {
 /** MCPWM_DT2_RED_CFG_REG register
 *  Rising edge delay (RED) shadow register
 */
-#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc)
+#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc)
 /** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
 *  Configures shadow register for RED.
 */
@@ -2885,7 +2887,7 @@ extern "C" {
 /** MCPWM_CARRIER2_CFG_REG register
 *  Carrier2 configuration register
 */
-#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd0)
+#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0)
 /** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable carrier2.
 *  0: Bypassed
@@ -2941,7 +2943,7 @@ extern "C" {
 /** MCPWM_FH2_CFG0_REG register
 *  PWM2 A and PWM2 B trip events actions configuration register
 */
-#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd4)
+#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd4)
 /** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable software force cycle-by-cycle mode action.
 *  0: Disable
@@ -3114,7 +3116,7 @@ extern "C" {
 /** MCPWM_FH2_CFG1_REG register
 *  Software triggers for fault handler actions configuration register
 */
-#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xd8)
+#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xd8)
 /** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
 *  Configures the generation of software one-shot mode action clear. A toggle
 *  (software negate its value) triggers a clear for on going one-shot mode action.
@@ -3153,7 +3155,7 @@ extern "C" {
 /** MCPWM_FH2_STATUS_REG register
 *  Fault events status register
 */
-#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xdc)
+#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xdc)
 /** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
 *  Represents whether or not an cycle-by-cycle mode action is on going.
 *  0:No action
@@ -3176,7 +3178,7 @@ extern "C" {
 /** MCPWM_FAULT_DETECT_REG register
 *  Fault detection configuration and status register
 */
-#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe0)
+#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe0)
 /** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable event_f0 generation.
 *  0: Disable
@@ -3262,7 +3264,7 @@ extern "C" {
 /** MCPWM_CAP_TIMER_CFG_REG register
 *  Capture timer configuration register
 */
-#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe4)
+#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe4)
 /** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable capture timer increment.
 *  0: Disable
@@ -3310,7 +3312,7 @@ extern "C" {
 /** MCPWM_CAP_TIMER_PHASE_REG register
 *  Capture timer sync phase register
 */
-#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xe8)
+#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xe8)
 /** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
 *  Configures phase value for capture timer sync operation.
 */
@@ -3322,7 +3324,7 @@ extern "C" {
 /** MCPWM_CAP_CH0_CFG_REG register
 *  Capture channel 0 configuration register
 */
-#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xec)
+#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xec)
 /** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable capture on channel 0.
 *  0: Disable
@@ -3372,7 +3374,7 @@ extern "C" {
 /** MCPWM_CAP_CH1_CFG_REG register
 *  Capture channel 1 configuration register
 */
-#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf0)
+#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0)
 /** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable capture on channel 1.
 *  0: Disable
@@ -3422,7 +3424,7 @@ extern "C" {
 /** MCPWM_CAP_CH2_CFG_REG register
 *  Capture channel 2 configuration register
 */
-#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf4)
+#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4)
 /** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable capture on channel 2.
 *  0: Disable
@@ -3472,7 +3474,7 @@ extern "C" {
 /** MCPWM_CAP_CH0_REG register
 *  CAP0 capture value register
 */
-#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xf8)
+#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xf8)
 /** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
 *  Represents value of last capture on CAP0
 */
@@ -3484,7 +3486,7 @@ extern "C" {
 /** MCPWM_CAP_CH1_REG register
 *  CAP1 capture value register
 */
-#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0xfc)
+#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0xfc)
 /** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
 *  Represents value of last capture on CAP1
 */
@@ -3496,7 +3498,7 @@ extern "C" {
 /** MCPWM_CAP_CH2_REG register
 *  CAP2 capture value register
 */
-#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x100)
+#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x100)
 /** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
 *  Represents value of last capture on CAP2
 */
@@ -3508,7 +3510,7 @@ extern "C" {
 /** MCPWM_CAP_STATUS_REG register
 *  Last capture trigger edge information register
 */
-#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x104)
+#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x104)
 /** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
 *  Represents edge of last capture trigger on channel0.
 *  0: Posedge
@@ -3540,7 +3542,7 @@ extern "C" {
 /** MCPWM_UPDATE_CFG_REG register
 *  Generator Update configuration register
 */
-#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x108)
+#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x108)
 /** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
 *  Configures whether or not to enable global update for all active registers in MCPWM
 *  module.
@@ -3621,7 +3623,7 @@ extern "C" {
 /** MCPWM_INT_ENA_REG register
 *  Interrupt enable register
 */
-#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x10c)
+#define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x10c)
 /** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
 */
@@ -3842,7 +3844,7 @@ extern "C" {
 /** MCPWM_INT_RAW_REG register
 *  Interrupt raw status register
 */
-#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x110)
+#define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x110)
 /** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
 *  0 stops.
@@ -4087,7 +4089,7 @@ extern "C" {
 /** MCPWM_INT_ST_REG register
 *  Interrupt masked status register
 */
-#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x114)
+#define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x114)
 /** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
 *  Masked status bit: The masked interrupt status of the interrupt triggered when the
 *  timer 0 stops.
@@ -4332,7 +4334,7 @@ extern "C" {
 /** MCPWM_INT_CLR_REG register
 *  Interrupt clear register
 */
-#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x118)
+#define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x118)
 /** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
 *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
 */
@@ -4553,7 +4555,7 @@ extern "C" {
 /** MCPWM_EVT_EN_REG register
 *  Event enable register
 */
-#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x11c)
+#define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x11c)
 /** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable timer0 stop event generate.
 *  0: Disable
@@ -4828,7 +4830,7 @@ extern "C" {
 /** MCPWM_TASK_EN_REG register
 *  Task enable register
 */
-#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x120)
+#define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120)
 /** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
 *  update task receive.
@@ -5091,7 +5093,7 @@ extern "C" {
 /** MCPWM_EVT_EN2_REG register
 *  Event enable register2
 */
-#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x124)
+#define MCPWM_EVT_EN2_REG(i) (REG_MCPWM_BASE(i) + 0x124)
 /** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
 *  event generate.
@@ -5210,7 +5212,7 @@ extern "C" {
 /** MCPWM_OP0_TSTMP_E1_REG register
 *  Generator0 timer stamp E1 value register
 */
-#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x128)
+#define MCPWM_OP0_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x128)
 /** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
 *  Configures generator0 timer stamp E1 value register
 */
@@ -5222,7 +5224,7 @@ extern "C" {
 /** MCPWM_OP0_TSTMP_E2_REG register
 *  Generator0 timer stamp E2 value register
 */
-#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x12c)
+#define MCPWM_OP0_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x12c)
 /** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
 *  Configures generator0 timer stamp E2 value register
 */
@@ -5234,7 +5236,7 @@ extern "C" {
 /** MCPWM_OP1_TSTMP_E1_REG register
 *  Generator1 timer stamp E1 value register
 */
-#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x130)
+#define MCPWM_OP1_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x130)
 /** MCPWM_OP1_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
 *  Configures generator1 timer stamp E1 value register
 */
@@ -5246,7 +5248,7 @@ extern "C" {
 /** MCPWM_OP1_TSTMP_E2_REG register
 *  Generator1 timer stamp E2 value register
 */
-#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x134)
+#define MCPWM_OP1_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x134)
 /** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
 *  Configures generator1 timer stamp E2 value register
 */
@@ -5258,7 +5260,7 @@ extern "C" {
 /** MCPWM_OP2_TSTMP_E1_REG register
 *  Generator2 timer stamp E1 value register
 */
-#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x138)
+#define MCPWM_OP2_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x138)
 /** MCPWM_OP2_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
 *  Configures generator2 timer stamp E1 value register
 */
@@ -5270,7 +5272,7 @@ extern "C" {
 /** MCPWM_OP2_TSTMP_E2_REG register
 *  Generator2 timer stamp E2 value register
 */
-#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x13c)
+#define MCPWM_OP2_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x13c)
 /** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
 *  Configures generator2 timer stamp E2 value register
 */
@@ -5282,7 +5284,7 @@ extern "C" {
 /** MCPWM_CLK_REG register
 *  Global configuration register
 */
-#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x140)
+#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x140)
 /** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to open register clock gate.
 *  0: Open the clock gate only when application writes registers
@@ -5296,7 +5298,7 @@ extern "C" {
 /** MCPWM_VERSION_REG register
 *  Version register.
 */
-#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x144)
+#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x144)
 /** MCPWM_DATE : R/W; bitpos: [27:0]; default: 37761424;
 *  Configures the version.
 */
@@ -5308,7 +5310,7 @@ extern "C" {
 /** MCPWM_TIMER0_CFG2_REG register
 *  PWM timer0 timestamp a configuration register.
 */
-#define MCPWM_TIMER0_CFG2_REG (DR_REG_MCPWM_BASE + 0x14c)
+#define MCPWM_TIMER0_CFG2_REG(i) (REG_MCPWM_BASE(i) + 0x14c)
 /** MCPWM_TIMER0_A : R/W; bitpos: [15:0]; default: 255;
 *  Configures the timestamp a shadow of PWM timer0
 */
@@ -5342,7 +5344,7 @@ extern "C" {
 /** MCPWM_TIMER0_CFG3_REG register
 *  PWM timer0 timestamp b configuration register.
 */
-#define MCPWM_TIMER0_CFG3_REG (DR_REG_MCPWM_BASE + 0x150)
+#define MCPWM_TIMER0_CFG3_REG(i) (REG_MCPWM_BASE(i) + 0x150)
 /** MCPWM_TIMER0_B : R/W; bitpos: [15:0]; default: 255;
 *  Configures the timestamp b shadow of PWM timer0
 */
@@ -5376,7 +5378,7 @@ extern "C" {
 /** MCPWM_TIMER1_CFG2_REG register
 *  PWM timer1 timestamp a configuration register.
 */
-#define MCPWM_TIMER1_CFG2_REG (DR_REG_MCPWM_BASE + 0x154)
+#define MCPWM_TIMER1_CFG2_REG(i) (REG_MCPWM_BASE(i) + 0x154)
 /** MCPWM_TIMER1_A : R/W; bitpos: [15:0]; default: 255;
 *  Configures the timestamp a shadow of PWM timer1
 */
@@ -5410,7 +5412,7 @@ extern "C" {
 /** MCPWM_TIMER1_CFG3_REG register
 *  PWM timer1 timestamp b configuration register.
 */
-#define MCPWM_TIMER1_CFG3_REG (DR_REG_MCPWM_BASE + 0x158)
+#define MCPWM_TIMER1_CFG3_REG(i) (REG_MCPWM_BASE(i) + 0x158)
 /** MCPWM_TIMER1_B : R/W; bitpos: [15:0]; default: 255;
 *  Configures the timestamp b shadow of PWM timer1
 */
@@ -5444,7 +5446,7 @@ extern "C" {
 /** MCPWM_TIMER2_CFG2_REG register
 *  PWM timer2 timestamp a configuration register.
 */
-#define MCPWM_TIMER2_CFG2_REG (DR_REG_MCPWM_BASE + 0x15c)
+#define MCPWM_TIMER2_CFG2_REG(i) (REG_MCPWM_BASE(i) + 0x15c)
 /** MCPWM_TIMER2_A : R/W; bitpos: [15:0]; default: 255;
 *  Configures the timestamp a shadow of PWM timer2
 */
@@ -5478,7 +5480,7 @@ extern "C" {
 /** MCPWM_TIMER2_CFG3_REG register
 *  PWM timer2 timestamp b configuration register.
 */
-#define MCPWM_TIMER2_CFG3_REG (DR_REG_MCPWM_BASE + 0x160)
+#define MCPWM_TIMER2_CFG3_REG(i) (REG_MCPWM_BASE(i) + 0x160)
 /** MCPWM_TIMER2_B : R/W; bitpos: [15:0]; default: 255;
 *  Configures the timestamp b shadow of PWM timer2
 */
--- a/components/soc/esp32s31/register/soc/timer_group_reg.h
+++ b/components/soc/esp32s31/register/soc/timer_group_reg.h
@@ -1,15 +1,20 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0 OR MIT
 */
+
 #pragma once

-#include "soc/soc.h"
+#include "soc/reg_base.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif

+/* Multi-instance reg base macro */
+#define REG_TIMG_BASE(i)                        (DR_REG_TIMERG0_BASE + (i)*0x1000)
+
 /** TIMG_T0CONFIG_REG register
 *  Timer 0 configuration register
 */
@@ -180,6 +185,176 @@ extern "C" {
 #define TIMG_T0_LOAD_V  0xFFFFFFFFU
 #define TIMG_T0_LOAD_S  0

+/** TIMG_T1CONFIG_REG register
+ *  Timer 1 configuration register
+ */
+#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
+/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable the timer 1 alarm function. This bit will be
+ *  automatically cleared once an alarm occurs.
+ *  0: Disable
+ *  1: Enable
+ */
+#define TIMG_T1_ALARM_EN    (BIT(10))
+#define TIMG_T1_ALARM_EN_M  (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
+#define TIMG_T1_ALARM_EN_V  0x00000001U
+#define TIMG_T1_ALARM_EN_S  10
+/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
+ *  Configures whether or not to reset the timer 1 's clock divider counter.
+ *  0: No effect
+ *  1: Reset
+ */
+#define TIMG_T1_DIVCNT_RST    (BIT(12))
+#define TIMG_T1_DIVCNT_RST_M  (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
+#define TIMG_T1_DIVCNT_RST_V  0x00000001U
+#define TIMG_T1_DIVCNT_RST_S  12
+/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
+ *  Represents the timer 1 clock (T1_clk) prescaler value.
+ */
+#define TIMG_T1_DIVIDER    0x0000FFFFU
+#define TIMG_T1_DIVIDER_M  (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
+#define TIMG_T1_DIVIDER_V  0x0000FFFFU
+#define TIMG_T1_DIVIDER_S  13
+/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
+ *  Configures whether or not to enable the timer 1 auto-reload function at the time of
+ *  alarm.
+ *  0: No effect
+ *  1: Enable
+ */
+#define TIMG_T1_AUTORELOAD    (BIT(29))
+#define TIMG_T1_AUTORELOAD_M  (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
+#define TIMG_T1_AUTORELOAD_V  0x00000001U
+#define TIMG_T1_AUTORELOAD_S  29
+/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
+ *  Configures the counting direction of the timer 1 time-base counter.
+ *  0: Decrement
+ *  1: Increment
+ */
+#define TIMG_T1_INCREASE    (BIT(30))
+#define TIMG_T1_INCREASE_M  (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
+#define TIMG_T1_INCREASE_V  0x00000001U
+#define TIMG_T1_INCREASE_S  30
+/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
+ *  Configures whether or not to enable the timer 1 time-base counter.
+ *  0: Disable
+ *  1: Enable
+ */
+#define TIMG_T1_EN    (BIT(31))
+#define TIMG_T1_EN_M  (TIMG_T1_EN_V << TIMG_T1_EN_S)
+#define TIMG_T1_EN_V  0x00000001U
+#define TIMG_T1_EN_S  31
+
+/** TIMG_T1LO_REG register
+ *  Timer 1 current value, low 32 bits
+ */
+#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28)
+/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
+ *  Represents the low 32 bits of the time-base counter of timer 1. Valid only after
+ *  writing to TIMG_T1UPDATE_REG.
+ *  Measurement unit: T1_clk
+ */
+#define TIMG_T1_LO    0xFFFFFFFFU
+#define TIMG_T1_LO_M  (TIMG_T1_LO_V << TIMG_T1_LO_S)
+#define TIMG_T1_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LO_S  0
+
+/** TIMG_T1HI_REG register
+ *  Timer 1 current value, high 22 bits
+ */
+#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2c)
+/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
+ *  Represents the high 22 bits of the time-base counter of timer 1. Valid only after
+ *  writing to TIMG_T1UPDATE_REG.
+ *  Measurement unit: T1_clk
+ */
+#define TIMG_T1_HI    0x003FFFFFU
+#define TIMG_T1_HI_M  (TIMG_T1_HI_V << TIMG_T1_HI_S)
+#define TIMG_T1_HI_V  0x003FFFFFU
+#define TIMG_T1_HI_S  0
+
+/** TIMG_T1UPDATE_REG register
+ *  Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG
+ */
+#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30)
+/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  Configures to latch the counter value.
+ *  0: Latch
+ *  1: Latch
+ */
+#define TIMG_T1_UPDATE    (BIT(31))
+#define TIMG_T1_UPDATE_M  (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
+#define TIMG_T1_UPDATE_V  0x00000001U
+#define TIMG_T1_UPDATE_S  31
+
+/** TIMG_T1ALARMLO_REG register
+ *  Timer 1 alarm value, low 32 bits
+ */
+#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34)
+/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the low 32 bits of timer 1 alarm trigger time-base counter value. Valid
+ *  only when TIMG_T1_ALARM_EN is 1.
+ *  Measurement unit: T1_clk
+ */
+#define TIMG_T1_ALARM_LO    0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_M  (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
+#define TIMG_T1_ALARM_LO_V  0xFFFFFFFFU
+#define TIMG_T1_ALARM_LO_S  0
+
+/** TIMG_T1ALARMHI_REG register
+ *  Timer 1 alarm value, high bits
+ */
+#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38)
+/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Configures the high 22 bits of timer 1 alarm trigger time-base counter value. Valid
+ *  only when TIMG_T1_ALARM_EN is 1.
+ *  Measurement unit: T1_clk
+ */
+#define TIMG_T1_ALARM_HI    0x003FFFFFU
+#define TIMG_T1_ALARM_HI_M  (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
+#define TIMG_T1_ALARM_HI_V  0x003FFFFFU
+#define TIMG_T1_ALARM_HI_S  0
+
+/** TIMG_T1LOADLO_REG register
+ *  Timer 1 reload value, low 32 bits
+ */
+#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3c)
+/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  Configures low 32 bits of the value that a reload will load onto timer 1 time-base
+ *  counter.
+ *  Measurement unit: T1_clk
+ */
+#define TIMG_T1_LOAD_LO    0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_M  (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
+#define TIMG_T1_LOAD_LO_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_LO_S  0
+
+/** TIMG_T1LOADHI_REG register
+ *  Timer 1 reload value, high 22 bits
+ */
+#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40)
+/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
+ *  Configures high 22 bits of the value that a reload will load onto timer 1 time-base
+ *  counter.
+ *  Measurement unit: T1_clk
+ */
+#define TIMG_T1_LOAD_HI    0x003FFFFFU
+#define TIMG_T1_LOAD_HI_M  (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
+#define TIMG_T1_LOAD_HI_V  0x003FFFFFU
+#define TIMG_T1_LOAD_HI_S  0
+
+/** TIMG_T1LOAD_REG register
+ *  Write to reload timer from TIMG_T1LOADLO_REG or TIMG_T1LOADHI_REG
+ */
+#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44)
+/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
+ *  Write any value to trigger a timer 1 time-base counter reload.
+ *
+ */
+#define TIMG_T1_LOAD    0xFFFFFFFFU
+#define TIMG_T1_LOAD_M  (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
+#define TIMG_T1_LOAD_V  0xFFFFFFFFU
+#define TIMG_T1_LOAD_S  0
+
 /** TIMG_WDTCONFIG0_REG register
 *  Watchdog timer configuration register
 */
@@ -479,6 +654,13 @@ extern "C" {
 #define TIMG_T0_INT_ENA_M  (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
 #define TIMG_T0_INT_ENA_V  0x00000001U
 #define TIMG_T0_INT_ENA_S  0
+/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable the TIMG_T1_INT interrupt.
+ */
+#define TIMG_T1_INT_ENA    (BIT(1))
+#define TIMG_T1_INT_ENA_M  (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
+#define TIMG_T1_INT_ENA_V  0x00000001U
+#define TIMG_T1_INT_ENA_S  1
 /** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
 *  Write 1 to enable the TIMG_WDT_INT interrupt.
 */
@@ -498,6 +680,13 @@ extern "C" {
 #define TIMG_T0_INT_RAW_M  (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
 #define TIMG_T0_INT_RAW_V  0x00000001U
 #define TIMG_T0_INT_RAW_S  0
+/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit of the TIMG_T1_INT interrupt.
+ */
+#define TIMG_T1_INT_RAW    (BIT(1))
+#define TIMG_T1_INT_RAW_M  (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
+#define TIMG_T1_INT_RAW_V  0x00000001U
+#define TIMG_T1_INT_RAW_S  1
 /** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
 *  The raw interrupt status bit of the TIMG_WDT_INT interrupt.
 */
@@ -517,6 +706,13 @@ extern "C" {
 #define TIMG_T0_INT_ST_M  (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
 #define TIMG_T0_INT_ST_V  0x00000001U
 #define TIMG_T0_INT_ST_S  0
+/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit of the TIMG_T1_INT interrupt.
+ */
+#define TIMG_T1_INT_ST    (BIT(1))
+#define TIMG_T1_INT_ST_M  (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
+#define TIMG_T1_INT_ST_V  0x00000001U
+#define TIMG_T1_INT_ST_S  1
 /** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
 *  The masked interrupt status bit of the TIMG_WDT_INT interrupt.
 */
@@ -536,6 +732,13 @@ extern "C" {
 #define TIMG_T0_INT_CLR_M  (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
 #define TIMG_T0_INT_CLR_V  0x00000001U
 #define TIMG_T0_INT_CLR_S  0
+/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear the TIMG_T1_INT interrupt.
+ */
+#define TIMG_T1_INT_CLR    (BIT(1))
+#define TIMG_T1_INT_CLR_M  (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
+#define TIMG_T1_INT_CLR_V  0x00000001U
+#define TIMG_T1_INT_CLR_S  1
 /** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
 *  Write 1 to clear the TIMG_WDT_INT interrupt.
 */
--- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c
+++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c
@@ -76,7 +76,6 @@
 #define EXAMPLE_I2S_TDM_SLOT_MASK  (I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3)

 /* ES7210 configurations */
-#define EXAMPLE_ES7210_I2C_ADDR    (0x40)
 #define EXAMPLE_ES7210_MIC_GAIN    (30)  // 30db
 #define EXAMPLE_ES7210_MIC_SELECTED (ES7210_SEL_MIC1 | ES7210_SEL_MIC2 | ES7210_SEL_MIC3 | ES7210_SEL_MIC4)