fix(driver_spi): add test for flash encryption config

2026-10-01 18:50:34 +03:00 · 2026-09-01 20:35:42 +08:00
parent 1c52acdf86
commit 7d6790aea0
24 changed files with 118 additions and 16 deletions
@@ -2160,7 +2160,7 @@ TEST_CASE("SPI_Master: PSRAM buffer transaction via EDMA", "[spi]")
        printf("\n==== %s ====\n", i ? "EDMA" : "Auto Malloc");
        trans_cfg.flags = i ? SPI_TRANS_DMA_USE_PSRAM : 0;
        uint32_t before = esp_get_free_heap_size();
-        spi_device_polling_start(dev_handle, &trans_cfg, portMAX_DELAY);
+        TEST_ESP_OK(spi_device_polling_start(dev_handle, &trans_cfg, portMAX_DELAY));
        uint32_t after = esp_get_free_heap_size();
        printf("mem_diff: %ld, trans_len: %d\n", after - before, TEST_EDMA_TRANS_LEN);
 #if !CONFIG_SECURE_FLASH_ENC_ENABLED
@@ -57,6 +57,27 @@ def test_master_single_dev_esp32c5_rev1(case_tester) -> None:  # type: ignore
        case_tester.run_normal_case(case=case, reset=True)


+def get_runner_psram_marks(target: str) -> tuple[pytest.MarkDecorator, ...]:
+    if target == 'esp32s3':
+        return (pytest.mark.flash_encryption_f8r8,)
+    return (pytest.mark.flash_encryption,)
+
+
+@pytest.mark.parametrize(
+    'config, target',
+    [
+        pytest.param('flash_enc', target, marks=get_runner_psram_marks(target))
+        for target in soc_filtered_targets('SOC_PSRAM_DMA_CAPABLE == 1 and SOC_GPSPI_SUPPORTED == 1')
+    ],
+    indirect=True,
+)
+def test_spi_master_flash_encryption(case_tester) -> None:  # type: ignore
+    for case in case_tester.test_menu:
+        if 'test_env' in case.attributes:
+            continue  # If `test_env` is defined, should not run on generic runner
+        case_tester.run_normal_case(case=case, reset=True)
+
+
 # Job for test_env `external_flash` just for esp32 only
@pytest.mark.flash_multi
@pytest.mark.parametrize(
@@ -0,0 +1,10 @@
+CONFIG_SPIRAM=y
+CONFIG_PARTITION_TABLE_OFFSET=0x9000
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
+CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
+CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
+CONFIG_SECURE_BOOT_ALLOW_JTAG=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
+CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
@@ -0,0 +1 @@
+CONFIG_SPIRAM_MODE_OCT=y
@@ -282,8 +282,8 @@ TEST_CASE("test slave using external ram", "[spi]")
 {
    custom_setup((TEST_SPI_PERIPH_NUM >= 2) ? TEST_SLAVE_HOST : 0, TEST_SPI_HOST);

-    uint8_t *slave_ext_tx = heap_caps_aligned_calloc(32, 1, PSRAM_TRANS_LEN, MALLOC_CAP_SPIRAM);
-    uint8_t *slave_ext_rx = heap_caps_aligned_calloc(32, 1, PSRAM_TRANS_LEN, MALLOC_CAP_SPIRAM);
+    uint8_t *slave_ext_tx = heap_caps_calloc(1, PSRAM_TRANS_LEN, MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA);
+    uint8_t *slave_ext_rx = heap_caps_calloc(1, PSRAM_TRANS_LEN, MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA);
    uint8_t *master_tx = heap_caps_malloc(PSRAM_TRANS_LEN, MALLOC_CAP_DMA);
    uint8_t *master_rx = heap_caps_malloc(PSRAM_TRANS_LEN, MALLOC_CAP_DMA);

@@ -31,6 +31,24 @@ def test_slave_single_dev_esp32c5_rev1(case_tester) -> None:  # type: ignore
    case_tester.run_all_normal_cases(reset=True)


+def get_runner_psram_marks(target: str) -> tuple[pytest.MarkDecorator, ...]:
+    if target == 'esp32s3':
+        return (pytest.mark.flash_encryption_f8r8,)
+    return (pytest.mark.flash_encryption,)
+
+
+@pytest.mark.parametrize(
+    'config, target',
+    [
+        pytest.param('flash_enc', target, marks=get_runner_psram_marks(target))
+        for target in soc_filtered_targets('SOC_PSRAM_DMA_CAPABLE == 1 and SOC_GPSPI_SUPPORTED == 1')
+    ],
+    indirect=True,
+)
+def test_spi_slave_flash_encryption(case_tester) -> None:  # type: ignore
+    case_tester.run_all_normal_cases(reset=True)
+
+
@pytest.mark.generic_multi_device
@pytest.mark.parametrize('count, config', [(2, 'release'), (2, 'iram_safe')], indirect=True)
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
@@ -0,0 +1,9 @@
+CONFIG_PARTITION_TABLE_OFFSET=0x9000
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
+CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
+CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
+CONFIG_SECURE_BOOT_ALLOW_JTAG=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
+CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
@@ -0,0 +1,3 @@
+# don't enable s3 psram in default because s3 burger runner don't has psram
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
@@ -6,3 +6,6 @@ CONFIG_COMPILER_OPTIMIZATION_NONE=y
 CONFIG_ESP_IPC_TASK_STACK_SIZE=2048
 # silent the error check, as the error string are stored in rodata, causing RTL check failure
 CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
+
+# ESP32-P4 PSRAM halfsleep code/data is placed in SPM, which overflows with -O0 in this config.
+CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED=n
@@ -532,10 +532,10 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
    same_pin_func_sel(0, TEST_SLAVE_HOST, bus_cfg, slave_hd_cfg.spics_io_num);

    const int send_buf_size = 1024;
-    WORD_ALIGNED_ATTR uint8_t* slave_send_buf = malloc(send_buf_size * 2);
-    WORD_ALIGNED_ATTR uint8_t* master_send_buf = malloc(send_buf_size * 2);
-    WORD_ALIGNED_ATTR uint8_t* slave_recv_buf = malloc(send_buf_size * 2);
-    WORD_ALIGNED_ATTR uint8_t* master_recv_buf = malloc(send_buf_size * 2);
+    uint8_t* slave_send_buf = heap_caps_malloc(send_buf_size * 2, MALLOC_CAP_DMA);
+    uint8_t* master_send_buf = heap_caps_malloc(send_buf_size * 2, MALLOC_CAP_DMA);
+    uint8_t* slave_recv_buf = heap_caps_malloc(send_buf_size * 2, MALLOC_CAP_DMA);
+    uint8_t* master_recv_buf = heap_caps_malloc(send_buf_size * 2, MALLOC_CAP_DMA);

    memset(slave_recv_buf, 0xcc, send_buf_size * 2);
    memset(master_recv_buf, 0xcc, send_buf_size * 2);
@@ -1100,8 +1100,8 @@ TEST_CASE("test slave hd edma segment and append mode", "[spi]")
 {
    uint8_t *mst_tx = heap_caps_malloc(TEST_PSRAM_TRANS_LEN, MALLOC_CAP_DEFAULT);
    uint8_t *mst_rx = heap_caps_malloc(TEST_PSRAM_TRANS_LEN, MALLOC_CAP_DEFAULT);
-    uint8_t *slv_tx = heap_caps_malloc(TEST_PSRAM_TRANS_LEN, MALLOC_CAP_SPIRAM);
-    uint8_t *slv_rx = heap_caps_malloc(TEST_PSRAM_TRANS_LEN, MALLOC_CAP_SPIRAM);
+    uint8_t *slv_tx = heap_caps_malloc(TEST_PSRAM_TRANS_LEN, MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA);
+    uint8_t *slv_rx = heap_caps_malloc(TEST_PSRAM_TRANS_LEN, MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA);
    spi_slave_hd_data_t *ret_trans, tx_data = {
        .data = slv_tx,
        .len = TEST_PSRAM_TRANS_LEN,
@@ -1123,26 +1123,26 @@ TEST_CASE("test slave hd edma segment and append mode", "[spi]")
        bus_cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS;
        spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG();
        slave_hd_cfg.flags |= i ? SPI_SLAVE_HD_APPEND_MODE : 0;
-        TEST_ESP_OK(spi_slave_hd_init(TEST_SLAVE_HOST, &bus_cfg, &slave_hd_cfg));
-        same_pin_func_sel(0, TEST_SLAVE_HOST, bus_cfg, slave_hd_cfg.spics_io_num);
+        TEST_ESP_OK(spi_slave_hd_init(TEST_SPI_HOST, &bus_cfg, &slave_hd_cfg));
+        same_pin_func_sel(0, TEST_SPI_HOST, bus_cfg, slave_hd_cfg.spics_io_num);
        vTaskDelay(1);

-        TEST_ESP_OK(hd_trans[i](TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &tx_data, portMAX_DELAY));
-        TEST_ESP_OK(hd_trans[i](TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &rx_data, portMAX_DELAY));
+        TEST_ESP_OK(hd_trans[i](TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &tx_data, portMAX_DELAY));
+        TEST_ESP_OK(hd_trans[i](TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &rx_data, portMAX_DELAY));

        // tx append transaction
        printf("tx %d bytes\n", TEST_PSRAM_TRANS_LEN);
        essl_sspi_hd_dma_trans_seg(bus_cfg, slave_hd_cfg.spics_io_num, 0, false, mst_tx, TEST_PSRAM_TRANS_LEN, -1);
-        TEST_ESP_OK(hd_get_trans_res[i](TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
+        TEST_ESP_OK(hd_get_trans_res[i](TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));

        // rx append transaction
        printf("rx %d bytes\n", TEST_PSRAM_TRANS_LEN);
        essl_sspi_hd_dma_trans_seg(bus_cfg, slave_hd_cfg.spics_io_num, 0, true, mst_rx, TEST_PSRAM_TRANS_LEN, -1);
-        TEST_ESP_OK(hd_get_trans_res[i](TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));
+        TEST_ESP_OK(hd_get_trans_res[i](TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));

        spitest_cmp_or_dump(slv_rx, mst_tx, TEST_PSRAM_TRANS_LEN);
        spitest_cmp_or_dump(mst_rx, slv_tx, TEST_PSRAM_TRANS_LEN);
-        spi_slave_hd_deinit(TEST_SLAVE_HOST);
+        spi_slave_hd_deinit(TEST_SPI_HOST);
        printf("test done\n");
    }
    free(mst_tx);
@@ -25,6 +25,24 @@ def test_slave_hd_single_dev_esp32c5_rev1(case_tester) -> None:  # type: ignore
    case_tester.run_all_normal_cases(reset=True, timeout=180)


+def get_runner_psram_marks(target: str) -> tuple[pytest.MarkDecorator, ...]:
+    if target == 'esp32s3':
+        return (pytest.mark.flash_encryption_f8r8,)
+    return (pytest.mark.flash_encryption,)
+
+
+@pytest.mark.parametrize(
+    'config, target',
+    [
+        pytest.param('flash_enc', target, marks=get_runner_psram_marks(target))
+        for target in soc_filtered_targets('SOC_PSRAM_DMA_CAPABLE == 1 and SOC_SPI_SUPPORT_SLAVE_HD_VER2 == 1')
+    ],
+    indirect=True,
+)
+def test_spi_slave_hd_flash_encryption(case_tester) -> None:  # type: ignore
+    case_tester.run_all_normal_cases(reset=True, timeout=180)
+
+
@pytest.mark.generic_multi_device
@pytest.mark.parametrize('count, config', [(2, 'release')], indirect=True)
@idf_parametrize('target', soc_filtered_targets('SOC_SPI_SUPPORT_SLAVE_HD_VER2 == 1'), indirect=['target'])
@@ -0,0 +1,9 @@
+CONFIG_PARTITION_TABLE_OFFSET=0x9000
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
+CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
+CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
+CONFIG_SECURE_BOOT_ALLOW_JTAG=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
+CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
@@ -0,0 +1,3 @@
+# don't enable s3 psram in default because s3 burger runner don't has psram
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
@@ -0,0 +1,2 @@
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
@@ -0,0 +1 @@
+CONFIG_SPIRAM=y
@@ -0,0 +1 @@
+CONFIG_SPIRAM=y
@@ -0,0 +1 @@
+CONFIG_SPIRAM=y
@@ -0,0 +1 @@
+CONFIG_SPIRAM=y
@@ -0,0 +1 @@
+CONFIG_SPIRAM=y