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Merge branch 'fix/esp_hal_usb_fsls_phy_default_settings' into 'master'

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fix(esp_hal_usb): Fix internal PHY default settings

Closes IDF-15718

See merge request espressif/esp-idf!48764
This commit is contained in:
Peter Marcisovsky
2026-05-22 09:53:44 +02:00
parent bf10423a5b c4b57d67aa
commit 7ac6e821f8
5 changed files with 61 additions and 4 deletions
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16
components/esp_hal_usb/esp32h4/include/hal/usb_wrap_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -172,6 +172,20 @@ FORCE_INLINE_ATTR void usb_wrap_ll_phy_set_tx_edge(usb_wrap_dev_t *hw, bool clk_
(void)clk_neg_edge;
}
/**
* @brief Route internal FSLS PHY AHB/PHY clock gating to DWC2
*
* Clears clock force-on bits so DWC2 can gate the internal PHY clocks during
* port suspend and internal clock gating.
*
* @param hw Start address of the USB Wrap registers
*/
FORCE_INLINE_ATTR void usb_wrap_ll_enable_automatic_phy_control(usb_wrap_dev_t *hw)
{
hw->wrap_otg_conf.wrap_ahb_clk_force_on = 0;
hw->wrap_otg_conf.wrap_phy_clk_force_on = 0;
}
/* ------------------------------ USB PHY Test ------------------------------ */
/**

16
components/esp_hal_usb/esp32p4/include/hal/usb_wrap_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -233,6 +233,20 @@ FORCE_INLINE_ATTR void usb_wrap_ll_phy_test_mode_set_signals(usb_wrap_dev_t *hw,
hw->test_conf.val = test_conf.val;
}
/**
* @brief Route internal FSLS PHY AHB/PHY clock gating to DWC2
*
* Clears clock force-on bits so DWC2 can gate the internal PHY clocks during
* port suspend and internal clock gating.
*
* @param hw Start address of the USB Wrap registers
*/
FORCE_INLINE_ATTR void usb_wrap_ll_enable_automatic_phy_control(usb_wrap_dev_t *hw)
{
hw->otg_conf.ahb_clk_force_on = 0;
hw->otg_conf.phy_clk_force_on = 0;
}
/* ----------------------------- RCC Functions ----------------------------- */
/**

16
components/esp_hal_usb/esp32s2/include/hal/usb_wrap_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -200,6 +200,20 @@ FORCE_INLINE_ATTR void usb_wrap_ll_phy_test_mode_set_signals(usb_wrap_dev_t *hw,
hw->test_conf.val = test_conf.val;
}
/**
* @brief Route internal FSLS PHY AHB/PHY clock gating to DWC2
*
* Clears clock force-on bits so DWC2 can gate the internal PHY clocks during
* port suspend and internal clock gating.
*
* @param hw Start address of the USB Wrap registers
*/
FORCE_INLINE_ATTR void usb_wrap_ll_enable_automatic_phy_control(usb_wrap_dev_t *hw)
{
hw->otg_conf.ahb_clk_force_on = 0;
hw->otg_conf.phy_clk_force_on = 0;
}
/* ----------------------------- RCC Functions ----------------------------- */
/**

16
components/esp_hal_usb/esp32s3/include/hal/usb_wrap_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -209,6 +209,20 @@ FORCE_INLINE_ATTR void usb_wrap_ll_phy_test_mode_set_signals(usb_wrap_dev_t *hw,
hw->test_conf.val = test_conf.val;
}
/**
* @brief Route internal FSLS PHY AHB/PHY clock gating to DWC2
*
* Clears clock force-on bits so DWC2 can gate the internal PHY clocks during
* port suspend and internal clock gating.
*
* @param hw Start address of the USB Wrap registers
*/
FORCE_INLINE_ATTR void usb_wrap_ll_enable_automatic_phy_control(usb_wrap_dev_t *hw)
{
hw->otg_conf.ahb_clk_force_on = 0;
hw->otg_conf.phy_clk_force_on = 0;
}
/* ----------------------------- RCC Functions ----------------------------- */
/**

1
components/esp_hal_usb/usb_wrap_hal.c
View File

@@ -11,6 +11,7 @@ void _usb_wrap_hal_init(usb_wrap_hal_context_t *hal)
hal->dev = &USB_WRAP;
_usb_wrap_ll_enable_bus_clock(true);
_usb_wrap_ll_reset_register();
usb_wrap_ll_enable_automatic_phy_control(hal->dev);
#if !USB_WRAP_LL_EXT_PHY_SUPPORTED
usb_wrap_ll_phy_set_defaults(hal->dev);
#endif