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https://github.com/espressif/esp-idf.git
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refactor(spi_flash): move internal types to private headers and refactor initialization
This commit refactors the SPI flash component to improve encapsulation and
modularity by moving internal types and functions to private headers, and
reorganizing initialization code.
Key changes:
1. Move PSRAM frequency constraint macro from soc_caps.h to mspi_ll.h
- Rename SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED to
MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED
- Move macro definition to chip-specific mspi_ll.h files (C5, C61, H4, P4, S31)
- Update usage in clk_utils.c and esp_flash_spi_init.c
- Remove old macro from all soc_caps.h files
2. Move internal types to private headers
- Move esp_flash_t structure to esp_private/esp_flash_types.h
- Move esp_flash_os_functions_t to esp_private/spi_flash_os.h
- Update all internal files to include private headers
- Keep forward declarations in public esp_flash.h
3. Move chip driver header to internal directory
- Move spi_flash_chip_driver.h to esp_flash_port/spi_flash_chip_driver.h
- Update all references to use new path
- Add esp_private/esp_flash_types.h include to the moved header
4. Refactor initialization functions
- Move init_flash from esp_system/startup_funcs.c to
spi_flash/esp_flash_spi_init.c
- Create new init_pm_flash_freq_limit function in startup_funcs.c
to call esp_pm_flash_freq_limit_init() conditionally
- Update system_init_fn.txt with new function locations
5. Improve API encapsulation
- Replace direct access to esp_flash_t->size in
esp_partition_register_external() with esp_flash_get_size() API
- Move esp_flash_is_quad_mode from inline function to regular function
in esp_flash_api.c
6. Update component dependencies
- Add esp_driver_gpio to spi_flash component PRIV_REQUIRES
- Remove unused includes and clean up header dependencies
These changes improve code organization by clearly separating public APIs
from internal implementation details, making the codebase more maintainable
and reducing the risk of breaking changes to internal structures.
This commit is contained in:
@@ -8,20 +8,24 @@
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#include "esp_flash.h"
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#include "memspi_host_driver.h"
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#include "esp_flash_spi_init.h"
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#include "driver/gpio.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp_log.h"
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#include "esp_heap_caps.h"
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#include "hal/spi_types.h"
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#include "esp_private/spi_share_hw_ctrl.h"
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#include "esp_private/mspi_intr.h"
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#include "esp_ldo_regulator.h"
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#include "hal/spi_flash_hal.h"
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#include "spi_flash_chip_driver.h"
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#include "esp_flash_port/spi_flash_chip_driver.h"
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#include "hal/gpio_hal.h"
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#include "esp_flash_internal.h"
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#include "esp_rom_gpio.h"
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/cache_utils.h"
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#include "esp_private/log_util.h"
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#include "esp_private/startup_internal.h"
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#include "esp_spi_flash_counters.h"
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#include "esp_rom_spiflash.h"
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#include "bootloader_flash.h"
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@@ -29,13 +33,10 @@
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#include "esp_private/esp_clk_tree_common.h"
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#include "clk_ctrl_os.h"
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#include "soc/soc_caps.h"
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#include "hal/mspi_ll.h"
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__attribute__((unused)) static const char TAG[] = "spi_flash";
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#if !CONFIG_SPI_FLASH_AUTO_SUSPEND && !CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM
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#error "CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM cannot be disabled when CONFIG_SPI_FLASH_AUTO_SUSPEND is disabled."
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#endif
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#if CONFIG_SPI_FLASH_ROM_IMPL && (CONFIG_ESPTOOLPY_FLASHSIZE_32MB || CONFIG_ESPTOOLPY_FLASHSIZE_64MB || CONFIG_ESPTOOLPY_FLASHSIZE_128MB)
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#error "Flash chip size equal or over 32MB memory cannot use driver in ROM"
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#endif
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@@ -149,7 +150,7 @@ esp_flash_t *esp_flash_default_chip = NULL;
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// 1. Frequency limit workaround is enabled (CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ)
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// 2. Flash frequency requires timing tuning (80MHz or 120MHz, i.e., > 40MHz)
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// 3. CPU frequency reduction will trigger MSPI timing tuning to enter low speed mode
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// This happens when: SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM &&
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// This happens when: MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM &&
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// (target_cpu_freq < CONFIG_SPIRAM_SPEED)
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// Note: The runtime check for CPU freq < PSRAM speed is done in clk_utils.c,
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// which calls mspi_timing_change_speed_mode_cache_safe(true) to enter low speed mode.
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@@ -356,10 +357,12 @@ static void deinit_gpspi_clock(esp_flash_t *chip)
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// Disable the clock source
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esp_clk_tree_enable_src(chip->clock_source, false);
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#if SOC_SPI_SUPPORT_CLK_RC_FAST
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// Disable RC_FAST clock if it was used
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if ((soc_module_clk_t)chip->clock_source == SOC_MOD_CLK_RC_FAST) {
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if (chip->clock_source == SPI_CLK_SRC_RC_FAST) {
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periph_rtc_dig_clk8m_disable();
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}
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#endif
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#endif // !CONFIG_IDF_TARGET_ESP32
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}
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@@ -553,10 +556,6 @@ esp_err_t esp_flash_init_default_chip(void)
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cfg.auto_waiti_pes = true;
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#endif
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#if CONFIG_SPI_FLASH_SOFTWARE_RESUME
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cfg.software_resume = true;
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#endif
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//the host is already initialized, only do init for the data and load it to the host
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esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg);
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if (err != ESP_OK) {
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@@ -644,3 +643,28 @@ esp_err_t esp_flash_app_init(void)
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err = esp_flash_app_enable_os_functions(&default_chip);
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return err;
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}
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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ESP_SYSTEM_INIT_FN(init_flash, CORE, BIT(0), 130)
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{
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#if CONFIG_SPI_FLASH_ROM_IMPL
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spi_flash_rom_impl_init();
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#endif
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esp_flash_app_init();
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esp_err_t flash_ret = esp_flash_init_default_chip();
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assert(flash_ret == ESP_OK);
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(void)flash_ret;
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#if CONFIG_SPI_FLASH_BROWNOUT_RESET
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spi_flash_needs_reset_check();
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#endif // CONFIG_SPI_FLASH_BROWNOUT_RESET
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// The log library will call the registered callback function to check if the cache is disabled.
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esp_log_util_set_cache_enabled_cb(spi_flash_cache_enabled);
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// Register MSPI Flash interrupt
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#if MSPI_LL_INTR_EVENT_SUPPORTED && MSPI_LL_INTR_SHARED
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esp_mspi_register_isr(NULL);
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#endif
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//else register flash standalone ISR to deal with CPU / API flash access
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return ESP_OK;
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}
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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