diff --git a/components/esp_hal_mspi/esp32c5/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32c5/include/hal/mspi_ll.h index cd2d1d0093b..cd49915fda7 100644 --- a/components/esp_hal_mspi/esp32c5/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32c5/include/hal/mspi_ll.h @@ -39,6 +39,9 @@ extern "C" { #define MSPI_LL_CORE_CLOCK_120_MHZ 120 #define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ +// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow. +#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1 + #define MSPI_LL_ADDR_INT_SUPPORTED 1 #define MSPI_LL_PMS_INT_SUPPORTED 1 #define MSPI_LL_ECC_INT_SUPPORTED 1 diff --git a/components/esp_hal_mspi/esp32c61/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32c61/include/hal/mspi_ll.h index a786c2423ec..71931f72ba1 100644 --- a/components/esp_hal_mspi/esp32c61/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32c61/include/hal/mspi_ll.h @@ -39,6 +39,9 @@ extern "C" { #define MSPI_LL_CORE_CLOCK_120_MHZ 120 #define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ +// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow. +#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1 + #define MSPI_LL_EVENT_SLV_ST_END (1<<3) #define MSPI_LL_EVENT_MST_ST_END (1<<4) #define MSPI_LL_EVENT_ECC_ERR (1<<5) diff --git a/components/esp_hal_mspi/esp32h4/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32h4/include/hal/mspi_ll.h index 8e8b5b51620..30d5593ebbc 100644 --- a/components/esp_hal_mspi/esp32h4/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32h4/include/hal/mspi_ll.h @@ -50,6 +50,9 @@ extern "C" { #endif +// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow. +#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1 + /************************** MSPI pll clock configurations **************************/ /* * @brief Select FLASH clock source diff --git a/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h index 9a71ff66c3b..b089f9a42cc 100644 --- a/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h @@ -47,6 +47,9 @@ extern "C" { #define MSPI_TIMING_LL_MSPI_ID_0 0 #define MSPI_TIMING_LL_MSPI_ID_1 1 +// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow. +#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1 + #define MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV 4 #define MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV 6 #define MSPI_TIMING_LL_FLASH_FDUMMY_RIN_SUPPORTED 1 diff --git a/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h index b06aa93d4c2..8dd83555b5f 100644 --- a/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h @@ -44,6 +44,9 @@ extern "C" { #define MSPI_TIMING_LL_MSPI_ID_0 0 #define MSPI_TIMING_LL_MSPI_ID_1 1 +// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow. +#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1 + #define MSPI_LL_AXI_DISABLE_SUPPORTED 1 #define MSPI_LL_INTR_EVENT_SUPPORTED 1 diff --git a/components/esp_hw_support/clk_utils.c b/components/esp_hw_support/clk_utils.c index 2deb5e78100..d00e781e91a 100644 --- a/components/esp_hw_support/clk_utils.c +++ b/components/esp_hw_support/clk_utils.c @@ -11,7 +11,6 @@ #include "sdkconfig.h" #include "esp_check.h" #include "esp_log.h" -#include "soc/soc_caps.h" #include "soc/rtc.h" #include "hal/mspi_ll.h" #include "hal/clk_tree_ll.h" @@ -38,7 +37,7 @@ void esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(uint32_t targe if (target_cpu_src_freq <= clk_ll_xtal_load_freq_mhz()) { mspi_timing_change_speed_mode_cache_safe(true); } -#elif SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM +#elif MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM /* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU * frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow. */ @@ -60,7 +59,7 @@ void esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(uint32_t target if (target_cpu_src_freq > clk_ll_xtal_load_freq_mhz()) { mspi_timing_change_speed_mode_cache_safe(false); } -#elif SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM +#elif MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM /* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU * frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow. */ diff --git a/components/esp_partition/partition.c b/components/esp_partition/partition.c index d5914b47a56..bbed812d6c0 100644 --- a/components/esp_partition/partition.c +++ b/components/esp_partition/partition.c @@ -477,7 +477,12 @@ esp_err_t esp_partition_register_external(esp_flash_t *flash_chip, size_t offset if (flash_chip == NULL) { flash_chip = esp_flash_default_chip; } - if (offset + size > flash_chip->size) { + uint32_t flash_size = 0; + esp_err_t ret = esp_flash_get_size(flash_chip, &flash_size); + if (ret != ESP_OK) { + return ret; + } + if (offset + size > flash_size) { return ESP_ERR_INVALID_SIZE; } #endif // CONFIG_IDF_TARGET_LINUX diff --git a/components/esp_system/startup_funcs.c b/components/esp_system/startup_funcs.c index 478b99b38a3..529d4286132 100644 --- a/components/esp_system/startup_funcs.c +++ b/components/esp_system/startup_funcs.c @@ -16,18 +16,17 @@ #include "esp_log.h" #include "esp_private/cache_utils.h" #include "spi_flash_mmap.h" -#include "esp_flash_internal.h" #include "esp_private/mspi_intr.h" #include "esp_newlib.h" #include "esp_xt_wdt.h" #include "esp_cpu.h" #include "esp_private/startup_internal.h" +#include "esp_private/pm_impl.h" +#include "freertos/portmacro.h" #include "soc/soc_caps.h" #include "hal/wdt_hal.h" #include "hal/uart_types.h" #include "hal/uart_ll.h" -#include "hal/mspi_ll.h" -#include "freertos/FreeRTOS.h" #if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE #include "private/esp_coexist_internal.h" @@ -106,36 +105,6 @@ ESP_SYSTEM_INIT_FN(init_newlib_time, CORE, BIT(0), 106) return ESP_OK; } -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP -ESP_SYSTEM_INIT_FN(init_flash, CORE, BIT(0), 130) -{ -#if CONFIG_SPI_FLASH_ROM_IMPL - spi_flash_rom_impl_init(); -#endif - - esp_flash_app_init(); - esp_err_t flash_ret = esp_flash_init_default_chip(); - assert(flash_ret == ESP_OK); - (void)flash_ret; -#if CONFIG_SPI_FLASH_BROWNOUT_RESET - spi_flash_needs_reset_check(); -#endif // CONFIG_SPI_FLASH_BROWNOUT_RESET - // The log library will call the registered callback function to check if the cache is disabled. - esp_log_util_set_cache_enabled_cb(spi_flash_cache_enabled); -#if CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED - esp_pm_flash_freq_limit_init(); -#endif // CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED - - // Register MSPI Flash interrupt -#if MSPI_LL_INTR_EVENT_SUPPORTED && MSPI_LL_INTR_SHARED - esp_mspi_register_isr(NULL); -#endif - //else register flash standalone ISR to deal with CPU / API flash access - - return ESP_OK; -} -#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - #if CONFIG_ESP_XT_WDT ESP_SYSTEM_INIT_FN(init_xt_wdt, CORE, BIT(0), 170) { @@ -155,6 +124,14 @@ ESP_SYSTEM_INIT_FN(init_pm, SECONDARY, BIT(0), 201) } #endif // CONFIG_PM_ENABLE +#if CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED +ESP_SYSTEM_INIT_FN(init_pm_flash_freq_limit, SECONDARY, BIT(0), 202) +{ + esp_pm_flash_freq_limit_init(); + return ESP_OK; +} +#endif // CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED + #if SOC_APB_BACKUP_DMA ESP_SYSTEM_INIT_FN(init_apb_dma, SECONDARY, BIT(0), 203) { diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt index ddcdf316d34..bdaeb3f9151 100644 --- a/components/esp_system/system_init_fn.txt +++ b/components/esp_system/system_init_fn.txt @@ -62,7 +62,7 @@ CORE: 118: init_vfs_nullfs in components/vfs/nullfs.c on BIT(0) CORE: 119: init_vfs_console in components/esp_stdio/stdio_vfs.c on BIT(0) CORE: 120: init_libc_stdio in components/esp_libc/src/init.c on BIT(0) -CORE: 130: init_flash in components/esp_system/startup_funcs.c on BIT(0) +CORE: 130: init_flash in components/spi_flash/esp_flash_spi_init.c on BIT(0) CORE: 140: init_efuse in components/efuse/src/esp_efuse_startup.c on BIT(0) CORE: 170: init_xt_wdt in components/esp_system/startup_funcs.c on BIT(0) @@ -114,6 +114,7 @@ SECONDARY: 151: nvs_sec_provider_register_hmac_scheme in components/nvs_sec_prov # the rest of the components which are initialized from startup_funcs.c # [refactor-todo]: move init calls into respective components SECONDARY: 201: init_pm in components/esp_system/startup_funcs.c on BIT(0) +SECONDARY: 202: init_pm_flash_freq_limit in components/esp_system/startup_funcs.c on BIT(0) SECONDARY: 203: init_apb_dma in components/esp_system/startup_funcs.c on BIT(0) SECONDARY: 204: init_coexist in components/esp_system/startup_funcs.c on BIT(0) SECONDARY: 205: init_bootloader_offset in components/esp_system/startup_funcs.c on BIT(0) diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 2895d7454e6..81ef3ec2544 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1027,10 +1027,6 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR bool default y -config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED - bool - default y - config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index d3457ab3564..4fca456f1ba 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -420,7 +420,6 @@ #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) -#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1) #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) #define SOC_MEMSPI_IS_INDEPENDENT 1 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 5bc2543e882..5ad4a8ea8c2 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -779,10 +779,6 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR bool default y -config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED - bool - default y - config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 057a5acfec7..51dc97ff5c4 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -326,7 +326,6 @@ #define SOC_SPI_MEM_SUPPORT_WRAP (1) #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) -#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1) #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) #define SOC_MEMSPI_IS_INDEPENDENT 1 diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index aa967fc440c..064e55eda40 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -763,10 +763,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y -config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED - bool - default y - config SOC_MEMSPI_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index c3e5277df7b..cd2f63affd7 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -379,7 +379,6 @@ #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) -#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1) #define SOC_MEMSPI_IS_INDEPENDENT 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 786878ef340..36c77c634df 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1395,10 +1395,6 @@ config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP bool default y -config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED - bool - default y - config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index a07ce2b2e79..65999a11c3b 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -532,7 +532,6 @@ #define SOC_MEMSPI_TIMING_TUNING_BY_DQS (1) #define SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY (1) #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) -#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_MSPI_HAS_INDEPENT_IOMUX 1 diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 156138b941c..0cca49a64fe 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -279,10 +279,6 @@ config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT bool default y -config SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED - bool - default y - config SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index ec8ed9b7890..797369bd561 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -212,7 +212,6 @@ #define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1 -#define SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED 1 #define SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT 1 diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt index 8708e2026e0..c6848477589 100644 --- a/components/spi_flash/CMakeLists.txt +++ b/components/spi_flash/CMakeLists.txt @@ -60,7 +60,7 @@ else() "spi_flash_os_func_noos.c") list(APPEND srcs ${cache_srcs}) - set(priv_requires bootloader_support soc esp_hal_gpio esp_mm) + set(priv_requires bootloader_support soc esp_hal_gpio esp_driver_gpio esp_mm) if(${target} STREQUAL "esp32s2") list(APPEND priv_requires esp_security) @@ -88,4 +88,6 @@ if(NOT non_os_build AND NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) # will be replaced with MMU requirements idf_component_optional_requires(PRIVATE esp_psram) endif() + # Force linking init_flash ESP_SYSTEM_INIT_FN to ensure it's not discarded by linker + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_flash_app_init") endif() diff --git a/components/spi_flash/esp_flash_api.c b/components/spi_flash/esp_flash_api.c index 49f01927c92..46359b94856 100644 --- a/components/spi_flash/esp_flash_api.c +++ b/components/spi_flash/esp_flash_api.c @@ -10,7 +10,7 @@ #include #include "esp_memory_utils.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "memspi_host_driver.h" #include "esp_log.h" #include "sdkconfig.h" @@ -24,7 +24,6 @@ #include "esp_check.h" #include "hal/efuse_hal.h" #include "soc/chip_revision.h" -#include "esp_cpu.h" #if CONFIG_IDF_TARGET_ESP32S2 #include "esp_crypto_lock.h" // for locking flash encryption peripheral @@ -1611,3 +1610,11 @@ esp_err_t esp_flash_app_disable_protect(bool disable) return esp_flash_app_enable_os_functions(esp_flash_default_chip); } } + +bool esp_flash_is_quad_mode(const esp_flash_t *chip) +{ + if (chip == NULL) { + chip = esp_flash_default_chip; + } + return (chip->read_mode == SPI_FLASH_QIO) || (chip->read_mode == SPI_FLASH_QOUT); +} diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index f55ebdbeb7a..b946198d814 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -8,20 +8,24 @@ #include "esp_flash.h" #include "memspi_host_driver.h" #include "esp_flash_spi_init.h" +#include "driver/gpio.h" #include "esp_rom_gpio.h" #include "esp_rom_efuse.h" #include "esp_log.h" #include "esp_heap_caps.h" #include "hal/spi_types.h" #include "esp_private/spi_share_hw_ctrl.h" +#include "esp_private/mspi_intr.h" #include "esp_ldo_regulator.h" #include "hal/spi_flash_hal.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "hal/gpio_hal.h" #include "esp_flash_internal.h" #include "esp_rom_gpio.h" #include "esp_private/spi_flash_os.h" #include "esp_private/cache_utils.h" +#include "esp_private/log_util.h" +#include "esp_private/startup_internal.h" #include "esp_spi_flash_counters.h" #include "esp_rom_spiflash.h" #include "bootloader_flash.h" @@ -29,13 +33,10 @@ #include "esp_private/esp_clk_tree_common.h" #include "clk_ctrl_os.h" #include "soc/soc_caps.h" +#include "hal/mspi_ll.h" __attribute__((unused)) static const char TAG[] = "spi_flash"; -#if !CONFIG_SPI_FLASH_AUTO_SUSPEND && !CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM -#error "CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM cannot be disabled when CONFIG_SPI_FLASH_AUTO_SUSPEND is disabled." -#endif - #if CONFIG_SPI_FLASH_ROM_IMPL && (CONFIG_ESPTOOLPY_FLASHSIZE_32MB || CONFIG_ESPTOOLPY_FLASHSIZE_64MB || CONFIG_ESPTOOLPY_FLASHSIZE_128MB) #error "Flash chip size equal or over 32MB memory cannot use driver in ROM" #endif @@ -149,7 +150,7 @@ esp_flash_t *esp_flash_default_chip = NULL; // 1. Frequency limit workaround is enabled (CONFIG_SPI_FLASH_FREQ_LIMIT_C5_240MHZ) // 2. Flash frequency requires timing tuning (80MHz or 120MHz, i.e., > 40MHz) // 3. CPU frequency reduction will trigger MSPI timing tuning to enter low speed mode -// This happens when: SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM && +// This happens when: MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM && // (target_cpu_freq < CONFIG_SPIRAM_SPEED) // Note: The runtime check for CPU freq < PSRAM speed is done in clk_utils.c, // which calls mspi_timing_change_speed_mode_cache_safe(true) to enter low speed mode. @@ -356,10 +357,12 @@ static void deinit_gpspi_clock(esp_flash_t *chip) // Disable the clock source esp_clk_tree_enable_src(chip->clock_source, false); +#if SOC_SPI_SUPPORT_CLK_RC_FAST // Disable RC_FAST clock if it was used - if ((soc_module_clk_t)chip->clock_source == SOC_MOD_CLK_RC_FAST) { + if (chip->clock_source == SPI_CLK_SRC_RC_FAST) { periph_rtc_dig_clk8m_disable(); } +#endif #endif // !CONFIG_IDF_TARGET_ESP32 } @@ -553,10 +556,6 @@ esp_err_t esp_flash_init_default_chip(void) cfg.auto_waiti_pes = true; #endif - #if CONFIG_SPI_FLASH_SOFTWARE_RESUME - cfg.software_resume = true; - #endif - //the host is already initialized, only do init for the data and load it to the host esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg); if (err != ESP_OK) { @@ -644,3 +643,28 @@ esp_err_t esp_flash_app_init(void) err = esp_flash_app_enable_os_functions(&default_chip); return err; } + +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP +ESP_SYSTEM_INIT_FN(init_flash, CORE, BIT(0), 130) +{ +#if CONFIG_SPI_FLASH_ROM_IMPL + spi_flash_rom_impl_init(); +#endif + + esp_flash_app_init(); + esp_err_t flash_ret = esp_flash_init_default_chip(); + assert(flash_ret == ESP_OK); + (void)flash_ret; +#if CONFIG_SPI_FLASH_BROWNOUT_RESET + spi_flash_needs_reset_check(); +#endif // CONFIG_SPI_FLASH_BROWNOUT_RESET + // The log library will call the registered callback function to check if the cache is disabled. + esp_log_util_set_cache_enabled_cb(spi_flash_cache_enabled); + // Register MSPI Flash interrupt +#if MSPI_LL_INTR_EVENT_SUPPORTED && MSPI_LL_INTR_SHARED + esp_mspi_register_isr(NULL); +#endif + //else register flash standalone ISR to deal with CPU / API flash access + return ESP_OK; +} +#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP diff --git a/components/spi_flash/include/esp_flash.h b/components/spi_flash/include/esp_flash.h index c3b29269efe..a9b742bd21a 100644 --- a/components/spi_flash/include/esp_flash.h +++ b/components/spi_flash/include/esp_flash.h @@ -10,6 +10,7 @@ #include #include "hal/spi_flash_types.h" #include "esp_blockdev.h" +#include "esp_bit_defs.h" #ifdef __cplusplus extern "C" { @@ -28,91 +29,6 @@ typedef struct { uint32_t size; ///< Size of the region } esp_flash_region_t; -/** @brief OS-level integration hooks for accessing flash chips inside a running OS - * - * It's in the public header because some instances should be allocated statically in the startup - * code. May be updated according to hardware version and new flash chip feature requirements, - * shouldn't be treated as public API. - * - * For advanced developers, you may replace some of them with your implementations at your own - * risk. -*/ -typedef struct { - /** - * Flags for start function - */ - /** Limit CPU frequency during flash operations (ESP32-C5 only, 240MHz). - */ - #define ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ BIT(0) - /** - * Called before commencing any flash operation. Does not need to be - * recursive (ie is called at most once for each call to 'end'). - */ - esp_err_t (*start)(void *arg, uint32_t flags); - - /** Called after completing any flash operation. */ - esp_err_t (*end)(void *arg); - - /** Called before any erase/write operations to check whether the region is limited by the OS */ - esp_err_t (*region_protected)(void* arg, size_t start_addr, size_t size); - - /** Delay for at least 'us' microseconds. Called in between 'start' and 'end'. */ - esp_err_t (*delay_us)(void *arg, uint32_t us); - - /** Called for get temp buffer when buffer from application cannot be directly read into/write from. */ - void *(*get_temp_buffer)(void* arg, size_t reqest_size, size_t* out_size); - - /** Called for release temp buffer. */ - void (*release_temp_buffer)(void* arg, void *temp_buf); - - #define SPI_FLASH_YIELD_REQ_YIELD BIT(0) - #define SPI_FLASH_YIELD_REQ_SUSPEND BIT(1) - - /** Yield to other tasks. Called during erase operations. - * @return ESP_OK means yield needs to be called (got an event to handle), while ESP_ERR_TIMEOUT means skip yield.*/ - esp_err_t (*check_yield)(void *arg, uint32_t chip_status, uint32_t* out_request); - - #define SPI_FLASH_YIELD_STA_RESUME BIT(2) - - /** Yield to other tasks. Called during erase operations. */ - esp_err_t (*yield)(void *arg, uint32_t* out_status); - - /** Called for get system time. */ - int64_t (*get_system_time)(void *arg); - - #define SPI_FLASH_OS_IS_ERASING_STATUS_FLAG BIT(0) - - /** Call to set flash operation status */ - void (*set_flash_op_status)(uint32_t op_status); - -} esp_flash_os_functions_t; - -/** @brief Structure to describe a SPI flash chip connected to the system. - - Structure must be initialized before use (passed to esp_flash_init()). It's in the public - header because some instances should be allocated statically in the startup code. May be - updated according to hardware version and new flash chip feature requirements, shouldn't be - treated as public API. - - For advanced developers, you may replace some of them with your implementations at your own - risk. -*/ -struct esp_flash_t { - spi_flash_host_inst_t* host; ///< Pointer to hardware-specific "host_driver" structure. Must be initialized before used. - const spi_flash_chip_t *chip_drv; ///< Pointer to chip-model-specific "adapter" structure. If NULL, will be detected during initialisation. - - const esp_flash_os_functions_t *os_func; ///< Pointer to os-specific hook structure. Call ``esp_flash_init_os_functions()`` to setup this field, after the host is properly initialized. - void *os_func_data; ///< Pointer to argument for os-specific hooks. Left NULL and will be initialized with ``os_func``. - - esp_flash_io_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called. - uint32_t size; ///< Size of SPI flash in bytes. If 0, size will be detected during initialisation. Note: this stands for the size in the binary image header. If you want to get the flash physical size, please call `esp_flash_get_physical_size`. - uint32_t chip_id; ///< Detected chip id. - uint32_t busy :1; ///< This flag is used to verify chip's status. - uint32_t hpm_dummy_ena :1; ///< This flag is used to verify whether flash works under HPM status. - uint32_t reserved_flags :30; ///< reserved. - int clock_source; ///< Clock source for GPSPI. -}; - /** @brief Initialise SPI flash chip interface. * @@ -384,10 +300,7 @@ extern esp_flash_t *esp_flash_default_chip; * * @return true if flash works in quad mode, otherwise false */ -static inline bool esp_flash_is_quad_mode(const esp_flash_t *chip) -{ - return (chip->read_mode == SPI_FLASH_QIO) || (chip->read_mode == SPI_FLASH_QOUT); -} +bool esp_flash_is_quad_mode(const esp_flash_t *chip); /******************************************************************************* * BDL Functions diff --git a/components/spi_flash/include/esp_flash_internal.h b/components/spi_flash/include/esp_flash_internal.h index b3a87206bfb..66b6e5a5280 100644 --- a/components/spi_flash/include/esp_flash_internal.h +++ b/components/spi_flash/include/esp_flash_internal.h @@ -12,6 +12,7 @@ #include "sdkconfig.h" #include "esp_flash.h" +#include "esp_private/esp_flash_types.h" /** Internal API, don't use in the applications */ diff --git a/components/spi_flash/include/spi_flash_chip_driver.h b/components/spi_flash/include/esp_flash_port/spi_flash_chip_driver.h similarity index 99% rename from components/spi_flash/include/spi_flash_chip_driver.h rename to components/spi_flash/include/esp_flash_port/spi_flash_chip_driver.h index 5e769aa2e01..8b683b1c04d 100644 --- a/components/spi_flash/include/spi_flash_chip_driver.h +++ b/components/spi_flash/include/esp_flash_port/spi_flash_chip_driver.h @@ -7,9 +7,7 @@ #pragma once #include "esp_flash.h" #include "esp_attr.h" - -struct esp_flash_t; -typedef struct esp_flash_t esp_flash_t; +#include "esp_private/esp_flash_types.h" typedef struct spi_flash_chip_t spi_flash_chip_t; diff --git a/components/spi_flash/include/esp_private/esp_flash_types.h b/components/spi_flash/include/esp_private/esp_flash_types.h new file mode 100644 index 00000000000..076e161824d --- /dev/null +++ b/components/spi_flash/include/esp_private/esp_flash_types.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_err.h" +#include +#include +#include "esp_bit_defs.h" +#include "hal/spi_flash_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct spi_flash_chip_t; +typedef struct spi_flash_chip_t spi_flash_chip_t; + +/** @brief OS-level integration hooks for accessing flash chips inside a running OS + * + * This structure is used internally by the SPI flash driver and should not be used directly by applications. + * It's defined here because some instances need to be allocated statically in the startup code. + */ +typedef struct esp_flash_os_functions_t { + /** + * Flags for start function + */ + /** Limit CPU frequency during flash operations (ESP32-C5 only, 240MHz). + */ + #define ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ BIT(0) + /** + * Called before commencing any flash operation. Does not need to be + * recursive (ie is called at most once for each call to 'end'). + */ + esp_err_t (*start)(void *arg, uint32_t flags); + + /** Called after completing any flash operation. */ + esp_err_t (*end)(void *arg); + + /** Called before any erase/write operations to check whether the region is limited by the OS */ + esp_err_t (*region_protected)(void* arg, size_t start_addr, size_t size); + + /** Delay for at least 'us' microseconds. Called in between 'start' and 'end'. */ + esp_err_t (*delay_us)(void *arg, uint32_t us); + + /** Called for get temp buffer when buffer from application cannot be directly read into/write from. */ + void *(*get_temp_buffer)(void* arg, size_t reqest_size, size_t* out_size); + + /** Called for release temp buffer. */ + void (*release_temp_buffer)(void *arg, void *temp_buf); + + #define SPI_FLASH_YIELD_REQ_YIELD BIT(0) + #define SPI_FLASH_YIELD_REQ_SUSPEND BIT(1) + + /** Yield to other tasks. Called during erase operations. + * @return ESP_OK means yield needs to be called (got an event to handle), while ESP_ERR_TIMEOUT means skip yield.*/ + esp_err_t (*check_yield)(void *arg, uint32_t chip_status, uint32_t* out_request); + + #define SPI_FLASH_YIELD_STA_RESUME BIT(2) + + /** Yield to other tasks. Called during erase operations. */ + esp_err_t (*yield)(void *arg, uint32_t* out_status); + + /** Called for get system time. */ + int64_t (*get_system_time)(void *arg); + + #define SPI_FLASH_OS_IS_ERASING_STATUS_FLAG BIT(0) + + /** Call to set flash operation status */ + void (*set_flash_op_status)(uint32_t op_status); + +} esp_flash_os_functions_t; + +/** @brief Structure to describe a SPI flash chip connected to the system. + * + * This structure is used internally by the SPI flash driver and should not be used directly by applications. + * It's defined here because some instances need to be allocated statically in the startup code. + */ +struct esp_flash_t { + spi_flash_host_inst_t* host; ///< Pointer to hardware-specific "host_driver" structure. Must be initialized before used. + const spi_flash_chip_t *chip_drv; ///< Pointer to chip-model-specific "adapter" structure. If NULL, will be detected during initialisation. + + const esp_flash_os_functions_t *os_func; ///< Pointer to os-specific hook structure. Call ``esp_flash_init_os_functions()`` to setup this field, after the host is properly initialized. + void *os_func_data; ///< Pointer to argument for os-specific hooks. Left NULL and will be initialized with ``os_func``. + + esp_flash_io_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called. + uint32_t size; ///< Size of SPI flash in bytes. If 0, size will be detected during initialisation. Note: this stands for the size in the binary image header. If you want to get the flash physical size, please call `esp_flash_get_physical_size`. + uint32_t chip_id; ///< Detected chip id. + uint32_t busy :1; ///< This flag is used to verify chip's status. + uint32_t hpm_dummy_ena :1; ///< This flag is used to verify whether flash works under HPM status. + uint32_t reserved_flags :30; ///< reserved. + int clock_source; ///< Clock source for GPSPI. +}; + +#ifdef __cplusplus +} +#endif + diff --git a/components/spi_flash/include/esp_private/spi_flash_os.h b/components/spi_flash/include/esp_private/spi_flash_os.h index 89ac1e0c3d2..f08f7a6c36b 100644 --- a/components/spi_flash/include/esp_private/spi_flash_os.h +++ b/components/spi_flash/include/esp_private/spi_flash_os.h @@ -15,6 +15,7 @@ #include "esp_rom_spiflash.h" #include "esp_err.h" #include "esp_flash.h" +#include "esp_private/esp_flash_types.h" #include "hal/spi_flash_hal.h" #include "spi_flash_override.h" #include "soc/soc_caps.h" diff --git a/components/spi_flash/include/spi_flash_chip_boya.h b/components/spi_flash/include/spi_flash_chip_boya.h index 02fd05c6b10..810853ed69e 100644 --- a/components/spi_flash/include/spi_flash_chip_boya.h +++ b/components/spi_flash/include/spi_flash_chip_boya.h @@ -8,7 +8,7 @@ #include #include "esp_flash.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "sdkconfig.h" #ifdef CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP diff --git a/components/spi_flash/include/spi_flash_chip_gd.h b/components/spi_flash/include/spi_flash_chip_gd.h index 34b84f841dc..5c4e6d6efd4 100644 --- a/components/spi_flash/include/spi_flash_chip_gd.h +++ b/components/spi_flash/include/spi_flash_chip_gd.h @@ -8,7 +8,7 @@ #include #include "esp_flash.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "sdkconfig.h" diff --git a/components/spi_flash/include/spi_flash_chip_generic.h b/components/spi_flash/include/spi_flash_chip_generic.h index 019a6966a40..2bc219f854b 100644 --- a/components/spi_flash/include/spi_flash_chip_generic.h +++ b/components/spi_flash/include/spi_flash_chip_generic.h @@ -1,22 +1,14 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include #include "esp_flash.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" /* @@ -346,7 +338,7 @@ esp_err_t spi_flash_common_write_status_8b_wrsr2(esp_flash_t* chip, uint32_t sr) * Most chip QE enable follows a common pattern, though commands to read/write * the status register may be different, as well as the position of QE bit. * - * Registers to actually do Quad transtions and command to be sent in reading + * Registers to actually do Quad transitions and command to be sent in reading * should also be configured via * spi_flash_chip_generic_config_host_io_mode(). * diff --git a/components/spi_flash/include/spi_flash_chip_issi.h b/components/spi_flash/include/spi_flash_chip_issi.h index 58a8aac2227..a7e45c50568 100644 --- a/components/spi_flash/include/spi_flash_chip_issi.h +++ b/components/spi_flash/include/spi_flash_chip_issi.h @@ -8,7 +8,7 @@ #include #include "esp_flash.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "sdkconfig.h" diff --git a/components/spi_flash/include/spi_flash_chip_mxic.h b/components/spi_flash/include/spi_flash_chip_mxic.h index cf77ad92d85..276fe44c0ab 100644 --- a/components/spi_flash/include/spi_flash_chip_mxic.h +++ b/components/spi_flash/include/spi_flash_chip_mxic.h @@ -8,7 +8,7 @@ #include #include "esp_flash.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "sdkconfig.h" /** diff --git a/components/spi_flash/include/spi_flash_chip_th.h b/components/spi_flash/include/spi_flash_chip_th.h index bdab41ee56b..4635d927f53 100644 --- a/components/spi_flash/include/spi_flash_chip_th.h +++ b/components/spi_flash/include/spi_flash_chip_th.h @@ -8,7 +8,7 @@ #include #include "esp_flash.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "sdkconfig.h" #ifdef CONFIG_SPI_FLASH_SUPPORT_TH_CHIP diff --git a/components/spi_flash/include/spi_flash_chip_winbond.h b/components/spi_flash/include/spi_flash_chip_winbond.h index b6b4287c196..787833b8312 100644 --- a/components/spi_flash/include/spi_flash_chip_winbond.h +++ b/components/spi_flash/include/spi_flash_chip_winbond.h @@ -8,7 +8,7 @@ #include #include "esp_flash.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "sdkconfig.h" /** diff --git a/components/spi_flash/spi_flash_blockdev.c b/components/spi_flash/spi_flash_blockdev.c index 9b9c5e0298f..01aeb180f7f 100644 --- a/components/spi_flash/spi_flash_blockdev.c +++ b/components/spi_flash/spi_flash_blockdev.c @@ -7,7 +7,7 @@ #include #include #include "esp_flash.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "esp_heap_caps.h" #include "esp_blockdev.h" diff --git a/components/spi_flash/spi_flash_chip_drivers.c b/components/spi_flash/spi_flash_chip_drivers.c index d866d72954d..c1cd7f68dfa 100644 --- a/components/spi_flash/spi_flash_chip_drivers.c +++ b/components/spi_flash/spi_flash_chip_drivers.c @@ -5,7 +5,7 @@ */ #include -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "spi_flash_chip_generic.h" #include "spi_flash_chip_issi.h" #include "spi_flash_chip_mxic.h" diff --git a/components/spi_flash/spi_flash_os_func_app.c b/components/spi_flash/spi_flash_os_func_app.c index 073b102df01..ae5d8e517c6 100644 --- a/components/spi_flash/spi_flash_os_func_app.c +++ b/components/spi_flash/spi_flash_os_func_app.c @@ -10,6 +10,7 @@ #include "esp_attr.h" #include "esp_private/system_internal.h" #include "esp_flash.h" +#include "esp_private/esp_flash_types.h" #include "esp_flash_partitions.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index 0ba7c006c5f..113ebd3928b 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -7,6 +7,7 @@ #include #include "sdkconfig.h" #include "esp_flash.h" +#include "esp_private/esp_flash_types.h" #include "esp_attr.h" #include "esp_rom_sys.h" #include "esp_cpu.h" diff --git a/components/spi_flash/test_apps/esp_flash_blockdev/main/test_spi_flash.c b/components/spi_flash/test_apps/esp_flash_blockdev/main/test_spi_flash.c index 3bb408426ff..d977d4d4e85 100644 --- a/components/spi_flash/test_apps/esp_flash_blockdev/main/test_spi_flash.c +++ b/components/spi_flash/test_apps/esp_flash_blockdev/main/test_spi_flash.c @@ -9,7 +9,7 @@ #include "esp_log.h" #include "unity.h" -#include "spi_flash_chip_driver.h" +#include "esp_flash_port/spi_flash_chip_driver.h" #include "test_flash_utils.h" TEST_CASE("spi_flash BDL test", "[esp_flash]") diff --git a/components/spi_flash/test_apps/esp_flash_freq_limit/CMakeLists.txt b/components/spi_flash/test_apps/esp_flash_freq_limit/CMakeLists.txt index b888fea1ba9..614e10ca1cd 100644 --- a/components/spi_flash/test_apps/esp_flash_freq_limit/CMakeLists.txt +++ b/components/spi_flash/test_apps/esp_flash_freq_limit/CMakeLists.txt @@ -1,8 +1,6 @@ # This is the project CMakeLists.txt file for the test subproject cmake_minimum_required(VERSION 3.22) -set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/test_apps/components") - # "Trim" the build. Include the minimal set of components, main, and anything it depends on. We also depend on # esptool_py as we set CONFIG_ESPTOOLPY_... options. set(COMPONENTS main esptool_py) diff --git a/components/spi_flash/test_apps/esp_flash_freq_limit/main/test_esp_flash_freq_limit.c b/components/spi_flash/test_apps/esp_flash_freq_limit/main/test_esp_flash_freq_limit.c index c76fa625082..82d84feb1ce 100644 --- a/components/spi_flash/test_apps/esp_flash_freq_limit/main/test_esp_flash_freq_limit.c +++ b/components/spi_flash/test_apps/esp_flash_freq_limit/main/test_esp_flash_freq_limit.c @@ -14,6 +14,7 @@ #include #include "unity.h" #include "esp_flash.h" +#include "esp_private/esp_flash_types.h" #include "soc/rtc.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 0d6101edfbd..a3a446256e8 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -490,7 +490,6 @@ components/soc/esp32s2/include/soc/fe_reg.h components/soc/esp32s2/include/soc/memprot_defs.h components/soc/esp32s2/include/soc/nrx_reg.h components/soc/esp32s2/include/soc/soc_ulp.h -components/spi_flash/include/spi_flash_chip_generic.h components/spi_flash/spi_flash_chip_boya.c components/spi_flash/spi_flash_chip_issi.c components/tcp_transport/include/esp_transport_ws.h diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index cb0ac51d4a5..7d94052d67c 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -33,7 +33,6 @@ components/spi_flash/include/spi_flash_chip_winbond.h components/spi_flash/include/spi_flash_chip_boya.h components/spi_flash/include/spi_flash_chip_th.h components/spi_flash/include/memspi_host_driver.h -components/spi_flash/include/spi_flash_chip_driver.h components/spi_flash/include/spi_flash_chip_generic.h