Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-09-22 13:01:16 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'fix/fix_rgb_frame_buffer_alignment_v5.4' into 'release/v5.4'

Browse Source 
fix(gdma): fix buffer alignment when psram ecc enabled (v5.4)

See merge request espressif/esp-idf!49999
This commit is contained in:
morris
2026-08-14 14:27:10 +08:00
parent 35e52aec51 b28e9a3277
commit 708c7d28ce
1 changed files with 12 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
components/esp_hw_support/dma/gdma.c
View File

@@ -370,15 +370,19 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
// There's auto alignment for AHB GDMA version 1, so we don't need to do anything here
// While, for AHB GDMA version 2 and AXI GDMA, we need to ensure the alignment by software
#if (SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH) && SOC_AHB_GDMA_VERSION != 1
// if MSPI encryption is enabled, and DMA wants to read/write external memory
if (efuse_hal_flash_encryption_enabled() && config->access_ext_mem) {
uint32_t enc_mem_alignment = GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT;
// when DMA access the encrypted external memory, extra alignment is needed for external memory
ext_mem_alignment = MAX(ext_mem_alignment, enc_mem_alignment);
if (max_data_burst_size < enc_mem_alignment) {
ESP_LOGW(TAG, "GDMA channel access encrypted external memory, adjust burst size to %"PRIu32, enc_mem_alignment);
bool ext_mem_needs_mspi_alignment = efuse_hal_flash_encryption_enabled();
#if CONFIG_SPIRAM_ECC_ENABLE
ext_mem_needs_mspi_alignment = true;
#endif
// When MSPI encryption or PSRAM ECC address conversion is enabled, DMA accesses to
// external memory need to follow the MSPI encryption alignment restriction.
if (ext_mem_needs_mspi_alignment && config->access_ext_mem) {
uint32_t mspi_mem_alignment = GDMA_LL_ACCESS_ENCRYPTION_MEM_ALIGNMENT;
ext_mem_alignment = MAX(ext_mem_alignment, mspi_mem_alignment);
if (max_data_burst_size < mspi_mem_alignment) {
ESP_LOGW(TAG, "GDMA channel access encrypted/ECC external memory, adjust burst size to %"PRIu32, mspi_mem_alignment);
en_data_burst = true;
max_data_burst_size = enc_mem_alignment;
max_data_burst_size = mspi_mem_alignment;
}
}
#endif // SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH