Merge branch 'stub_bins_for_more_targets_v6.1' into 'release/v6.1'

Increase OCD stub memory reservation from 8K to 12K and extend this feature to more targets (v6.1) See merge request espressif/esp-idf!51534
2026-09-22 13:01:16 +03:00 · 2026-09-04 15:55:25 +08:00
parent eb0faad47b ae0c69d9d8
commit 6d6facef39
21 changed files with 75 additions and 12 deletions
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@@ -406,18 +406,25 @@ menu "ESP System Settings"
            which does some useful debugging stuff, e.g. GCOV data dump.

    config ESP_DEBUG_INCLUDE_OCD_STUB_BINS
-        bool "Preload OpenOCD stub binaries to speed up debugging. 8K memory will be reserved"
+        bool "Preload OpenOCD stub binaries to speed up debugging. 12K memory will be reserved"
        default n
        depends on SOC_DEBUG_HAVE_OCD_STUB_BINS
+        depends on !IDF_TARGET_ESP32P4 || ESP32P4_SELECTS_REV_LESS_V3 || CACHE_L2_CACHE_512KB
        help
            OpenOCD uses stub code to access flash during programming or when inserting and removing
            SW flash breakpoints.
            To execute stub code, OpenOCD allocates memory on the target device, backs up the existing memory,
            loads the stub binary, runs the binary, and then restores the original memory.
            This process can be time-consuming, especially when using USB serial JTAG.
-            By enabling this option, 8K of memory in RAM will be preallocated with the stub code,
+            By enabling this option, 12K of memory in RAM will be preallocated with the stub code,
            eliminating the need to back up and restore the memory region.

+            The stub binaries are prebuilt and linked to run at the start of IRAM (_iram_start).
+            On ESP32-P4 rev >= v3, _iram_start is 0x4FF00000 + L2 cache size, so it only matches the
+            stub's link address (0x4FF80000) when the L2 cache is 512KB. This option is therefore
+            only available on ESP32-P4 rev >= v3 when CACHE_L2_CACHE_512KB is selected. Earlier P4
+            revisions and other targets place _iram_start at a fixed address and are not affected.
+
    config ESP_DEBUG_OCDAWARE
        bool "Make exception and panic handlers JTAG/OCD aware"
        default y
--- a/components/esp_system/ld/ld.iram.sections
+++ b/components/esp_system/ld/ld.iram.sections
@@ -9,14 +9,14 @@
    /* Do not move this block! OpenOCD expects this to be at the beginning of IRAM. */
    KEEP(*(.ocd_stub.code));
    KEEP(*(.ocd_stub.tramp));
-    . = ALIGN(0x800);
+    . = ALIGN(0x1000);
    KEEP(*(.ocd_stub.data));
    KEEP(*(.ocd_stub.bss));
    KEEP(*(.ocd_stub.stack));
    KEEP(*(.ocd_stub.params));
    . = ALIGN(0x1000);
    KEEP(*(.ocd_stub.scratchmem));
-    ASSERT(ABSOLUTE(.) == _iram_start + 0x2000, "openocd stub memory must be ended at _iram_start + 0x2000");
+    ASSERT(ABSOLUTE(.) == _iram_start + 0x3000, "openocd stub memory must be ended at _iram_start + 0x3000");
 #endif

    /* Vectors go to start of IRAM */
--- a/components/esp_system/openocd_stub_bins/CMakeLists.txt
+++ b/components/esp_system/openocd_stub_bins/CMakeLists.txt
@@ -15,10 +15,14 @@ set(openocd_path $ENV{OPENOCD_SCRIPTS})

 if(openocd_path)
    set(stub_bin_path ${openocd_path}/../espressif/stub_bins)
-    if(IS_DIRECTORY ${stub_bin_path} AND IS_DIRECTORY ${stub_bin_path}/${target})
-        set(code_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_code.inc")
-        set(data_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_data.inc")
-        set(img_header "${stub_bin_path}/${target}/stub_flash_idf_image.h")
+    set(stub_target_dir ${target})
+    if(target STREQUAL "esp32p4" AND CONFIG_ESP32P4_REV_MIN_FULL LESS 300)
+        set(stub_target_dir "esp32p4-rev1")
+    endif()
+    if(IS_DIRECTORY ${stub_bin_path} AND IS_DIRECTORY ${stub_bin_path}/${stub_target_dir})
+        set(code_bin "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_binary_code.inc")
+        set(data_bin "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_binary_data.inc")
+        set(img_header "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_image.h")
        if(EXISTS ${code_bin} AND EXISTS ${data_bin} AND EXISTS ${img_header})
            set(dest_dir "${CMAKE_BINARY_DIR}/openocd_stub_bins")
            set(output_code_bin "${dest_dir}/stub_flash_idf_binary_code.inc")
--- a/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in
+++ b/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in
@@ -32,7 +32,12 @@
 * should be stored via esp_app_tee_config structure
 */

+#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x32b0 );
+#else
 PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2b0 );
+#endif
+
 PROVIDE ( GDMA                      = 0x60080000 );

 /* SPI Flash functions required from the ROM (refer esp32c5.rom.spiflash.ld) */
--- a/components/esp_tee/subproject/main/ld/esp32c6/esp_tee.ld.in
+++ b/components/esp_tee/subproject/main/ld/esp32c6/esp_tee.ld.in
@@ -33,7 +33,7 @@
 */

 #if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
-PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x22e0 );
+PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x32e0 );
 #else
 PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2e0 );
 #endif
--- a/components/esp_tee/subproject/main/ld/esp32c61/esp_tee.ld.in
+++ b/components/esp_tee/subproject/main/ld/esp32c61/esp_tee.ld.in
@@ -32,7 +32,12 @@
 * should be stored via esp_app_tee_config structure
 */

+#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x32b0 );
+#else
 PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2b0 );
+#endif
+
 PROVIDE ( GDMA                      = 0x60080000 );

 /* SPI Flash functions required from the ROM (refer esp32c61.rom.spiflash.ld) */
--- a/components/esp_tee/subproject/main/ld/esp32h2/esp_tee.ld.in
+++ b/components/esp_tee/subproject/main/ld/esp32h2/esp_tee.ld.in
@@ -33,7 +33,7 @@
 */

 #if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
-PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x22e0 );
+PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x32e0 );
 #else
 PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2e0 );
 #endif
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -1623,6 +1623,10 @@ config SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
    bool
    default y

+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
+
 config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR
    bool
    default y
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -650,6 +650,9 @@
 // #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
 #define SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT (1)

+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*------------------------------------- ULP CAPS -------------------------------------*/
 #define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR         (1) /*!< LP Core interrupts all map to a single entry in vector table */
 #define SOC_LP_CORE_SUPPORT_ETM                     (1) /*!< LP Core supports ETM */
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -1254,3 +1254,7 @@ config SOC_PHY_COMBO_MODULE
 config SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
    bool
    default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -507,5 +507,8 @@
 #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
 #define SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT (1)

+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*------------------------------------- No Reset CAPS -------------------------------------*/
 //  \#define SOC_CAPS_NO_RESET_BY_ANA_BOD           (1)   //TODO: [ESP32C61] IDF-9254
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -1094,3 +1094,7 @@ config SOC_BLE_SUBRATE_SUPPORTED
 config SOC_BLE_PERIODIC_ADV_WITH_RESPONSE
    bool
    default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -503,3 +503,6 @@
 #define SOC_BLE_CTE_SUPPORTED           (1)    /*!< Support Bluetooth LE Constant Tone Extension (CTE) */
 #define SOC_BLE_SUBRATE_SUPPORTED       (1)    /*!< Support Bluetooth LE Connection Subrating */
 #define SOC_BLE_PERIODIC_ADV_WITH_RESPONSE  (1)    /*!< Support Bluetooth LE Periodic Advertising with Response (PAwR) */
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -1383,6 +1383,10 @@ config SOC_USB_FSLS_PHY_NUM
    int
    default 1

+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
+
 config SOC_ASRC_SUPPORTED
    bool
    default y
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -573,5 +573,8 @@
 #define SOC_USB_OTG_PERIPH_NUM          (1U)
 #define SOC_USB_FSLS_PHY_NUM            (1U)

+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*---------------------------------- ASRC CAPS ----------------------------------*/
 #define SOC_ASRC_SUPPORTED (1)
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1958,3 +1958,7 @@ config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
 config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
    bool
    default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -749,3 +749,6 @@
 #define SOC_LP_CORE_SUPPORT_I2C                     (1) /*!< LP Core supports I2C */
 #define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
 #define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED   (1) /*!< LP UART wakeup source is kept triggered */
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
--- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
@@ -1866,3 +1866,7 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM
 config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
    bool
    default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
--- a/components/soc/esp32s31/include/soc/soc_caps.h
+++ b/components/soc/esp32s31/include/soc/soc_caps.h
@@ -693,3 +693,6 @@
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM                   (1)
 // temperature sensor on esp32s31 in under low power domain.
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION       (1)
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
--- a/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst
+++ b/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst
@@ -115,7 +115,7 @@ In order to achieve higher data rates and minimize number of dropped packets it
    Improve Debugging Speed
    ^^^^^^^^^^^^^^^^^^^^^^^

-    Enabling :ref:`CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS` allocates 8 KB of RAM and embeds pre-built stub binaries into RAM. This improves the overall debugging speed by eliminating the need to load the stub binaries at runtime. It is particularly beneficial when using flash breakpoints, as it reduces the latency of add/remove breakpoints. However, keep in mind that the increased RAM usage may reduce memory availability for other tasks.
+    Enabling :ref:`CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS` allocates 12 KB of RAM and embeds pre-built stub binaries into RAM. This improves the overall debugging speed by eliminating the need to load the stub binaries at runtime. It is particularly beneficial when using flash breakpoints, as it reduces the latency of add/remove breakpoints. However, keep in mind that the increased RAM usage may reduce memory availability for other tasks.

    .. _jtag-debugging-tip-debugger-startup-commands:

--- a/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst
+++ b/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst
@@ -115,7 +115,7 @@ GDB 具有 FreeRTOS 支持的 Python 扩展模块。在系统要求满足的情
    提高调试速度
    ^^^^^^^^^^^^^^^^^^^^^^^

-    启用 :ref:`CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS` 将预先分配 8 KB 的 RAM, 且预编译的存根二进制文件将嵌入到 RAM 中，因此运行时将无需加载存根二进制文件，从而提高整体调试速度。在使用 flash 断点时，上述优化可以有效降低添加和删除断点的延迟。但要注意，RAM 使用量的增加可能会占用其他任务所需的内存。
+    启用 :ref:`CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS` 将预先分配 12 KB 的 RAM, 且预编译的存根二进制文件将嵌入到 RAM 中，因此运行时将无需加载存根二进制文件，从而提高整体调试速度。在使用 flash 断点时，上述优化可以有效降低添加和删除断点的延迟。但要注意，RAM 使用量的增加可能会占用其他任务所需的内存。

    .. _jtag-debugging-tip-debugger-startup-commands: