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fix(hal): Fix MMU PSRAM anti-fi MMU target check

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In case of ESP32-C5 and ESP32-C61, mmu_ids for PSRAM and Flash
MMU are the same due to their shared memory space. Thus, instead of
mmu_id we should use mmu_target_t.
This commit is contained in:
harshal.patil
2026-08-03 14:29:42 +05:30
committed by Mahavir Jain
parent 27362ab26b
commit 67affdd43b
3 changed files with 10 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/hal/esp32c5/include/hal/mmu_ll.h
+3 -1
View File
@@ -227,14 +227,16 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
#if !BOOTLOADER_BUILD
// Anti-FI check to confirm the encryption status for PSRAM entry.
// This avoids a potential FI attacks to keep PSRAM unencrypted and
// hence read out plaintext in execute from PSRAM model.
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID && efuse_hal_chip_revision() > 100));
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100));
}
#endif // !BOOTLOADER_BUILD
}
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE
components/hal/esp32c61/include/hal/mmu_ll.h
+3 -1
View File
@@ -230,14 +230,16 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
#if !BOOTLOADER_BUILD
// Anti-FI check to confirm the encryption status for PSRAM entry.
// This avoids a potential FI attacks to keep PSRAM unencrypted and
// hence read out plaintext in execute from PSRAM model.
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID && efuse_hal_chip_revision() > 100));
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100));
}
#endif // !BOOTLOADER_BUILD
}
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE
components/hal/esp32p4/include/hal/mmu_ll.h
+4 -2
View File
@@ -292,14 +292,16 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
REG_WRITE(index_reg, entry_id);
REG_WRITE(content_reg, mmu_val);
#if !BOOTLOADER_BUILD
// Anti-FI check to confirm the encryption status for PSRAM entry.
// This avoids a potential FI attacks to keep PSRAM unencrypted and
// hence read out plaintext in execute from PSRAM model.
if (mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID) {
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0) {
ESP_FAULT_ASSERT(REG_READ(content_reg) & SOC_MMU_PSRAM_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID));
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0));
}
#endif // !BOOTLOADER_BUILD
}
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE