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fix(security): add anti-FI checks while setting up PSRAM encryption

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This commit is contained in:
Mahavir Jain
2025-09-04 18:01:16 +05:30
parent d276041d1c
commit 27362ab26b
3 changed files with 30 additions and 0 deletions
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10
components/hal/esp32c5/include/hal/mmu_ll.h
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@@ -15,6 +15,7 @@
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#include "esp_fault_internal.h"
#if SOC_EFUSE_SUPPORTED
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
@@ -225,6 +226,15 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
mmu_raw_value = mmu_val | SOC_MMU_VALID;
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
// Anti-FI check to confirm the encryption status for PSRAM entry.
// This avoids a potential FI attacks to keep PSRAM unencrypted and
// hence read out plaintext in execute from PSRAM model.
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID && efuse_hal_chip_revision() > 100));
}
}
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE

10
components/hal/esp32c61/include/hal/mmu_ll.h
View File

@@ -15,6 +15,7 @@
#include "hal/mmu_types.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
#include "esp_fault_internal.h"
// TODO: [ESP32C61] IDF-9265, inherit from c6
@@ -228,6 +229,15 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
mmu_raw_value = mmu_val | SOC_MMU_VALID;
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
// Anti-FI check to confirm the encryption status for PSRAM entry.
// This avoids a potential FI attacks to keep PSRAM unencrypted and
// hence read out plaintext in execute from PSRAM model.
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID && efuse_hal_chip_revision() > 100));
}
}
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE

10
components/hal/esp32p4/include/hal/mmu_ll.h
View File

@@ -15,6 +15,7 @@
#include "hal/assert.h"
#include "hal/mmu_types.h"
#include "hal/efuse_ll.h"
#include "esp_fault_internal.h"
#ifdef __cplusplus
@@ -290,6 +291,15 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
REG_WRITE(index_reg, entry_id);
REG_WRITE(content_reg, mmu_val);
// Anti-FI check to confirm the encryption status for PSRAM entry.
// This avoids a potential FI attacks to keep PSRAM unencrypted and
// hence read out plaintext in execute from PSRAM model.
if (mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID) {
ESP_FAULT_ASSERT(REG_READ(content_reg) & SOC_MMU_PSRAM_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID));
}
}
#if SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE