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refactor(driver_spi): remove some SPI_LL_xxx SOC_xxx macros
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@@ -123,7 +123,7 @@ typedef struct {
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int iocfg[9]; ///< GPIO config in array format follow the above order.
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};
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bool data_io_default_level; ///< Output data IO default level when no transaction.
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int max_transfer_sz; ///< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to `SOC_SPI_MAXIMUM_BUFFER_SIZE` if DMA is disabled.
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int max_transfer_sz; ///< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to hardware fifo length (usually 64 bytes) if DMA is disabled.
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uint32_t dma_burst_size; ///< DMA data burst size in bytes. Only used when DMA is enabled. Set to 0 to use driver default. When non-zero, must be one of the chip-supported values (see GDMA driver or chip TRM). Ignored on chips that do not support configurable burst size.
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uint32_t flags; ///< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags.
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esp_intr_cpu_affinity_t isr_cpu_id; ///< Select cpu core to register SPI ISR.
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@@ -20,7 +20,6 @@
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extern "C" {
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#endif
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#ifdef SOC_SPI_SCT_SUPPORTED
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/**
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* @Backgrounds: `SCT Mode`
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* Segmented-Configure-Transfer Mode
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@@ -115,7 +114,6 @@ esp_err_t spi_device_queue_multi_trans(spi_device_handle_t handle, spi_multi_tra
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* - ESP_ERR_TIMEOUT: Timeout, didn't get a completed SCT transaction
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*/
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esp_err_t spi_device_get_multi_trans_result(spi_device_handle_t handle, spi_multi_transaction_t **seg_trans_desc, uint32_t ticks_to_wait);
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#endif //#ifdef SOC_SPI_SCT_SUPPORTED
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#ifdef __cplusplus
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}
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