diff --git a/components/esp_driver_spi/include/driver/spi_common.h b/components/esp_driver_spi/include/driver/spi_common.h
index 424b9b79f2f..87e8abc6ff4 100644
--- a/components/esp_driver_spi/include/driver/spi_common.h
+++ b/components/esp_driver_spi/include/driver/spi_common.h
@@ -123,7 +123,7 @@ typedef struct {
         int iocfg[9];               ///< GPIO config in array format follow the above order.
     };
     bool data_io_default_level; ///< Output data IO default level when no transaction.
-    int max_transfer_sz;  ///< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to `SOC_SPI_MAXIMUM_BUFFER_SIZE` if DMA is disabled.
+    int max_transfer_sz;  ///< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to hardware fifo length (usually 64 bytes) if DMA is disabled.
     uint32_t dma_burst_size; ///< DMA data burst size in bytes. Only used when DMA is enabled. Set to 0 to use driver default. When non-zero, must be one of the chip-supported values (see GDMA driver or chip TRM). Ignored on chips that do not support configurable burst size.
     uint32_t flags;       ///< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags.
     esp_intr_cpu_affinity_t  isr_cpu_id;    ///< Select cpu core to register SPI ISR.
diff --git a/components/esp_driver_spi/include/esp_private/spi_master_internal.h b/components/esp_driver_spi/include/esp_private/spi_master_internal.h
index cdd85114ec1..8d2f9e07e4e 100644
--- a/components/esp_driver_spi/include/esp_private/spi_master_internal.h
+++ b/components/esp_driver_spi/include/esp_private/spi_master_internal.h
@@ -20,7 +20,6 @@
 extern "C" {
 #endif
 
-#ifdef SOC_SPI_SCT_SUPPORTED
 /**
  * @Backgrounds: `SCT Mode`
  * Segmented-Configure-Transfer Mode
@@ -115,7 +114,6 @@ esp_err_t spi_device_queue_multi_trans(spi_device_handle_t handle, spi_multi_tra
  *        - ESP_ERR_TIMEOUT:       Timeout, didn't get a completed SCT transaction
  */
 esp_err_t spi_device_get_multi_trans_result(spi_device_handle_t handle, spi_multi_transaction_t **seg_trans_desc, uint32_t ticks_to_wait);
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c
index e313bfa4a20..de5ec5d3094 100644
--- a/components/esp_driver_spi/src/gpspi/spi_common.c
+++ b/components/esp_driver_spi/src/gpspi/spi_common.c
@@ -949,7 +949,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *
 
     spi_bus_lock_config_t lock_config = {
         .host_id = host_id,
-        .cs_num = SOC_SPI_PERIPH_CS_NUM(host_id),
+        .cs_num = SPI_LL_PERIPH_CS_NUM(host_id),
     };
     err = spi_bus_init_lock(&bus_attr->lock, &lock_config);
     if (err != ESP_OK) {
diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c
index e7f8ec197f1..bdcb863dc15 100644
--- a/components/esp_driver_spi/src/gpspi/spi_master.c
+++ b/components/esp_driver_spi/src/gpspi/spi_master.c
@@ -182,12 +182,12 @@ typedef struct {
     const uint32_t *buffer_to_send;    //equals to tx_data, if SPI_TRANS_USE_RXDATA is applied; otherwise if original buffer wasn't in DMA-capable memory, this gets the address of a temporary buffer that is;
     //otherwise sets to the original buffer or NULL if no buffer is assigned.
     uint32_t *buffer_to_rcv;           //similar to buffer_to_send
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
     uint32_t reserved[2];              //As we create the queue when in init, to use sct mode private descriptor as a queue item (when in sct mode), we need to add a dummy member here to keep the same size with `spi_sct_trans_priv_t`.
 #endif
 } spi_trans_priv_t;
 
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
 //Type of dma descriptors that used under SPI SCT mode
 typedef struct {
     spi_dma_desc_t          *tx_seg_head;
@@ -219,7 +219,7 @@ typedef struct {
     intr_handle_t intr;
     spi_hal_context_t hal;
     spi_trans_priv_t cur_trans_buf;
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
     spi_sct_desc_ctx_t sct_desc_pool;
     spi_sct_trans_priv_t cur_sct_trans;
 #endif
@@ -406,7 +406,7 @@ int spi_get_freq_limit(bool gpio_is_used, int input_delay_ns)
 #endif
 }
 
-#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
+#if SPI_LL_SRC_PRE_DIV_MAX
 static uint32_t s_spi_find_clock_src_pre_div(uint32_t src_freq, uint32_t target_freq)
 {
     // pre division must be even and at least 2
@@ -423,7 +423,7 @@ static uint32_t s_spi_find_clock_src_pre_div(uint32_t src_freq, uint32_t target_
     }
     return min_div;
 }
-#endif //SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
+#endif //SPI_LL_SRC_PRE_DIV_MAX
 
 /*
  Add a device. This allocates a CS line for the device, allocates memory for the device structure and hooks
@@ -455,7 +455,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
     }
     SPI_CHECK(esp_clk_tree_enable_src(clk_src, true) == ESP_OK, "clock source enable failed", ESP_ERR_INVALID_STATE);
     esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz);
-#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
+#if SPI_LL_SRC_PRE_DIV_MAX
     clock_source_div = s_spi_find_clock_src_pre_div(clock_source_hz, dev_config->clock_speed_hz);
     clock_source_hz /= clock_source_div; //actual freq enter to SPI peripheral
 #endif
@@ -684,7 +684,7 @@ static SPI_MASTER_ISR_ATTR void spi_setup_device(spi_device_t *dev, spi_trans_pr
         /* Configuration has not been applied yet. */
         spi_hal_setup_device(hal, hal_dev);
         PERIPH_RCC_ATOMIC() {
-#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
+#if SPI_LL_SRC_PRE_DIV_MAX
             //we set mst_div as const 2, then (hs_clk = 2*mst_clk) to ensure timing turning work as past
             //and sure (hs_div * mst_div = source_pre_div)
             spi_ll_clk_source_pre_div(hal->hw, hal_dev->timing_conf.source_pre_div / 2, 2);
@@ -861,7 +861,7 @@ static void SPI_MASTER_ISR_ATTR spi_post_trans(spi_host_t *host)
     host->cur_cs = DEV_NUM_MAX;
 }
 
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
 static void SPI_MASTER_ISR_ATTR spi_sct_set_hal_trans_config(spi_multi_transaction_t *trans_header, spi_hal_trans_config_t *hal_trans)
 {
     spi_transaction_t *trans = &trans_header->base;
@@ -935,7 +935,7 @@ static void SPI_MASTER_ISR_ATTR spi_post_sct_trans(spi_host_t *host)
 
     host->cur_cs = DEV_NUM_MAX;
 }
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
+#endif  //#ifdef SPI_LL_PERIPH_HAS_SCT
 
 static void SPI_MASTER_ISR_ATTR spi_trans_dma_error_check(spi_host_t *host)
 {
@@ -968,7 +968,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
     const spi_dma_ctx_t *dma_ctx = host->dma_ctx;
 #endif
 
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
     assert(spi_hal_usr_is_done(&host->hal) || spi_hal_get_intr_mask(&host->hal, SPI_LL_INTR_SEG_DONE));
 #else
     assert(spi_hal_usr_is_done(&host->hal));
@@ -998,7 +998,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
             spi_trans_dma_error_check(host);
         }
 
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
         if (host->sct_mode_enabled) {
             //cur_cs is changed to DEV_NUM_MAX here
             spi_post_sct_trans(host);
@@ -1006,7 +1006,7 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
                 xQueueSendFromISR(host->device[cs]->ret_queue, &host->cur_sct_trans, &do_yield);
             }
         } else
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
+#endif  //#ifdef SPI_LL_PERIPH_HAS_SCT
         {
             //cur_cs is changed to DEV_NUM_MAX here
             spi_post_trans(host);
@@ -1051,11 +1051,11 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
             bool dev_has_req = spi_bus_lock_bg_check_dev_req(desired_dev);
             if (dev_has_req) {
                 device_to_send = host->device[spi_bus_lock_get_dev_id(desired_dev)];
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
                 if (host->sct_mode_enabled) {
                     trans_found = xQueueReceiveFromISR(device_to_send->trans_queue, &host->cur_sct_trans, &do_yield);
                 } else
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
+#endif  //#ifdef SPI_LL_PERIPH_HAS_SCT
                 {
                     trans_found = xQueueReceiveFromISR(device_to_send->trans_queue, &host->cur_trans_buf, &do_yield);
                 }
@@ -1066,11 +1066,11 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
         }
 
         if (trans_found) {
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
             if (host->sct_mode_enabled) {
                 spi_new_sct_trans(device_to_send, &host->cur_sct_trans);
             } else
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
+#endif  //#ifdef SPI_LL_PERIPH_HAS_SCT
             {
                 spi_trans_priv_t *const cur_trans_buf = &host->cur_trans_buf;
 #if CONFIG_IDF_TARGET_ESP32
@@ -1477,7 +1477,7 @@ esp_err_t spi_bus_get_max_transaction_len(spi_host_device_t host_id, size_t *max
     return ESP_OK;
 }
 
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
 
 /*-----------------------------------------------------------
  * Below functions should be in the same spinlock
@@ -1659,7 +1659,7 @@ static void s_spi_sct_reset_dma_pool(const spi_dma_ctx_t *dma_ctx, spi_sct_desc_
 esp_err_t spi_bus_multi_trans_mode_enable(spi_device_handle_t handle, bool enable)
 {
     SPI_CHECK(handle, "Invalid arguments.", ESP_ERR_INVALID_ARG);
-    SPI_CHECK(SOC_SPI_SCT_SUPPORTED(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG);
+    SPI_CHECK(SPI_LL_PERIPH_HAS_SCT(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG);
     SPI_CHECK(handle->cfg.flags & SPI_DEVICE_HALFDUPLEX, "SCT mode only available under Half Duplex mode", ESP_ERR_INVALID_STATE);
     SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot queue new transaction while previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE);
     SPI_CHECK(uxQueueMessagesWaiting(handle->trans_queue) == 0, "Cannot enable SCT mode when internal Queue still has items", ESP_ERR_INVALID_STATE);
@@ -1783,7 +1783,7 @@ static void SPI_MASTER_ATTR s_sct_format_conf_buffer(spi_device_handle_t handle,
 esp_err_t SPI_MASTER_ATTR spi_device_queue_multi_trans(spi_device_handle_t handle, spi_multi_transaction_t *seg_trans_desc, uint32_t trans_num, uint32_t ticks_to_wait)
 {
     SPI_CHECK(handle, "Invalid arguments.", ESP_ERR_INVALID_ARG);
-    SPI_CHECK(SOC_SPI_SCT_SUPPORTED(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG);
+    SPI_CHECK(SPI_LL_PERIPH_HAS_SCT(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG);
     SPI_CHECK(handle->host->sct_mode_enabled == 1, "SCT mode isn't enabled", ESP_ERR_INVALID_STATE);
 
     esp_err_t ret = ESP_OK;
@@ -1881,7 +1881,7 @@ esp_err_t SPI_MASTER_ATTR spi_device_queue_multi_trans(spi_device_handle_t handl
 esp_err_t SPI_MASTER_ATTR spi_device_get_multi_trans_result(spi_device_handle_t handle, spi_multi_transaction_t **seg_trans_desc, uint32_t ticks_to_wait)
 {
     SPI_CHECK(handle, "Invalid arguments.", ESP_ERR_INVALID_ARG);
-    SPI_CHECK(SOC_SPI_SCT_SUPPORTED(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG);
+    SPI_CHECK(SPI_LL_PERIPH_HAS_SCT(handle->host->id), "Invalid arguments", ESP_ERR_INVALID_ARG);
     SPI_CHECK(handle->host->sct_mode_enabled == 1, "SCT mode isn't enabled", ESP_ERR_INVALID_STATE);
     spi_sct_trans_priv_t sct_desc = {};
 
@@ -1894,4 +1894,4 @@ esp_err_t SPI_MASTER_ATTR spi_device_get_multi_trans_result(spi_device_handle_t
 
     return ESP_OK;
 }
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
+#endif  //#ifdef SPI_LL_PERIPH_HAS_SCT
diff --git a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c
index b805ee1576f..8eb484ef579 100644
--- a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c
+++ b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c
@@ -139,8 +139,8 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
     };
     gdma_apply_strategy(host->dma_ctx->tx_dma_chan, &dma_strategy);
 #else
-    spi_dma_ll_enable_out_auto_wrback(SPI_LL_GET_HW(host->dma_ctx->tx_dma_chan.host_id), host->dma_ctx->tx_dma_chan.chan_id, 1);
-    spi_dma_ll_set_out_eof_generation(SPI_LL_GET_HW(host->dma_ctx->tx_dma_chan.host_id), host->dma_ctx->tx_dma_chan.chan_id, 1);
+    spi_dma_ll_enable_out_auto_wrback(spi_periph_signal[host->dma_ctx->tx_dma_chan.host_id].hw, host->dma_ctx->tx_dma_chan.chan_id, 1);
+    spi_dma_ll_set_out_eof_generation(spi_periph_signal[host->dma_ctx->tx_dma_chan.host_id].hw, host->dma_ctx->tx_dma_chan.chan_id, 1);
 #endif
     ret = spicommon_dma_desc_alloc(host_id, bus_config->max_transfer_sz, &host->bus_attr->max_transfer_sz);
     if (ret != ESP_OK) {
diff --git a/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt
index 91e5f4d0fc4..2d7f098c3c8 100644
--- a/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt
+++ b/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt
@@ -1,3 +1,4 @@
+idf_build_get_property(target IDF_TARGET)
 
 set(srcs
     "test_app_main.c"
@@ -6,10 +7,14 @@ set(srcs
     "test_spi_bus_lock.c"
 )
 
-# sct test using slave hd APIs, need slave hd support
-# tmp skip sct test under iram_safe, both sct and slave hd are not cleaned
-if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 AND CONFIG_SOC_SPI_SCT_SUPPORTED AND NOT CONFIG_COMPILER_DUMP_RTL_FILES)
-    list(APPEND srcs "test_spi_master_sct.c")
+# TODO: IDF-10593 ～ IDF-10585: SCT is temporarily supported on follow chips
+set(sct_targets esp32s2 esp32s3 esp32c2 esp32c3 esp32c6 esp32h2 esp32h21)
+if("${target}" IN_LIST sct_targets)
+    # sct test using slave hd APIs, need slave hd support
+    # tmp skip sct test under iram_safe, both sct and slave hd are not cleaned
+    if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 AND NOT CONFIG_COMPILER_DUMP_RTL_FILES)
+        list(APPEND srcs "test_spi_master_sct.c")
+    endif()
 endif()
 
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
index 954ce0ffd70..acaac7cc13f 100644
--- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
+++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
@@ -12,7 +12,7 @@
 #include "driver/spi_slave.h"
 #include "sys/param.h"
 #include "driver/gpio.h"
-#include "hal/spi_ll.h"     // for SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
+#include "hal/spi_ll.h"     // for SPI_LL_SRC_PRE_DIV_MAX
 #include "soc/spi_periph.h"
 #include "soc/soc_memory_layout.h"
 #include "esp_private/cache_utils.h"
@@ -97,7 +97,7 @@ static void check_spi_pre_n_for(int clk, int pre, int n)
 #define TEST_CLK_TIMES     8
 uint32_t clk_param_80m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} };
 uint32_t clk_param_160m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} };
-#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
+#if SPI_LL_SRC_PRE_DIV_MAX
 uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 4, 50}, {333333, 1, 60}, {800000, 1, 25}, {2000000, 1, 10}, {5000000, 1,  4}, {12000000, 1, 2}, {18000000, 1, 1} };
 uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SPI_LL_MAX_PRE_DIV_NUM, 64}, {100000, 4, 60}, {333333, 2, 36}, {800000, 1, 30}, {5000000, 1, 5}, {12000000, 1, 2}, {18000000, 1, 2}, {24000000, 1, 1} };
 #else
@@ -157,7 +157,7 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
     for (uint8_t sour_idx = 0; sour_idx < sizeof(spi_clk_sour); sour_idx++) {
         esp_clk_tree_src_get_freq_hz(spi_clk_sour[sour_idx], ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz);
         printf("\nTesting unknown clock source @%ld Hz\n", clock_source_hz);
-#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
+#if SPI_LL_SRC_PRE_DIV_MAX
         clock_source_hz /= 2;  //targets support pre-div will divide clock by 2 before SPI peripheral
 #endif
         for (uint8_t test_time = 0; test_time < 8; test_time ++) {
@@ -1573,7 +1573,7 @@ TEST_CASE("spi_speed", "[spi]")
 #endif // !(CONFIG_SPIRAM) || (CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL >= 16384)
 
 //****************************************spi master add device test************************************//
-#define SPI_MAX_DEVICE_NUM  SOC_SPI_PERIPH_CS_NUM(TEST_SPI_HOST)
+#define SPI_MAX_DEVICE_NUM  SPI_LL_PERIPH_CS_NUM(TEST_SPI_HOST)
 //add dummy devices first
 #if CONFIG_IDF_TARGET_ESP32
 #define DUMMY_CS_PINS() {25, 26, 27}
diff --git a/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h
index 54fea8f0a1b..a0fdcfbc6c7 100644
--- a/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) ((ID)==SPI1_HOST ? &SPI1:((ID)==SPI2_HOST ? &SPI2 : &SPI3))
 /// Registers to reset during initialization. Don't use in app.
 #define SPI_LL_DMA_FIFO_RST_MASK (SPI_AHBM_RST | SPI_AHBM_FIFO_RST)
 /// Interrupt not used. Don't use in app.
@@ -36,14 +37,15 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_DUAL | SPI_FWRITE_QUAD | SPI_FWRITE_DIO | SPI_FWRITE_QIO)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) ((ID)==0? &SPI1:((ID)==1? &SPI2 : &SPI3))
 
+#define SPI_LL_PERIPH_CS_NUM(i)  3
 #define SPI_LL_DMA_CHANNEL_NUM    (2)
 #define SPI_LL_DMA_MAX_BIT_LEN    (1 << 24)    //reg len: 24 bits
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 1            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (8192)
+#define SPI_LL_PERIPH_BITWIDTH(host) (4)       //Supported line mode: DIO, DOUT, QIO, or QOUT
 #define SPI_LL_SUPPORT_CLK_AS_CS  1            //Output clock on CS line if CS is active
 #define SPI_LL_MOSI_FREE_LEVEL    0            //Default level after bus initialized
 
diff --git a/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h
index 6311945610e..e90d2d88bb6 100644
--- a/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) (((ID)==SPI2_HOST) ? &GPSPI2 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -34,14 +35,16 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : NULL)
 
+#define SPI_LL_PERIPH_CS_NUM(i)   6            //c2 only support gpspi2
 #define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 2            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
+#define SPI_LL_PERIPH_BITWIDTH(host) (4)       //Supported line mode: DIO, DOUT, QIO, or QOUT
+#define SPI_LL_PERIPH_HAS_SCT(host)  ((host) == SPI2_HOST)  //If peripheral support SCT (DMA Segmented Configured Transaction) mode
 #define SPI_LL_MAX_SCT_CONF_LEN   (0x3FFFA)    //18 bits wide reg
 #define SPI_LL_SCT_CONF_BUF_NUM   (1 + 14)     //1-word-bitmap + 14-word-regs according to TRM
 
diff --git a/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h
index f6958ac1833..223c297aafa 100644
--- a/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) (((ID)==SPI2_HOST) ? &GPSPI2 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -34,13 +35,15 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : NULL)
 
+#define SPI_LL_PERIPH_CS_NUM(i)   6            //c3 only support gpspi2
 #define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 2            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
+#define SPI_LL_PERIPH_BITWIDTH(host) (4)       //Supported line mode: DIO, DOUT, QIO, or QOUT
+#define SPI_LL_PERIPH_HAS_SCT(host)  ((host) == SPI2_HOST)  //If peripheral support SCT (DMA Segmented Configured Transaction) mode
 #define SPI_LL_MAX_SCT_CONF_LEN   (0x3FFFA)    //18 bits wide reg
 #define SPI_LL_SCT_CONF_BUF_NUM   (1 + 14)     //1-word-bitmap + 14-word-regs according to TRM
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
diff --git a/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h
index 617176baa29..2f197801709 100644
--- a/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h
@@ -28,6 +28,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) (((ID)==SPI2_HOST) ? &GPSPI2 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -35,16 +36,16 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : NULL)
 
+#define SPI_LL_PERIPH_CS_NUM(i)   6            //c5 only support gpspi2
 #define SPI_LL_DMA_MAX_BIT_LEN    SPI_MS_DATA_BITLEN
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
 #define SPI_LL_TX_MINI_EXTRA_BITS 1            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
-#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV      1  //clock source have divider before peripheral
-#define SPI_LL_SRC_PRE_DIV_MAX    (PCR_SPI2_CLKM_DIV_NUM + 1)   //source pre divider max
+#define SPI_LL_PERIPH_BITWIDTH(host) (4)       //Supported line mode: DIO, DOUT, QIO, or QOUT
+#define SPI_LL_SRC_PRE_DIV_MAX    (PCR_SPI2_CLKM_DIV_NUM + 1)   //source pre divider max before peripheral
 #define SPI_LL_PERIPH_CLK_DIV_MAX   ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
 
 /**
diff --git a/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h
index 0d0eeb31271..7006df33fa9 100644
--- a/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) (((ID)==SPI2_HOST) ? &GPSPI2 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -34,13 +35,15 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : NULL)
 
+#define SPI_LL_PERIPH_CS_NUM(i)   6            //c6 only support gpspi2
 #define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 2            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
+#define SPI_LL_PERIPH_BITWIDTH(host) (4)       //Supported line mode: DIO, DOUT, QIO, or QOUT
+#define SPI_LL_PERIPH_HAS_SCT(host)  ((host) == SPI2_HOST)  //If peripheral support SCT (DMA Segmented Configured Transaction) mode
 #define SPI_LL_MAX_SCT_CONF_LEN   (0x3FFFA)    //18 bits wide reg
 #define SPI_LL_SCT_CONF_BUF_NUM   (1 + 14)     //1-word-bitmap + 14-word-regs according to TRM
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
diff --git a/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h
index 4cf7f99baf2..31aa102ce01 100644
--- a/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h
@@ -28,6 +28,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) (((ID)==SPI2_HOST) ? &GPSPI2 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -35,16 +36,16 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : NULL)
 
+#define SPI_LL_PERIPH_CS_NUM(i)   6            //c61 only support gpspi2
 #define SPI_LL_DMA_MAX_BIT_LEN    SPI_MS_DATA_BITLEN
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
+#define SPI_LL_PERIPH_BITWIDTH(host)    (4) // Supported line mode: SPI2: 1, 2, 4
 #define SPI_LL_TX_MINI_EXTRA_BITS 1            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
-#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV      1  //clock source have divider before peripheral
-#define SPI_LL_SRC_PRE_DIV_MAX    (PCR_SPI2_CLKM_DIV_NUM + 1)   //source pre divider max
+#define SPI_LL_SRC_PRE_DIV_MAX    (PCR_SPI2_CLKM_DIV_NUM + 1)   //source pre divider max before peripheral
 #define SPI_LL_PERIPH_CLK_DIV_MAX   ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
 
 /**
diff --git a/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h
index 7f59061638f..814d0e4f0c1 100644
--- a/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h
@@ -29,6 +29,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) (((ID)==SPI2_HOST) ? &GPSPI2 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -36,13 +37,15 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : NULL)
 
+#define SPI_LL_PERIPH_CS_NUM(i)   6            //h2 only support gpspi2
 #define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102) ? 1 : 2)  //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
+#define SPI_LL_PERIPH_BITWIDTH(host)    (4)    // Supported line mode: SPI2: 1, 2, 4
+#define SPI_LL_PERIPH_HAS_SCT(host)  ((host) == SPI2_HOST)  //If peripheral support SCT (DMA Segmented Configured Transaction) mode
 #define SPI_LL_MAX_SCT_CONF_LEN   (0x3FFFA)    //18 bits wide reg
 #define SPI_LL_SCT_CONF_BUF_NUM   (1 + 14)     //1-word-bitmap + 14-word-regs according to TRM
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
diff --git a/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h
index b5ce3b33880..1e7331c3d3f 100644
--- a/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h
@@ -29,7 +29,7 @@
 extern "C" {
 #endif
 
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : NULL)
+#define SPI_LL_GET_HW(ID) (((ID)==SPI2_HOST) ? &GPSPI2 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -37,11 +37,15 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
+
+#define SPI_LL_PERIPH_CS_NUM(i)   6            //h21 only support gpspi2
 #define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 1            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
+#define SPI_LL_PERIPH_BITWIDTH(host) (4)       //Supported line mode: DIO, DOUT, QIO, or QOUT
+#define SPI_LL_PERIPH_HAS_SCT(host)  ((host) == SPI2_HOST)  //If peripheral support SCT (DMA Segmented Configured Transaction) mode
 #define SPI_LL_MAX_SCT_CONF_LEN   (0x3FFFA)    //18 bits wide reg
 #define SPI_LL_SCT_CONF_BUF_NUM   (1 + 14)     //1-word-bitmap + 14-word-regs according to TRM
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
diff --git a/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h
index 679417f8416..ba6cd597220 100644
--- a/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h
@@ -28,7 +28,7 @@
 extern "C" {
 #endif
 
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : (((ID)==2) ? &GPSPI3 : NULL))
+#define SPI_LL_GET_HW(ID) ((ID)==SPI2_HOST ? &GPSPI2 : (ID)==SPI3_HOST ? &GPSPI3 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -37,14 +37,15 @@ extern "C" {
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
 
+#define SPI_LL_PERIPH_CS_NUM(i)   (((i)==0)? 2: (((i)==1)? 6: 3))
 #define SPI_LL_DMA_MAX_BIT_LEN    SPI_MS_DATA_BITLEN
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 1            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
+#define SPI_LL_PERIPH_BITWIDTH(host)    (4)    // Supported line mode: SPI2: 1, 2, 4
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
-#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV      1  //clock source have divider before peripheral
-#define SPI_LL_SRC_PRE_DIV_MAX    (PCR_SPI2_CLKM_DIV_NUM + 1)   //source pre divider max
+#define SPI_LL_SRC_PRE_DIV_MAX    (PCR_SPI2_CLKM_DIV_NUM + 1)   //source pre divider max before peripheral
 #define SPI_LL_PERIPH_CLK_DIV_MAX   ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
 /**
  * The data structure holding calculated clock configuration. Since the
diff --git a/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h
index 1f4984bc787..e1c44fef8d4 100644
--- a/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h
@@ -28,6 +28,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) ((ID)==SPI2_HOST ? &GPSPI2 : (ID)==SPI3_HOST ? &GPSPI3 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -35,15 +36,15 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : (((ID)==2) ? &GPSPI3 : NULL))
 
+#define SPI_LL_PERIPH_CS_NUM(i)   (((i)==0)? 2: (((i)==1)? 6: 3))
 #define SPI_LL_DMA_MAX_BIT_LEN    SPI_MS_DATA_BITLEN
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 1            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
-#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV      1  //clock source have divider before peripheral
-#define SPI_LL_SRC_PRE_DIV_MAX    (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM + 1)   //source pre divider max
+#define SPI_LL_PERIPH_BITWIDTH(host)    ((host == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8
+#define SPI_LL_SRC_PRE_DIV_MAX    (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM + 1)   //source pre divider max before peripheral
 #define SPI_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
 
diff --git a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h
index 88ad203d4be..5669114254b 100644
--- a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h
@@ -31,6 +31,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) ((ID)==SPI2_HOST ? &GPSPI2 : (ID)==SPI3_HOST ? &GPSPI3 : NULL)
 /// Registers to reset during initialization. Don't use in app.
 #define SPI_LL_DMA_FIFO_RST_MASK (SPI_AHBM_RST | SPI_AHBM_FIFO_RST)
 /// Interrupt not used. Don't use in app.
@@ -41,14 +42,16 @@ extern "C" {
 #define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_OCT | SPI_FWRITE_QUAD | SPI_FWRITE_DUAL)
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : (((ID)==2) ? &GPSPI3 : NULL))
 
+#define SPI_LL_PERIPH_CS_NUM(i)   (((i)==0)? 2: (((i)==1)? 6: 3))
 #define SPI_LL_DMA_CHANNEL_NUM    (3)
 #define SPI_LL_DMA_MAX_BIT_LEN    (1 << 23)    //reg len: 23 bits
 #define SPI_LL_CPU_MAX_BIT_LEN    (18 * 32)    //Fifo len: 18 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 1            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 8            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (8192)
+#define SPI_LL_PERIPH_BITWIDTH(host)    ((host == 2) ? 1 : 8) // Supported line mode: SPI3: 1, SPI1/2: 1, 2, 4, 8
+#define SPI_LL_PERIPH_HAS_SCT(host)  ((host) == SPI2_HOST)  //If peripheral support SCT (DMA Segmented Configured Transaction) mode
 #define SPI_LL_MAX_SCT_CONF_LEN   0x7FFFFD     //23 bit wide reg
 #define SPI_LL_SCT_CONF_BUF_NUM   (1 + 27)     //1-word-bitmap + 27-word-regs according to TRM
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
diff --git a/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h
index 086626e7136..ffb7e300188 100644
--- a/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h
+++ b/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h
@@ -27,6 +27,7 @@
 extern "C" {
 #endif
 
+#define SPI_LL_GET_HW(ID) ((ID)==SPI2_HOST ? &GPSPI2 : (ID)==SPI3_HOST ? &GPSPI3 : NULL)
 /// Interrupt not used. Don't use in app.
 #define SPI_LL_UNUSED_INT_MASK  (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
 /// These 2 masks together will set SPI transaction to one line mode
@@ -36,13 +37,15 @@ extern "C" {
 
 /// Swap the bit order to its correct place to send
 #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
-#define SPI_LL_GET_HW(ID) (((ID)==1) ? &GPSPI2 : (((ID)==2) ? &GPSPI3 : NULL))
 
+#define SPI_LL_PERIPH_CS_NUM(i)   (((i)==0)? 2: (((i)==1)? 6: 3))
 #define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_TX_MINI_EXTRA_BITS 2            //Minimum length of TX non byte aligned data in bits
 #define SPI_LL_RX_MINI_EXTRA_BITS 1            //Minimum length of RX non byte aligned data in bits
 #define SPI_LL_MAX_PRE_DIV_NUM    (16)
+#define SPI_LL_PERIPH_BITWIDTH(host)    ((host == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8
+#define SPI_LL_PERIPH_HAS_SCT(host)  ((host) == SPI2_HOST)  //If peripheral support SCT (DMA Segmented Configured Transaction) mode
 #define SPI_LL_MAX_SCT_CONF_LEN   (0x3FFFA)    //18 bits wide reg
 #define SPI_LL_SCT_CONF_BUF_NUM   (1 + 14)     //1-word-bitmap + 14-word-regs according to TRM
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
diff --git a/components/esp_hal_gpspi/include/hal/spi_hal.h b/components/esp_hal_gpspi/include/hal/spi_hal.h
index 4561c4f34e4..2af6dafa2b9 100644
--- a/components/esp_hal_gpspi/include/hal/spi_hal.h
+++ b/components/esp_hal_gpspi/include/hal/spi_hal.h
@@ -27,7 +27,6 @@
 #pragma once
 #include "esp_err.h"
 #include "soc/soc_caps.h"
-#include "soc/spi_periph.h"
 #include "hal/spi_types.h"
 #if SOC_GPSPI_SUPPORTED
 #include "hal/spi_ll.h"
@@ -127,7 +126,6 @@ typedef struct {
     };//boolean configurations
 } spi_hal_dev_config_t;
 
-#ifdef SOC_SPI_SCT_SUPPORTED
 /**
  * SCT mode required configurations, per segment
  */
@@ -152,7 +150,6 @@ typedef struct {
     /* DONE State */
     int cs_hold;                        ///< Hold time of CS inactive edge after the last SPI clock
 } spi_hal_seg_config_t;
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
 
 /**
  * Init the peripheral and the context.
@@ -312,7 +309,6 @@ void spi_hal_cal_timing(int source_freq_hz, int eff_clk, bool gpio_is_used, int
  */
 int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns);
 
-#ifdef SOC_SPI_SCT_SUPPORTED
 /*----------------------------------------------------------
  * Segmented-Configure-Transfer (SCT) Mode
  * ---------------------------------------------------------*/
@@ -354,7 +350,6 @@ void spi_hal_sct_set_conf_bits_len(spi_hal_context_t *hal, uint32_t conf_len);
  * Set conf_bitslen base to HW for sct, only supported on s2.
  */
 #define spi_hal_sct_setup_conf_base(hal, conf_base)     spi_ll_set_conf_base_bitslen((hal)->hw, conf_base)
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
 #endif  //#if SOC_GPSPI_SUPPORTED
 
 #ifdef __cplusplus
diff --git a/components/esp_hal_gpspi/spi_hal.c b/components/esp_hal_gpspi/spi_hal.c
index 92c71085f63..91ffb8a125f 100644
--- a/components/esp_hal_gpspi/spi_hal.c
+++ b/components/esp_hal_gpspi/spi_hal.c
@@ -9,11 +9,12 @@
 #include "hal/spi_hal.h"
 #include "soc/soc_caps.h"
 #include "soc/clk_tree_defs.h"
+#include "soc/spi_periph.h"
 
 void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id)
 {
     memset(hal, 0, sizeof(spi_hal_context_t));
-    spi_dev_t *hw = SPI_LL_GET_HW(host_id);
+    spi_dev_t *hw = spi_periph_signal[host_id].hw;
     hal->hw = hw;
     spi_ll_master_init(hw);
 
@@ -45,7 +46,7 @@ void spi_hal_deinit(spi_hal_context_t *hal)
     }
 }
 
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
 void spi_hal_sct_init(spi_hal_context_t *hal)
 {
     spi_ll_conf_state_enable(hal->hw, true);
@@ -63,7 +64,7 @@ void spi_hal_sct_deinit(spi_hal_context_t *hal)
     spi_ll_clear_int_stat(hal->hw);
     spi_ll_enable_int(hal->hw); //recover trans_done intr
 }
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
+#endif  //#ifdef SPI_LL_PERIPH_HAS_SCT
 
 int spi_hal_master_cal_clock(int fapb, int hz, int duty_cycle)
 {
diff --git a/components/esp_hal_gpspi/spi_hal_iram.c b/components/esp_hal_gpspi/spi_hal_iram.c
index c22351f48de..f03bffcc91c 100644
--- a/components/esp_hal_gpspi/spi_hal_iram.c
+++ b/components/esp_hal_gpspi/spi_hal_iram.c
@@ -264,7 +264,7 @@ void spi_hal_fetch_result(const spi_hal_context_t *hal)
     }
 }
 
-#ifdef SOC_SPI_SCT_SUPPORTED
+#ifdef SPI_LL_PERIPH_HAS_SCT
 /*------------------------------------------------------------------------------
  * Segmented-Configure-Transfer
 *----------------------------------------------------------------------------*/
@@ -294,4 +294,4 @@ void spi_hal_sct_format_conf_buffer(spi_hal_context_t *hal, const spi_hal_seg_co
 #endif
 }
 
-#endif  //#ifdef SOC_SPI_SCT_SUPPORTED
+#endif  //#ifdef SPI_LL_PERIPH_HAS_SCT
diff --git a/components/esp_hal_gpspi/spi_slave_hal.c b/components/esp_hal_gpspi/spi_slave_hal.c
index c638638ac51..1e7d3b905b5 100644
--- a/components/esp_hal_gpspi/spi_slave_hal.c
+++ b/components/esp_hal_gpspi/spi_slave_hal.c
@@ -6,10 +6,11 @@
 #include "hal/spi_slave_hal.h"
 #include "hal/spi_ll.h"
 #include "soc/soc_caps.h"
+#include "soc/spi_periph.h"
 
 void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config_t *hal_config)
 {
-    hal->hw = SPI_LL_GET_HW(hal_config->host_id);
+    hal->hw = spi_periph_signal[hal_config->host_id].hw;
 
     spi_ll_slave_init(hal->hw);
 
diff --git a/components/esp_hal_gpspi/spi_slave_hd_hal.c b/components/esp_hal_gpspi/spi_slave_hd_hal.c
index d6278a04212..676940bba51 100644
--- a/components/esp_hal_gpspi/spi_slave_hd_hal.c
+++ b/components/esp_hal_gpspi/spi_slave_hd_hal.c
@@ -13,12 +13,13 @@
 #include "soc/lldesc.h"
 #include "soc/soc_caps.h"
 #include "soc/soc.h"   //for SOC_NON_CACHEABLE_OFFSET_SRAM
+#include "soc/spi_periph.h"
 #include "hal/spi_slave_hd_hal.h"
 #include "hal/assert.h"
 
 void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config)
 {
-    spi_dev_t *hw = SPI_LL_GET_HW(hal_config->host_id);
+    spi_dev_t *hw = spi_periph_signal[hal_config->host_id].hw;
     hal->dev = hw;
     hal->dma_enabled = hal_config->dma_enabled;
     hal->append_mode = hal_config->append_mode;
diff --git a/components/esp_hal_mspi/include/hal/spi_flash_hal.h b/components/esp_hal_mspi/include/hal/spi_flash_hal.h
index 6b0ffd94b07..ae85f7dc2d9 100644
--- a/components/esp_hal_mspi/include/hal/spi_flash_hal.h
+++ b/components/esp_hal_mspi/include/hal/spi_flash_hal.h
@@ -86,7 +86,7 @@ typedef struct {
     bool iomux;             ///< Whether the IOMUX is used, used for timing compensation.
     int input_delay_ns;     ///< Input delay on the MISO pin after the launch clock, used for timing compensation.
     spi_host_device_t host_id;            ///< SPI peripheral ID.
-    int cs_num;             ///< Which cs pin is used, 0-(SOC_SPI_PERIPH_CS_NUM-1).
+    int cs_num;             ///< Which cs pin is used, 0-(SPI_LL_PERIPH_CS_NUM-1).
     bool auto_sus_en;       ///< Auto suspend feature enable bit 1: enable, 0: disable.
     bool octal_mode_en;     ///< Octal spi flash mode enable bit 1: enable, 0: disable.
     bool using_timing_tuning;               ///< System exist SPI0/1 timing tuning, using value from system directly if set to 1.
diff --git a/components/esp_hal_mspi/spi_flash_hal.c b/components/esp_hal_mspi/spi_flash_hal.c
index 5a9f443a436..d4f52a55fed 100644
--- a/components/esp_hal_mspi/spi_flash_hal.c
+++ b/components/esp_hal_mspi/spi_flash_hal.c
@@ -13,6 +13,7 @@
 #include "soc/soc_caps.h"
 #include "hal/gpio_caps.h"    //for GPIO_CAPS_GET(MATRIX_DELAY_NS)
 #include "hal/spi_flash_hal.h"
+#include "hal/spi_ll.h"
 #include "hal/assert.h"
 #include "hal/log.h"
 #include "hal/spi_flash_types.h"
@@ -101,7 +102,7 @@ static inline int extra_dummy_under_timing_tuning(const spi_flash_hal_config_t *
 
 esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg)
 {
-    if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
+    if (cfg->cs_num >= SPI_LL_PERIPH_CS_NUM(cfg->host_id)) {
         return ESP_ERR_INVALID_ARG;
     }
 
diff --git a/components/esp_hal_mspi/spi_flash_hal_common.inc b/components/esp_hal_mspi/spi_flash_hal_common.inc
index a0e9ec86c0b..28120a7612b 100644
--- a/components/esp_hal_mspi/spi_flash_hal_common.inc
+++ b/components/esp_hal_mspi/spi_flash_hal_common.inc
@@ -15,6 +15,7 @@
 #include <string.h>
 #include <stdlib.h>
 #include "hal/spi_flash_hal.h"
+#include "hal/spi_ll.h"
 #include "hal/assert.h"
 #include "soc/soc_caps.h"
 #include "soc/chip_revision.h"
@@ -96,7 +97,7 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
      */
     bool conf_required = ((extra_bits & SPI_FLASH_CONFIG_CONF_BITS) != 0);
 
-    if ((SOC_SPI_MAX_BITWIDTH(spi_flash_ll_hw_get_id(dev)) < 2) && io_mode > SPI_FLASH_FASTRD) {
+    if ((SPI_LL_PERIPH_BITWIDTH(spi_flash_ll_hw_get_id(dev)) < 2) && io_mode > SPI_FLASH_FASTRD) {
         return ESP_ERR_NOT_SUPPORTED;
     }
 
diff --git a/components/esp_hw_support/spi_bus_lock.c b/components/esp_hw_support/spi_bus_lock.c
index d128205abf8..387ecbc6393 100644
--- a/components/esp_hw_support/spi_bus_lock.c
+++ b/components/esp_hw_support/spi_bus_lock.c
@@ -12,6 +12,7 @@
 #include "esp_private/critical_section.h"
 #include "esp_intr_alloc.h"
 #include "soc/soc_caps.h"
+#include "hal/spi_ll.h"
 #include "stdatomic.h"
 #include "esp_log.h"
 #include "esp_check.h"
@@ -864,7 +865,7 @@ static spi_bus_lock_t main_spi_bus_lock = {
     .acquiring_dev = NULL,
     .dev = {ATOMIC_VAR_INIT((intptr_t)&lock_main_flash_dev)},
     .new_req = 0,
-    .periph_cs_num = SOC_SPI_PERIPH_CS_NUM(0),
+    .periph_cs_num = SPI_LL_PERIPH_CS_NUM(0),
 };
 const spi_bus_lock_handle_t g_main_spi_bus_lock = &main_spi_bus_lock;
 
diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
index e83f4ee306d..7c38519b52c 100644
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -531,10 +531,6 @@ config SOC_SPI_MAXIMUM_BUFFER_SIZE
     int
     default 64
 
-config SOC_MEMSPI_ENCRYPTION_ALIGNMENT
-    int
-    default 16
-
 config SOC_LP_TIMER_BIT_WIDTH_LO
     int
     default 32
@@ -611,6 +607,10 @@ config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
     bool
     default y
 
+config SOC_MEMSPI_ENCRYPTION_ALIGNMENT
+    int
+    default 16
+
 config SOC_SHA_SUPPORT_PARALLEL_ENG
     bool
     default y
diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index 65f48d08992..5b316a9dbaf 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -263,13 +263,8 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM              3
-#define SOC_SPI_PERIPH_CS_NUM(i)        3
-
 #define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1  //Support enabling MOSI and MISO phases together under Halfduplex mode
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
-#define SOC_SPI_MAX_BITWIDTH(host_id)   (4) // Supported line mode: DIO, DOUT, QIO, or QOUT
-
-#define SOC_MEMSPI_ENCRYPTION_ALIGNMENT           16    /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */
 
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
@@ -303,6 +298,7 @@
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE         (1)
+#define SOC_MEMSPI_ENCRYPTION_ALIGNMENT           16    /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */
 
 /*--------------------------- SHA CAPS ---------------------------------------*/
 /* ESP32 style SHA engine, where multiple states can be stored in parallel */
diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
index f36792cf488..943d5f27948 100644
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -211,12 +211,8 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM              2
-#define SOC_SPI_PERIPH_CS_NUM(i)        6
-
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2   1
-#define SOC_SPI_MAX_BITWIDTH(host_id)   (4) // Supported line mode: SPI2: 1, 2, 4
-#define SOC_SPI_SCT_SUPPORTED(host_id)  ((host_id) == 1)
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index a5b6e67567f..ef9c55eb48d 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -287,11 +287,8 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  2
-#define SOC_SPI_PERIPH_CS_NUM(i)            6
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       (4) // Supported line mode: SPI2: 1, 2, 4
-#define SOC_SPI_SCT_SUPPORTED(host_id)      ((host_id) == 1)
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index fd0e611b972..45d7668ef50 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -398,11 +398,9 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  2
-#define SOC_SPI_PERIPH_CS_NUM(i)            6
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       (4) // Supported line mode: SPI2: 1, 2, 4
 
 /*-------------------------- SPIRAM CAPS ----------------------------------------*/
 #define SOC_SPIRAM_XIP_SUPPORTED        1
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 05d60318dd1..b0c81995307 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -348,12 +348,9 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  2
-#define SOC_SPI_PERIPH_CS_NUM(i)            6
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       (4) // Supported line mode: SPI2: 1, 2, 4
-#define SOC_SPI_SCT_SUPPORTED(host_id)      ((host_id) == 1)
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index 7bcce02ad3e..f842a0169f2 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -304,11 +304,9 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  2
-#define SOC_SPI_PERIPH_CS_NUM(i)            6
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       (4) // Supported line mode: SPI2: 1, 2, 4
 
 /*-------------------------- SPIRAM CAPS ----------------------------------------*/
 #define SOC_SPIRAM_XIP_SUPPORTED        1
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index bded92df9a6..66d7f68926c 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -363,12 +363,9 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  2
-#define SOC_SPI_PERIPH_CS_NUM(i)            6
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       (4) // Supported line mode: SPI2: 1, 2, 4
-#define SOC_SPI_SCT_SUPPORTED(host_id)      ((host_id) == 1)
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h
index d884a663234..07da7d3d9cc 100644
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -342,11 +342,8 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  2
-#define SOC_SPI_PERIPH_CS_NUM(i)            6
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       (4) // Supported line mode: SPI2: 1, 2, 4
-#define SOC_SPI_SCT_SUPPORTED(host_id)      ((host_id) == 1)
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
index 74aef76b993..f81103e9f30 100644
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -362,10 +362,8 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  3
-#define SOC_SPI_PERIPH_CS_NUM(i)            (((i)==0)? 2: (((i)==1)? 6: 3))
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       (4) // Supported line mode: SPI2: 1, 2, 4
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index ef43703a6fe..b0556ccb605 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -508,12 +508,10 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  3
-#define SOC_SPI_PERIPH_CS_NUM(i)            6
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_SUPPORT_OCT                 1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       ((host_id == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8
 
 /*-------------------------- LP SPI CAPS ----------------------------------------*/
 #define SOC_LP_SPI_MAXIMUM_BUFFER_SIZE     64
diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h
index 2621012d4ef..631f7aff845 100644
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -267,14 +267,11 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  3
-#define SOC_SPI_PERIPH_CS_NUM(i)            (((i)==0)? 2: (((i)==1)? 6: 3))
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         72
 /// The SPI Slave half duplex mode has been updated greatly in ESP32-S2
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_HD_BOTH_INOUT_SUPPORTED     1   //Support enabling MOSI and MISO phases together under Halfduplex mode
 #define SOC_SPI_SUPPORT_OCT                 1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       ((host_id == 2) ? 1 : 8) // Supported line mode: SPI3: 1, SPI1/2: 1, 2, 4, 8
-#define SOC_SPI_SCT_SUPPORTED(host_id)      ((host_id) == 1)
 
 // Peripheral supports output given level during its "dummy phase"
 // Only SPI1 supports this feature
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index d12fc77af9d..228893254ed 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -289,12 +289,9 @@
 
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM                  3
-#define SOC_SPI_PERIPH_CS_NUM(i)            (((i)==0)? 2: (((i)==1)? 6: 3))
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_SUPPORT_OCT                 1
-#define SOC_SPI_MAX_BITWIDTH(host_id)       ((host_id == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8
-#define SOC_SPI_SCT_SUPPORTED(host_id)      ((host_id) == 1)
 
 /*-------------------------- SPIRAM CAPS ----------------------------------------*/
 #define SOC_SPIRAM_SUPPORTED            1
diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c
index 684f6f79fa0..5c9eb78edf5 100644
--- a/components/spi_flash/esp_flash_spi_init.c
+++ b/components/spi_flash/esp_flash_spi_init.c
@@ -28,6 +28,7 @@
 #include "soc/soc_caps.h"
 #include "hal/spi_flash_hal.h"
 #include "hal/mspi_ll.h"
+#include "hal/spi_ll.h"
 
 #include "esp_flash.h"
 #include "esp_flash_spi_init.h"
@@ -240,7 +241,7 @@ static esp_err_t acquire_spi_device(const esp_flash_spi_device_config_t *config,
         }
     } else {
         const bool is_main_flash = (config->host_id == SPI1_HOST && config->cs_id == 0);
-        if (config->cs_id >= SOC_SPI_PERIPH_CS_NUM(config->host_id) || config->cs_id < 0 || is_main_flash) {
+        if (config->cs_id >= SPI_LL_PERIPH_CS_NUM(config->host_id) || config->cs_id < 0 || is_main_flash) {
             ESP_LOGE(TAG, "Not valid CS.");
             ret = ESP_ERR_INVALID_ARG;
         } else {
diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
index c23887d5303..adf3b5f688f 100644
--- a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
+++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
@@ -22,6 +22,7 @@
 #include "driver/gpio.h"
 #include "esp_private/gpio.h"
 #include "soc/io_mux_reg.h"
+#include "hal/spi_ll.h"
 #include "sdkconfig.h"
 
 #include "esp_spi_flash_counters.h"
@@ -614,7 +615,7 @@ void test_permutations_part(const flashtest_config_t* config, esp_partition_t* p
             //the io mode will switch frequently.
             esp_flash_io_mode_t io_mode = SPI_FLASH_READ_MODE_MIN;
             while (io_mode != SPI_FLASH_QIO + 1) {
-                if (io_mode > SPI_FLASH_FASTRD && (SOC_SPI_MAX_BITWIDTH(config->host_id) < 2)) {
+                if (io_mode > SPI_FLASH_FASTRD && (SPI_LL_PERIPH_BITWIDTH(config->host_id) < 2)) {
                     io_mode++;
                     continue;
                 }
diff --git a/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c b/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c
index 480921c9826..ab5d823762b 100644
--- a/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c
+++ b/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c
@@ -30,9 +30,9 @@
 
 //---------This should be negotiated with the Slave!!!!-------------//
 #define SLAVE_READY_FLAG    0x88
-#define READY_FLAG_REG      0
-#define SYNC_REG_FROM_HOST  (14 * 4)
-#define SYNC_REG_TO_HOST    (15 * 4)
+#define READY_FLAG_REG      (0 * 4) // first register is used for ready flag
+#define SYNC_REG_FROM_HOST  (1 * 4) // second register is used for sync from host
+#define SYNC_REG_TO_HOST    (2 * 4) // third register is used for sync to host
 
 static void init_driver(spi_device_handle_t *out_spi, essl_handle_t *out_essl)
 {
diff --git a/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c b/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c
index 88065a994d9..e6dd9d7e003 100644
--- a/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c
+++ b/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c
@@ -26,12 +26,13 @@
 #define HOST_ID             SPI2_HOST
 #define QUEUE_SIZE          6
 #define TRANSACTION_LEN     64
-#define SYNC_REG_FROM_HOST  (14 * 4)
-#define SYNC_REG_TO_HOST    (15 * 4)
 
 //---------This should be negotiated with the Master!!!!-------------//
 #define SLAVE_READY_FLAG    0x88
-#define READY_FLAG_REG      0
+#define SLAVE_SHARE_REG_NUM 3
+#define READY_FLAG_REG      (0 * 4) // first register is used for ready flag
+#define SYNC_REG_FROM_HOST  (1 * 4) // second register is used for sync from host
+#define SYNC_REG_TO_HOST    (2 * 4) // third register is used for sync to host
 
 struct trans_link_s {
     spi_slave_hd_data_t trans;
@@ -242,8 +243,8 @@ void app_main(void)
     init_slave_hd();
 
     //Init the shared register
-    uint8_t init_value[SOC_SPI_MAXIMUM_BUFFER_SIZE] = {0x0};
-    spi_slave_hd_write_buffer(HOST_ID, 0, init_value, SOC_SPI_MAXIMUM_BUFFER_SIZE);
+    uint8_t init_value[SLAVE_SHARE_REG_NUM * 4] = {0x0};
+    spi_slave_hd_write_buffer(HOST_ID, 0, init_value, sizeof(init_value));
 
     uint8_t ready_flag = SLAVE_READY_FLAG;
     spi_slave_hd_write_buffer(HOST_ID, READY_FLAG_REG, &ready_flag, 4);
diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c
index e13c3b14990..e59e67f6e7e 100644
--- a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c
+++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c
@@ -33,6 +33,7 @@
  * The address and value should be negotiated with Master beforehand
  */
 //----------------------General Settings---------------------//
+#define SLAVE_SHARE_REG_NUM             5   // number of shared registers list below
 //Indicate Slave General Settings are ready
 #define SLAVE_READY_FLAG_REG            0
 #define SLAVE_READY_FLAG                0xEE
@@ -287,8 +288,8 @@ void app_main(void)
     init_slave_hd();
 
     //Reset the shared register to 0
-    uint8_t init_value[SOC_SPI_MAXIMUM_BUFFER_SIZE] = {0x0};
-    spi_slave_hd_write_buffer(SLAVE_HOST, 0, init_value, SOC_SPI_MAXIMUM_BUFFER_SIZE);
+    uint8_t init_value[SLAVE_SHARE_REG_NUM * 4] = {0x0};
+    spi_slave_hd_write_buffer(SLAVE_HOST, 0, init_value, sizeof(init_value));
 
     static uint32_t send_buf_size = 4800;
     spi_slave_hd_write_buffer(SLAVE_HOST, SLAVE_MAX_TX_BUF_LEN_REG, (uint8_t *)&send_buf_size, sizeof(send_buf_size));