Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat: enable support for aes and sha peripheral in esp32h4

Browse Source
This commit is contained in:
nilesh.kale
2026-01-07 12:41:21 +05:30
parent f2068bb34f
commit 5e94bc0942
9 changed files with 668 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+68
View File
@@ -111,6 +111,14 @@ config SOC_SYSTIMER_SUPPORTED
bool
default y
config SOC_AES_SUPPORTED
bool
default y
config SOC_SHA_SUPPORTED
bool
default y
config SOC_ECC_SUPPORTED
bool
default y
@@ -191,6 +199,26 @@ config SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 1
@@ -675,6 +703,46 @@ config SOC_PARLIO_SUPPORT_I80_LCD
bool
default y
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SHA_SUPPORT_SHA384
bool
default y
config SOC_SHA_SUPPORT_SHA512
bool
default y
config SOC_SHA_SUPPORT_SHA512_T
bool
default y
config SOC_ECC_CONSTANT_TIME_POINT_MUL
bool
default y
components/soc/esp32h4/include/soc/hwcrypto_reg.h
+10
View File
@@ -0,0 +1,10 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include "soc/aes_reg.h"
#include "soc/hmac_reg.h"
#include "soc/sha_reg.h"
components/soc/esp32h4/include/soc/soc_caps.h
+18 -13
View File
@@ -65,8 +65,8 @@
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1
// #define SOC_SUPPORT_COEXISTENCE 1 // TODO: [ESP32H4] IDF-12251 IDF-12252 IDF-12253
// #define SOC_AES_SUPPORTED 0 // TODO: [ESP32H4] IDF-12266
// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32H4] IDF-12263
#define SOC_AES_SUPPORTED 1
#define SOC_SHA_SUPPORTED 1
// #define SOC_HMAC_SUPPORTED 0 // TODO: [ESP32H4] IDF-12257
#define SOC_ECC_SUPPORTED 1
#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
@@ -96,13 +96,15 @@
#define SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN 1
/*-------------------------- AES CAPS -----------------------------------------*/
// #define SOC_AES_SUPPORT_DMA (1)
#define SOC_AES_SUPPORT_DMA (1)
/* Has a centralized DMA, which is shared with all peripherals */
// #define SOC_AES_GDMA (1)
#define SOC_AES_GDMA (1)
// #define SOC_AES_SUPPORT_AES_128 (1)
// #define SOC_AES_SUPPORT_AES_256 (1)
#define SOC_AES_SUPPORT_AES_128 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
#define SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION (1)
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
@@ -349,19 +351,22 @@
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
// #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
// #define SOC_SHA_SUPPORT_DMA (1)
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
// #define SOC_SHA_SUPPORT_RESUME (1)
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
// #define SOC_SHA_GDMA (1)
#define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
// #define SOC_SHA_SUPPORT_SHA1 (1)
// #define SOC_SHA_SUPPORT_SHA224 (1)
// #define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA384 (1)
#define SOC_SHA_SUPPORT_SHA512 (1)
#define SOC_SHA_SUPPORT_SHA512_T (1)
/*--------------------------- ECC CAPS ---------------------------------------*/
#define SOC_ECC_CONSTANT_TIME_POINT_MUL 1