From 5e94bc0942caab5938f74ef061c4571408a676d9 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Wed, 13 Aug 2025 17:58:11 +0530 Subject: [PATCH] feat: enable support for aes and sha peripheral in esp32h4 --- .../esp_rom/esp32h4/include/esp32h4/rom/aes.h | 47 +++ .../esp_rom/esp32h4/include/esp32h4/rom/sha.h | 2 - components/hal/esp32h4/include/hal/aes_ll.h | 274 ++++++++++++++++++ components/hal/esp32h4/include/hal/sha_ll.h | 195 +++++++++++++ .../esp32h4/include/soc/Kconfig.soc_caps.in | 68 +++++ .../soc/esp32h4/include/soc/hwcrypto_reg.h | 10 + components/soc/esp32h4/include/soc/soc_caps.h | 31 +- components/soc/esp32h4/register/soc/sha_reg.h | 24 ++ .../soc/esp32h4/register/soc/sha_struct.h | 33 ++- 9 files changed, 668 insertions(+), 16 deletions(-) create mode 100644 components/esp_rom/esp32h4/include/esp32h4/rom/aes.h create mode 100644 components/hal/esp32h4/include/hal/aes_ll.h create mode 100644 components/hal/esp32h4/include/hal/sha_ll.h create mode 100644 components/soc/esp32h4/include/soc/hwcrypto_reg.h diff --git a/components/esp_rom/esp32h4/include/esp32h4/rom/aes.h b/components/esp_rom/esp32h4/include/esp32h4/rom/aes.h new file mode 100644 index 00000000000..4e78d028b39 --- /dev/null +++ b/components/esp_rom/esp32h4/include/esp32h4/rom/aes.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_AES_H_ +#define _ROM_AES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ets_sys.h" +#include "hal/efuse_hal.h" + +enum AES_TYPE { + AES_ENC, + AES_DEC, +}; + +enum AES_BITS { + AES128, + AES256 = 2, /* skipping enum value 1 to keep compatibility with chips that support AES-192 */ +}; + +// OR these with AES_BITS when writing to AES_MODE_REG +#define AES_MODE_ENCRYPT (0) +#define AES_MODE_DECRYPT (1<<2) + +void ets_aes_enable(void); + +void ets_aes_disable(void); + +ETS_STATUS ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); + +ETS_STATUS ets_aes_setkey_enc(const void *key, enum AES_BITS bits) __attribute__((deprecated)); + +ETS_STATUS ets_aes_setkey_dec(const void *key, enum AES_BITS bits) __attribute__((deprecated)); + +void ets_aes_block(const void *input, void *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_AES_H_ */ diff --git a/components/esp_rom/esp32h4/include/esp32h4/rom/sha.h b/components/esp_rom/esp32h4/include/esp32h4/rom/sha.h index 612fabc19c3..0d4a84c105a 100644 --- a/components/esp_rom/esp32h4/include/esp32h4/rom/sha.h +++ b/components/esp_rom/esp32h4/include/esp32h4/rom/sha.h @@ -14,8 +14,6 @@ extern "C" { #endif -//TODO: [ESP32H4] IDF-12263 inherit from verification branch, need check - typedef enum { SHA1 = 0, SHA2_224, diff --git a/components/hal/esp32h4/include/hal/aes_ll.h b/components/hal/esp32h4/include/hal/aes_ll.h new file mode 100644 index 00000000000..a065b078d33 --- /dev/null +++ b/components/hal/esp32h4/include/hal/aes_ll.h @@ -0,0 +1,274 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/aes_reg.h" +#include "soc/pcr_struct.h" +#include "hal/aes_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief State of AES accelerator, busy, idle or done + * + */ +typedef enum { + ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */ + ESP_AES_STATE_BUSY, /* Transform in progress */ + ESP_AES_STATE_DONE, /* Transform completed */ +} esp_aes_state_t; + +/** + * @brief Enable the bus clock for AES peripheral module + * + * @param enable true to enable the module, false to disable the module + */ +static inline void aes_ll_enable_bus_clock(bool enable) +{ + PCR.aes_conf.aes_clk_en = enable; +} + +/** + * @brief Reset the AES peripheral module + */ +static inline void aes_ll_reset_register(void) +{ + PCR.aes_conf.aes_rst_en = 1; + PCR.aes_conf.aes_rst_en = 0; +} + +/** + * @brief Write the encryption/decryption key to hardware + * + * @param key Key to be written to the AES hardware + * @param key_word_len Number of words in the key + * + * @return Number of bytes written to hardware, used for fault injection check + */ +static inline uint8_t aes_ll_write_key(const uint8_t *key, size_t key_word_len) +{ + /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */ + volatile uint8_t key_in_hardware = 0; + /* Memcpy to avoid potential unaligned access */ + uint32_t key_word; + for (int i = 0; i < key_word_len; i++) { + memcpy(&key_word, key + 4 * i, 4); + REG_WRITE(AES_KEY_0_REG + i * 4, key_word); + key_in_hardware += 4; + } + return key_in_hardware; +} + +/** + * @brief Sets the mode + * + * @param mode ESP_AES_ENCRYPT = 1, or ESP_AES_DECRYPT = 0 + * @param key_bytes Number of bytes in the key + */ +static inline void aes_ll_set_mode(int mode, uint8_t key_bytes) +{ + const uint32_t MODE_DECRYPT_BIT = 4; + unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT; + + /* See TRM for the mapping between keylength and mode bit */ + REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); +} + +/** + * @brief Writes message block to AES hardware + * + * @param input Block to be written + */ +static inline void aes_ll_write_block(const void *input) +{ + uint32_t input_word; + + for (int i = 0; i < AES_BLOCK_WORDS; i++) { + memcpy(&input_word, (uint8_t*)input + 4 * i, 4); + REG_WRITE(AES_TEXT_IN_0_REG + i * 4, input_word); + } +} + +/** + * @brief Read the AES block + * + * @param output the output of the transform, length = AES_BLOCK_BYTES + */ +static inline void aes_ll_read_block(void *output) +{ + uint32_t output_word; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < AES_BLOCK_WORDS; i++) { + output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH)); + /* Memcpy to avoid potential unaligned access */ + memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word)); + } +} + +/** + * @brief Starts block transform + * + */ +static inline void aes_ll_start_transform(void) +{ + REG_WRITE(AES_TRIGGER_REG, 1); +} + + +/** + * @brief Read state of AES accelerator + * + * @return esp_aes_state_t + */ +static inline esp_aes_state_t aes_ll_get_state(void) +{ + return (esp_aes_state_t)REG_READ(AES_STATE_REG); +} + + +/** + * @brief Set mode of operation + * + * @note Only used for DMA transforms + * + * @param mode Mode of operation to set (e.g., ECB, CBC, CTR, etc.) + */ +static inline void aes_ll_set_block_mode(esp_aes_mode_t mode) +{ + REG_WRITE(AES_BLOCK_MODE_REG, mode); +} + +/** + * @brief Set AES-CTR counter to INC32 + * + * @note Only affects AES-CTR mode + * + */ +static inline void aes_ll_set_inc(void) +{ + REG_WRITE(AES_INC_SEL_REG, 0); +} + +/** + * @brief Release the DMA + * + */ +static inline void aes_ll_dma_exit(void) +{ + REG_WRITE(AES_DMA_EXIT_REG, 0); +} + +/** + * @brief Sets the number of blocks to be transformed + * + * @note Only used for DMA transforms + * + * @param num_blocks Number of blocks to transform + */ +static inline void aes_ll_set_num_blocks(size_t num_blocks) +{ + REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); +} + +/* + * Write IV to hardware iv registers + */ +static inline void aes_ll_set_iv(const uint8_t *iv) +{ + uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM); + uint32_t iv_word; + + for (int i = 0; i < IV_WORDS; i++ ) { + /* Memcpy to avoid potential unaligned access */ + memcpy(&iv_word, iv + 4 * i, sizeof(iv_word)); + REG_WRITE(®_addr_buf[i], iv_word); + } +} + +/* + * Read IV from hardware iv registers + */ +static inline void aes_ll_read_iv(uint8_t *iv) +{ + uint32_t iv_word; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < IV_WORDS; i++) { + iv_word = REG_READ(AES_IV_MEM + (i * REG_WIDTH)); + /* Memcpy to avoid potential unaligned access */ + memcpy(iv + i * 4, &iv_word, sizeof(iv_word)); + } +} + +/** + * @brief Enable or disable DMA mode + * + * @param enable true to enable, false to disable. + */ +static inline void aes_ll_dma_enable(bool enable) +{ + REG_WRITE(AES_DMA_ENABLE_REG, enable); +} + +/** + * @brief Enable or disable transform completed interrupt + * + * @param enable true to enable, false to disable. + */ +static inline void aes_ll_interrupt_enable(bool enable) +{ + REG_WRITE(AES_INT_ENA_REG, enable); +} + +/** + * @brief Clears the interrupt + * + */ +static inline void aes_ll_interrupt_clear(void) +{ + REG_WRITE(AES_INT_CLEAR_REG, 1); +} + +/** + * @brief Enable the pseudo-round function during AES operations + * + * @param enable true to enable, false to disable + * @param base basic number of pseudo rounds, zero if disable + * @param increment increment number of pseudo rounds, zero if disable + * @param key_rng_cnt update frequency of the pseudo-key, zero if disable + */ +static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt) +{ + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_EN, enable); + + if (enable) { + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, base); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, increment); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, key_rng_cnt); + } else { + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, 0); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, 0); + REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, 0); + } +} + +/** + * @brief Check if the pseudo round function is supported + */ +static inline bool aes_ll_is_pseudo_rounds_function_supported(void) +{ + return true; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/include/hal/sha_ll.h b/components/hal/esp32h4/include/hal/sha_ll.h new file mode 100644 index 00000000000..e2bdba36944 --- /dev/null +++ b/components/hal/esp32h4/include/hal/sha_ll.h @@ -0,0 +1,195 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/hwcrypto_reg.h" +#include "soc/pcr_struct.h" +#include "hal/sha_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Enable the bus clock for SHA peripheral module + * + * @param enable true to enable the module, false to disable the module + */ +static inline void sha_ll_enable_bus_clock(bool enable) +{ + PCR.sha_conf.sha_clk_en = enable; +} + +/** + * @brief Reset the SHA peripheral module + */ +static inline void sha_ll_reset_register(void) +{ + PCR.sha_conf.sha_rst_en = 1; + PCR.sha_conf.sha_rst_en = 0; + + PCR.hmac_conf.hmac_rst_en = 0; + PCR.ecdsa_conf.ecdsa_rst_en = 0; +} + +/** + * @brief Load the mode for the SHA engine + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_set_mode(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); +} + +/** + * @brief Start a new SHA block conversions (no initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_start_block(esp_sha_type sha_type) +{ + (void) sha_type; + REG_WRITE(SHA_START_REG, 1); +} + +/** + * @brief Continue a SHA block conversion (initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_continue_block(esp_sha_type sha_type) +{ + (void) sha_type; + REG_WRITE(SHA_CONTINUE_REG, 1); +} + +/** + * @brief Start a new SHA message conversion using DMA (no initial hash in HW) + */ +static inline void sha_ll_start_dma(void) +{ + REG_WRITE(SHA_DMA_START_REG, 1); +} + +/** + * @brief Continue a SHA message conversion using DMA (initial hash in HW) + */ +static inline void sha_ll_continue_dma(void) +{ + REG_WRITE(SHA_DMA_CONTINUE_REG, 1); +} + +/** + * @brief Load the current hash digest to digest register + * + * @note Happens automatically on ESP32H4 + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_load(esp_sha_type sha_type) +{ +} + +/** + * @brief Sets the number of message blocks to be hashed + * + * @note DMA operation only + * + * @param num_blocks Number of message blocks to process + */ +static inline void sha_ll_set_block_num(size_t num_blocks) +{ + REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks); +} + +/** + * @brief Checks if the SHA engine is currently busy hashing a block + * + * @return true SHA engine busy + * @return false SHA engine idle + */ +static inline bool sha_ll_busy(void) +{ + return REG_READ(SHA_BUSY_REG); +} + +/** + * @brief Write a text (message) block to the SHA engine + * + * @param input_text Input buffer to be written to the SHA engine + * @param block_word_len Number of words in block + */ +static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len) +{ + uint32_t *data_words = (uint32_t *)input_text; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_2_SM_3_M_MEM); + + for (int i = 0; i < block_word_len; i++) { + REG_WRITE(®_addr_buf[i], data_words[i]); + } +} + +/** + * @brief Read the message digest from the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Buffer that message digest will be written to + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + const size_t REG_WIDTH = sizeof(uint32_t); + + for (size_t i = 0; i < digest_word_len; i++) { + digest_state_words[i] = REG_READ(SHA_2_SM_3_H_MEM + (i * REG_WIDTH)); + } + +} + +/** + * @brief Write the message digest to the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Message digest to be written to SHA engine + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_2_SM_3_H_MEM); + + for (int i = 0; i < digest_word_len; i++) { + REG_WRITE(®_addr_buf[i], digest_state_words[i]); + } +} + +/** + * @brief Sets SHA512_t T_string parameter + * + * @param t_string T_string parameter + */ +static inline void sha_ll_t_string_set(uint32_t t_string) +{ + REG_WRITE(SHA_T_STRING_REG, t_string); +} + +/** + * @brief Sets SHA512_t T_string parameter's length + * + * @param t_len T_string parameter length + */ +static inline void sha_ll_t_len_set(uint8_t t_len) +{ + REG_WRITE(SHA_T_LENGTH_REG, t_len); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 55dd944382f..d7afdcdfeb0 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -111,6 +111,14 @@ config SOC_SYSTIMER_SUPPORTED bool default y +config SOC_AES_SUPPORTED + bool + default y + +config SOC_SHA_SUPPORTED + bool + default y + config SOC_ECC_SUPPORTED bool default y @@ -191,6 +199,26 @@ config SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN bool default y +config SOC_AES_SUPPORT_DMA + bool + default y + +config SOC_AES_GDMA + bool + default y + +config SOC_AES_SUPPORT_AES_128 + bool + default y + +config SOC_AES_SUPPORT_AES_256 + bool + default y + +config SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION + bool + default y + config SOC_ADC_PERIPH_NUM int default 1 @@ -675,6 +703,46 @@ config SOC_PARLIO_SUPPORT_I80_LCD bool default y +config SOC_SHA_DMA_MAX_BUFFER_SIZE + int + default 3968 + +config SOC_SHA_SUPPORT_DMA + bool + default y + +config SOC_SHA_SUPPORT_RESUME + bool + default y + +config SOC_SHA_GDMA + bool + default y + +config SOC_SHA_SUPPORT_SHA1 + bool + default y + +config SOC_SHA_SUPPORT_SHA224 + bool + default y + +config SOC_SHA_SUPPORT_SHA256 + bool + default y + +config SOC_SHA_SUPPORT_SHA384 + bool + default y + +config SOC_SHA_SUPPORT_SHA512 + bool + default y + +config SOC_SHA_SUPPORT_SHA512_T + bool + default y + config SOC_ECC_CONSTANT_TIME_POINT_MUL bool default y diff --git a/components/soc/esp32h4/include/soc/hwcrypto_reg.h b/components/soc/esp32h4/include/soc/hwcrypto_reg.h new file mode 100644 index 00000000000..b625d3ba18b --- /dev/null +++ b/components/soc/esp32h4/include/soc/hwcrypto_reg.h @@ -0,0 +1,10 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include "soc/aes_reg.h" +#include "soc/hmac_reg.h" +#include "soc/sha_reg.h" diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 9cf6f4665f3..09a991e96d4 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -65,8 +65,8 @@ #define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 // #define SOC_SUPPORT_COEXISTENCE 1 // TODO: [ESP32H4] IDF-12251 IDF-12252 IDF-12253 -// #define SOC_AES_SUPPORTED 0 // TODO: [ESP32H4] IDF-12266 -// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32H4] IDF-12263 +#define SOC_AES_SUPPORTED 1 +#define SOC_SHA_SUPPORTED 1 // #define SOC_HMAC_SUPPORTED 0 // TODO: [ESP32H4] IDF-12257 #define SOC_ECC_SUPPORTED 1 #define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 @@ -96,13 +96,15 @@ #define SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN 1 /*-------------------------- AES CAPS -----------------------------------------*/ -// #define SOC_AES_SUPPORT_DMA (1) +#define SOC_AES_SUPPORT_DMA (1) /* Has a centralized DMA, which is shared with all peripherals */ -// #define SOC_AES_GDMA (1) +#define SOC_AES_GDMA (1) -// #define SOC_AES_SUPPORT_AES_128 (1) -// #define SOC_AES_SUPPORT_AES_256 (1) +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +#define SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION (1) /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ @@ -349,19 +351,22 @@ for SHA this means that the biggest safe amount of bytes is 31 blocks of 128 bytes = 3968 */ -// #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) -// #define SOC_SHA_SUPPORT_DMA (1) +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) /* The SHA engine is able to resume hashing from a user */ -// #define SOC_SHA_SUPPORT_RESUME (1) +#define SOC_SHA_SUPPORT_RESUME (1) /* Has a centralized DMA, which is shared with all peripherals */ -// #define SOC_SHA_GDMA (1) +#define SOC_SHA_GDMA (1) /* Supported HW algorithms */ -// #define SOC_SHA_SUPPORT_SHA1 (1) -// #define SOC_SHA_SUPPORT_SHA224 (1) -// #define SOC_SHA_SUPPORT_SHA256 (1) +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) +#define SOC_SHA_SUPPORT_SHA384 (1) +#define SOC_SHA_SUPPORT_SHA512 (1) +#define SOC_SHA_SUPPORT_SHA512_T (1) /*--------------------------- ECC CAPS ---------------------------------------*/ #define SOC_ECC_CONSTANT_TIME_POINT_MUL 1 diff --git a/components/soc/esp32h4/register/soc/sha_reg.h b/components/soc/esp32h4/register/soc/sha_reg.h index c461dba15cb..5d01ad68c6a 100644 --- a/components/soc/esp32h4/register/soc/sha_reg.h +++ b/components/soc/esp32h4/register/soc/sha_reg.h @@ -38,6 +38,30 @@ extern "C" { #define SHA_MODE_V 0x0000000FU #define SHA_MODE_S 0 +/** SHA_T_STRING_REG register + * SHA 512/t configuration register 0. + */ +#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) +/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + */ +#define SHA_T_STRING 0xFFFFFFFFU +#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) +#define SHA_T_STRING_V 0xFFFFFFFFU +#define SHA_T_STRING_S 0 + +/** SHA_T_LENGTH_REG register + * SHA 512/t configuration register 1. + */ +#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) +/** SHA_T_LENGTH : R/W; bitpos: [6:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + */ +#define SHA_T_LENGTH 0x0000007FU +#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) +#define SHA_T_LENGTH_V 0x0000007FU +#define SHA_T_LENGTH_S 0 + /** SHA_DMA_BLOCK_NUM_REG register * Block number register (only effective for DMA-SHA) */ diff --git a/components/soc/esp32h4/register/soc/sha_struct.h b/components/soc/esp32h4/register/soc/sha_struct.h index ee9f1c582bb..671cb41949a 100644 --- a/components/soc/esp32h4/register/soc/sha_struct.h +++ b/components/soc/esp32h4/register/soc/sha_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -125,6 +125,37 @@ typedef union { } sha_dma_rx_reset_reg_t; +/** Group: Configuration Register */ +/** Type of t_string register + * SHA 512/t configuration register 0. + */ +typedef union { + struct { + /** t_string : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t t_string:32; + }; + uint32_t val; +} sha_t_string_reg_t; + +/** Type of t_length register + * SHA 512/t configuration register 1. + */ +typedef union { + struct { + /** t_length : R/W; bitpos: [6:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t t_length:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} sha_t_length_reg_t; + + /** Group: Status Registers */ /** Type of busy register * Represents if SHA Accelerator is busy or not