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Merge branch 'bugfix/uart_tx_fifo_empty_threshold_v5.4' into 'release/v5.4'

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fix(uart): tx write bytes fails to use non-default tx fifo empty threshold (v5.4)

See merge request espressif/esp-idf!45891
This commit is contained in:
morris
2026-02-25 16:11:06 +08:00
parent 6e3a739678 e801bde973
commit 591dfac895
2 changed files with 13 additions and 9 deletions
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12
components/esp_driver_uart/include/driver/uart.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -248,7 +248,7 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baudrate);
* @param baudrate Pointer to accept value of UART baud rate
*
* @return
* - ESP_FAIL Parameter error
* - ESP_FAIL Parameter error or the UART port is not enabled
* - ESP_OK Success, result will be put in (*baudrate)
*
*/
@@ -365,7 +365,7 @@ esp_err_t uart_enable_rx_intr(uart_port_t uart_num);
esp_err_t uart_disable_rx_intr(uart_port_t uart_num);
/**
* @brief Disable UART TX interrupt (TX_FULL & TX_TIMEOUT INTERRUPT)
* @brief Disable UART TX interrupt (TX_FIFO_EMPTY INTERRUPT)
*
* @param uart_num UART port number
*
@@ -376,11 +376,11 @@ esp_err_t uart_disable_rx_intr(uart_port_t uart_num);
esp_err_t uart_disable_tx_intr(uart_port_t uart_num);
/**
* @brief Enable UART TX interrupt (TX_FULL & TX_TIMEOUT INTERRUPT)
* @brief Enable UART TX interrupt (TX_FIFO_EMPTY INTERRUPT)
*
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable 1: enable; 0: disable
* @param thresh Threshold of TX interrupt, 0 ~ UART_HW_FIFO_LEN(uart_num)
* @param enable Set to 1 to enable the interrupt
* @param thresh Threshold of TX FIFO empty interrupt, 0 ~ UART_HW_FIFO_LEN(uart_num). If -1 is given, threshold configuration will be skipped.
*
* @return
* - ESP_OK Success

10
components/esp_driver_uart/src/uart.c
View File

@@ -396,6 +396,7 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t *baudrate)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE(uart_ll_is_enabled(uart_num), ESP_FAIL, UART_TAG, "uart port not enabled, unable to get register values");
soc_module_clk_t src_clk;
uint32_t sclk_freq;
@@ -686,11 +687,14 @@ esp_err_t uart_disable_tx_intr(uart_port_t uart_num)
esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh)
{
(void)enable;
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((thresh < UART_HW_FIFO_LEN(uart_num)), ESP_FAIL, UART_TAG, "empty intr threshold error");
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), thresh);
if (thresh != -1) {
uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), thresh);
}
uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
return ESP_OK;
@@ -1577,7 +1581,7 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool
xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *)(src + offset), send_size, portMAX_DELAY);
size -= send_size;
offset += send_size;
uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT));
uart_enable_tx_intr(uart_num, 1, -1);
}
}
} else {
@@ -1587,7 +1591,7 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool
uint32_t sent = uart_enable_tx_write_fifo(uart_num, (const uint8_t *) src, size);
if (sent < size) {
p_uart_obj[uart_num]->tx_waiting_fifo = true;
uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT));
uart_enable_tx_intr(uart_num, 1, -1);
}
size -= sent;
src += sent;