change(esp_pm): add kconfig option for REGDMA sleep clock ICG

components/esp_hw_support/linker.lf

@@ -44,7 +44,7 @@ entries:
             pmu_param (noflash)
         if SOC_LIGHT_SLEEP_SUPPORTED = y:
             pmu_sleep (noflash)
-            if SOC_PM_SLEEP_CLK_ICG_USE_REGDMA = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP != y:
+            if PM_SLEEP_CLK_ICG_ENABLE = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP != y:
                 pmu_sleep_clock_icg:pmu_sleep_clock_icg_config (noflash)
             sleep_mspi (noflash)
             if PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32S31 != y:

components/esp_hw_support/port/esp32p4/CMakeLists.txt

@@ -12,7 +12,7 @@ set(srcs "rtc_clk_init.c"
 if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs "sar_periph_ctrl.c")
 
-    if(CONFIG_SOC_PM_SLEEP_CLK_ICG_USE_REGDMA AND NOT CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+    if(CONFIG_PM_SLEEP_CLK_ICG_ENABLE AND NOT CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
         list(APPEND srcs "pmu_sleep_clock_icg.c")
     endif()
 endif()

components/esp_hw_support/port/esp32p4/pmu_sleep.c

@@ -270,7 +270,7 @@ static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_c
 {
     pmu_ll_hp_set_icg_sysclk_enable (ctx->hal->dev, HP(SLEEP), (dig->icg_func[0] != 0));
     pmu_ll_hp_set_icg_func          (ctx->hal->dev, HP(SLEEP), dig->icg_func[0]); /* PMU FSM clock ICG config */
-#if SOC_PM_SLEEP_CLK_ICG_USE_REGDMA && !defined(CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+#if CONFIG_PM_SLEEP_CLK_ICG_ENABLE && !defined(CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
     pmu_sleep_clock_icg_config      (ctx->priv, dig->icg_func[1]); /* PMU REGDMA clock ICG config */
 #endif
     pmu_ll_hp_set_dig_pad_slp_sel   (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel);

components/esp_hw_support/sleep_modes.c

@@ -2799,6 +2799,14 @@ int32_t* esp_sleep_sub_mode_dump_config(FILE *stream) {
 #if SOC_PM_SUPPORT_PMU_CLK_ICG
 esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
 {
+#if SOC_PM_SLEEP_CLK_ICG_USE_REGDMA && !CONFIG_PM_SLEEP_CLK_ICG_ENABLE
+    static bool warned;
+    if (!warned) {
+        warned = true;
+        ESP_LOGW(TAG, "PM_SLEEP_CLK_ICG_ENABLE is disabled. "
+                 "Clock ungate requests may not be honored during sleep.");
+    }
+#endif
     if (clock >= ESP_SLEEP_CLOCK_MAX || option >= ESP_SLEEP_CLOCK_OPTION_MAX) {
         return ESP_ERR_INVALID_ARG;
     }

components/esp_pm/Kconfig

@@ -311,4 +311,17 @@ menu "Power Management"
             Configure the delay time between waking up PSRAM halfsleep mode and the first access to PSRAM.
             Refer to the tXHS parameter in datasheet of the used PSRAM to configure this option.
 
+    config PM_SLEEP_CLK_ICG_ENABLE
+        bool "Enable clock gating control during light sleep"
+        depends on SOC_PM_SLEEP_CLK_ICG_USE_REGDMA
+        default y
+        help
+            Enable clock gating for digital peripherals in Light Sleep mode.
+            Some digital peripherals require their functional clocks to
+            remain enabled during sleep. The Sleep Clock ICG selectively
+            ungates the clock tree for these peripherals, allowing their
+            hardware logic to continue running during Light Sleep, while
+            keeping all other peripheral clocks gated to minimize sleep
+            power consumption.
+
 endmenu # "Power Management"