feat(pwr_glitch): chip764 power glitch reset config

components/bootloader_support/src/esp32s31/bootloader_esp32s31.c

@@ -109,6 +109,7 @@ static inline void bootloader_ana_reset_config(void)
 {
     //Enable BOD reset
     brownout_ll_ana_reset_enable(true);
+    bootloader_power_glitch_reset_config(true);
 }
 
 #if SOC_RTC_WDT_SUPPORTED

components/bootloader_support/src/esp32s31/bootloader_soc.c

@@ -4,7 +4,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <stdbool.h>
+#include <assert.h>
+#include "soc/soc.h"
 #include "soc/lp_analog_peri_reg.h"
+#include "soc/pmu_reg.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
 
 void bootloader_ana_super_wdt_reset_config(bool enable)
 {
@@ -15,3 +20,20 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
     (void)enable;
 }
+
+void bootloader_power_glitch_reset_config(bool enable)
+{
+    //only detect VDDPST POWER GLITCH
+    SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_RSTB_PERIF_I2C);
+    SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C);
+    REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
+    REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PLLBB, 0);
+    REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PLL, 0);
+
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    if (enable) {
+        REG_SET_FIELD(LP_ANA_PG_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
+    } else {
+        REG_SET_FIELD(LP_ANA_PG_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
+    }
+}

components/soc/esp32s31/include/soc/regi2c_bias.h

@@ -32,4 +32,3 @@
 #define I2C_BIAS_DREG_2P2_PVT       1
 #define I2C_BIAS_DREG_2P2_PVT_MSB   7
 #define I2C_BIAS_DREG_2P2_PVT_LSB   4
-

components/soc/esp32s31/include/soc/regi2c_saradc.h

@@ -62,6 +62,38 @@
 #define ADC_SARADC_ENT_TSENS_ADDR_MSB       0x2
 #define ADC_SARADC_ENT_TSENS_ADDR_LSB       0x2
 
+#define POWER_GLITCH_XPD_VDET_PERIF         10
+#define POWER_GLITCH_XPD_VDET_PERIF_MSB     0
+#define POWER_GLITCH_XPD_VDET_PERIF_LSB     0
+
+#define POWER_GLITCH_XPD_VDET_VDDPST        10
+#define POWER_GLITCH_XPD_VDET_VDDPST_MSB    1
+#define POWER_GLITCH_XPD_VDET_VDDPST_LSB    1
+
+#define POWER_GLITCH_XPD_VDET_PLLBB         10
+#define POWER_GLITCH_XPD_VDET_PLLBB_MSB     2
+#define POWER_GLITCH_XPD_VDET_PLLBB_LSB     2
+
+#define POWER_GLITCH_XPD_VDET_PLL           10
+#define POWER_GLITCH_XPD_VDET_PLL_MSB       3
+#define POWER_GLITCH_XPD_VDET_PLL_LSB       3
+
+#define POWER_GLITCH_MODE_VDET_PERIF        10
+#define POWER_GLITCH_MODE_VDET_PERIF_MSB    4
+#define POWER_GLITCH_MODE_VDET_PERIF_LSB    4
+
+#define POWER_GLITCH_MODE_VDET_VDDPST       10
+#define POWER_GLITCH_MODE_VDET_VDDPST_MSB   5
+#define POWER_GLITCH_MODE_VDET_VDDPST_LSB   5
+
+#define POWER_GLITCH_MODE_VDET_PLLBB        10
+#define POWER_GLITCH_MODE_VDET_PLLBB_MSB    6
+#define POWER_GLITCH_MODE_VDET_PLLBB_LSB    6
+
+#define POWER_GLITCH_MODE_VDET_PLL          10
+#define POWER_GLITCH_MODE_VDET_PLL_MSB      7
+#define POWER_GLITCH_MODE_VDET_PLL_LSB      7
+
 #define POWER_GLITCH_DREF_VDET_PERIF         11
 #define POWER_GLITCH_DREF_VDET_PERIF_MSB     2
 #define POWER_GLITCH_DREF_VDET_PERIF_LSB     0

components/soc/esp32s31/register/soc/lp_analog_peri_reg.h

@@ -119,6 +119,11 @@ extern "C" {
 #define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
 #define LP_ANA_ANA_FIB_ENA_S  0
 
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA    0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M  (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S)
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V  0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S  2
+
 /** LP_ANA_INT_RAW_REG register
  *  need_des
  */