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feat(pwr_glitch): chip764 power glitch reset config

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hongshuqing
2026-07-16 17:51:17 +08:00
parent 47009c5458
commit 4ab85accea
5 changed files with 60 additions and 1 deletions
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components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
+1
View File
@@ -109,6 +109,7 @@ static inline void bootloader_ana_reset_config(void)
{
//Enable BOD reset
brownout_ll_ana_reset_enable(true);
bootloader_power_glitch_reset_config(true);
}
#if SOC_RTC_WDT_SUPPORTED
components/bootloader_support/src/esp32s31/bootloader_soc.c
+22
View File
@@ -4,7 +4,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <assert.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
@@ -15,3 +20,20 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable;
}
void bootloader_power_glitch_reset_config(bool enable)
{
//only detect VDDPST POWER GLITCH
SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_RSTB_PERIF_I2C);
SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PLLBB, 0);
REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PLL, 0);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
if (enable) {
REG_SET_FIELD(LP_ANA_PG_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
} else {
REG_SET_FIELD(LP_ANA_PG_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
}
}