mirror of
https://github.com/espressif/esp-idf.git
synced 2026-08-18 06:35:35 +03:00
Merge branch 'fix/rcp_spi_crash_issue' into 'master'
fix(openthread): fix multiple SPI communication bugs that caused the host to... Closes IDFCI-9931 See merge request espressif/esp-idf!47660
This commit is contained in:
@@ -168,6 +168,7 @@ private:
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esp_openthread_spi_host_config_t m_spi_config;
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uint8_t m_tx_buffer[kSPIFrameSize];
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uint8_t *m_rx_dma_buf; ///< DMA-aligned RX buffer; avoids cache-coherency issues with unaligned frame buffer
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int m_event_fd;
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volatile uint16_t m_pending_data_len;
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@@ -3,15 +3,6 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SPI Slave example, receiver (uses SPI Slave driver to communicate with sender)
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This example code is in the Public Domain (or CC0 licensed, at your option.)
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Unless required by applicable law or agreed to in writing, this
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software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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CONDITIONS OF ANY KIND, either express or implied.
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*/
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#include <openthread/platform/spi-slave.h>
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#include "esp_attr.h"
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@@ -42,6 +33,15 @@ typedef struct {
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uint16_t input_buf_len;
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} pending_transaction_t;
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// DMA bounce buffer for RX — always sized to max(input, output) so MISO is
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// driven for the full output even when NcpSpi passes a small input buffer.
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#define SPI_SLAVE_RX_DMA_BUF_SIZE OPENTHREAD_CONFIG_NCP_SPI_BUFFER_SIZE
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static DRAM_ATTR uint8_t *s_rx_dma_buf = NULL;
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// Guards the BUSY path: only return OT_ERROR_BUSY when a transaction is truly
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// queued in the driver, so post_trans_cb is guaranteed to fire and re-queue.
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static volatile DRAM_ATTR bool s_transaction_in_flight = false;
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static otPlatSpiSlaveTransactionProcessCallback s_process_callback = NULL;
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static otPlatSpiSlaveTransactionCompleteCallback s_complete_callback = NULL;
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@@ -59,12 +59,25 @@ static void IRAM_ATTR handle_spi_setup_done(spi_slave_transaction_t *trans)
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static void IRAM_ATTR handle_spi_transaction_done(spi_slave_transaction_t *trans)
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{
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gpio_set_level(s_spi_config->intr_pin, 1);
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s_transaction_in_flight = false;
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pending_transaction_t *pending_transaction = (pending_transaction_t *)(trans->user);
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trans->trans_len /= CHAR_BIT;
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// Cap trans_len: HW reports actual clock count which may exceed slave buffer.
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uint16_t max_buf_len = pending_transaction->output_buf_len > pending_transaction->input_buf_len
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? pending_transaction->output_buf_len : pending_transaction->input_buf_len;
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if (trans->trans_len > max_buf_len) {
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trans->trans_len = max_buf_len;
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}
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// Copy RX bounce buffer back to the actual NcpSpi input buffer.
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if (s_input_buf && s_rx_dma_buf && s_rx_dma_buf != s_input_buf) {
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memcpy(s_input_buf, s_rx_dma_buf, pending_transaction->input_buf_len);
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}
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if (s_complete_callback &&
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s_complete_callback(s_context, (void*)trans->tx_buffer, pending_transaction->output_buf_len,
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trans->rx_buffer, pending_transaction->input_buf_len, trans->trans_len)) {
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s_input_buf, pending_transaction->input_buf_len, trans->trans_len)) {
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esp_openthread_task_queue_post(s_process_callback, s_context);
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}
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}
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@@ -83,22 +96,23 @@ esp_err_t esp_openthread_host_rcp_spi_init(const esp_openthread_platform_config_
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.pin_bit_mask = (1ULL << s_spi_config->intr_pin),
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};
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ESP_GOTO_ON_ERROR(gpio_config(&io_conf), err, OT_PLAT_LOG_TAG, "fail to configure SPI gpio");
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// Deassert INT: GPIO latch resets to LOW after chip reset, which would
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// cause a spurious NEGEDGE before the slave is ready.
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gpio_set_level(s_spi_config->intr_pin, 1);
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gpio_set_pull_mode(s_spi_config->bus_config.mosi_io_num, GPIO_PULLUP_ONLY);
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gpio_set_pull_mode(s_spi_config->bus_config.sclk_io_num, GPIO_PULLUP_ONLY);
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gpio_set_pull_mode(s_spi_config->slave_config.spics_io_num, GPIO_PULLUP_ONLY);
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s_spi_transaction = heap_caps_malloc(sizeof(spi_slave_transaction_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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ESP_GOTO_ON_FALSE(s_spi_transaction != NULL, ESP_ERR_NO_MEM, err, OT_PLAT_LOG_TAG, "failed to allocate memory for SPI transaction on internal heap");
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s_pending_transaction = heap_caps_malloc(sizeof(pending_transaction_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (s_spi_transaction == NULL || s_pending_transaction == NULL) {
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ESP_LOGE(OT_PLAT_LOG_TAG, "failed to allocate memory for SPI transaction on internal heap");
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ret = ESP_ERR_NO_MEM;
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goto err;
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}
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ESP_GOTO_ON_FALSE(s_pending_transaction != NULL, ESP_ERR_NO_MEM, err, OT_PLAT_LOG_TAG, "failed to allocate memory for pending transaction on internal heap");
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s_rx_dma_buf = heap_caps_malloc(SPI_SLAVE_RX_DMA_BUF_SIZE, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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ESP_GOTO_ON_FALSE(s_rx_dma_buf != NULL, ESP_ERR_NO_MEM, err, OT_PLAT_LOG_TAG, "failed to allocate memory for RX DMA buffer on internal heap");
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s_spi_transaction->user = (void *)s_pending_transaction;
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/* Initialize SPI slave interface */
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s_spi_config->slave_config.post_setup_cb = handle_spi_setup_done;
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s_spi_config->slave_config.post_trans_cb = handle_spi_transaction_done;
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ESP_GOTO_ON_ERROR(spi_slave_initialize(s_spi_config->host_device, &s_spi_config->bus_config,
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@@ -114,6 +128,8 @@ err:
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s_spi_transaction = NULL;
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heap_caps_free(s_pending_transaction);
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s_pending_transaction = NULL;
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heap_caps_free(s_rx_dma_buf);
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s_rx_dma_buf = NULL;
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return ret;
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}
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@@ -125,9 +141,11 @@ void esp_openthread_spi_slave_deinit(void)
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heap_caps_free(s_spi_config);
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heap_caps_free(s_spi_transaction);
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heap_caps_free(s_pending_transaction);
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heap_caps_free(s_rx_dma_buf);
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s_spi_config = NULL;
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s_spi_transaction = NULL;
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s_pending_transaction = NULL;
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s_rx_dma_buf = NULL;
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return;
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}
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@@ -155,14 +173,21 @@ otError IRAM_ATTR otPlatSpiSlavePrepareTransaction(uint8_t *aOutputBuf, uint16_t
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s_input_len = aInputBufLen;
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}
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trans_length = s_output_len > s_input_len ? s_output_len : s_input_len;
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trans_length *= CHAR_BIT;
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if ((gpio_get_level(s_spi_config->slave_config.spics_io_num) == 0)) {
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// Use max(input, output) so MISO is driven for the full output frame;
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// s_rx_dma_buf absorbs extra RX bytes to avoid overflowing the NcpSpi buffer.
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uint16_t trans_data_len = (s_input_len > s_output_len) ? s_input_len : s_output_len;
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trans_length = trans_data_len * CHAR_BIT;
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// In task context, return BUSY only when a transaction is already in flight
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// AND CS is asserted — ensures post_trans_cb will fire to re-queue.
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// In ISR context (post_trans_cb) we always queue unconditionally.
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if (xPortCanYield() && s_transaction_in_flight &&
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(gpio_get_level(s_spi_config->slave_config.spics_io_num) == 0)) {
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ESP_EARLY_LOGE(SPI_SLAVE_TAG, "SPI busy");
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return OT_ERROR_BUSY;
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}
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s_spi_transaction->length = trans_length;
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s_spi_transaction->rx_buffer = s_input_buf;
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s_spi_transaction->rx_buffer = s_rx_dma_buf;
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s_spi_transaction->tx_buffer = s_output_buf;
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pending_transaction_t *pending_transaction = (pending_transaction_t *)s_spi_transaction->user;
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@@ -179,6 +204,7 @@ otError IRAM_ATTR otPlatSpiSlavePrepareTransaction(uint8_t *aOutputBuf, uint16_t
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}
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if (trans_state == ESP_OK) {
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s_transaction_in_flight = true;
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return OT_ERROR_NONE;
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} else {
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return OT_ERROR_FAILED;
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -8,6 +8,7 @@
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#include "openthread/error.h"
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#include "esp_check.h"
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#include "esp_heap_caps.h"
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#include "esp_openthread_common_macro.h"
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#include "esp_rom_sys.h"
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#include "esp_vfs.h"
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@@ -17,6 +18,7 @@
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#include "driver/gpio.h"
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#include "driver/spi_master.h"
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#include "hal/gpio_types.h"
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#include "soc/soc_caps.h"
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#include "ncp/ncp_spi.hpp"
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using ot::Spinel::SpiFrame;
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@@ -26,7 +28,8 @@ namespace esp {
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namespace openthread {
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SpiSpinelInterface::SpiSpinelInterface(void)
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: m_event_fd(-1)
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: m_rx_dma_buf(nullptr)
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, m_event_fd(-1)
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, m_receiver_frame_callback(nullptr)
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, m_receiver_frame_context(nullptr)
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, m_receive_frame_buffer(nullptr)
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@@ -73,7 +76,7 @@ esp_err_t SpiSpinelInterface::Enable(const esp_openthread_spi_host_config_t &spi
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io_conf.mode = GPIO_MODE_INPUT;
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io_conf.pull_up_en = GPIO_PULLUP_ENABLE;
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ESP_RETURN_ON_ERROR(gpio_config(&io_conf), OT_PLAT_LOG_TAG, "fail to config spi gpio");
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gpio_install_isr_service(0); // The gpio isr service may has been installed.
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gpio_install_isr_service(0);
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ESP_RETURN_ON_ERROR(gpio_isr_handler_add(spi_config.intr_pin, GpioIntrHandler, this), OT_PLAT_LOG_TAG,
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"fail to add gpio isr handler");
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m_has_pending_device_frame = false;
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@@ -82,6 +85,9 @@ esp_err_t SpiSpinelInterface::Enable(const esp_openthread_spi_host_config_t &spi
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ESP_RETURN_ON_FALSE(m_event_fd >= 0, ESP_FAIL, OT_PLAT_LOG_TAG, "fail to get event fd");
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m_rx_dma_buf = (uint8_t *)heap_caps_malloc(kSPIFrameSize, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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ESP_RETURN_ON_FALSE(m_rx_dma_buf != nullptr, ESP_ERR_NO_MEM, OT_PLAT_LOG_TAG, "fail to alloc SPI RX DMA buffer");
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ESP_LOGI(OT_PLAT_LOG_TAG, "spinel SPI interface initialization completed");
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return ESP_OK;
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@@ -105,6 +111,8 @@ esp_err_t SpiSpinelInterface::Disable(void)
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ESP_RETURN_ON_ERROR(spi_bus_free(m_spi_config.host_device), OT_PLAT_LOG_TAG, "fail to free spi bus");
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gpio_uninstall_isr_service();
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}
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heap_caps_free(m_rx_dma_buf);
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m_rx_dma_buf = nullptr;
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return ESP_OK;
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}
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@@ -115,8 +123,7 @@ otError SpiSpinelInterface::SendFrame(const uint8_t *frame, uint16_t length)
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"send frame is too long");
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memcpy(&m_tx_buffer[kSPIFrameHeaderSize], frame, length);
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uint16_t rx_data_size =
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length < kSmallPacketSize ? kSmallPacketSize : length; // We'll use tx_size to receive small packets piggybacked
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uint16_t rx_data_size = length < kSmallPacketSize ? kSmallPacketSize : length;
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if (ConductSPITransaction(false, length, rx_data_size) == ESP_OK) {
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return OT_ERROR_NONE;
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} else {
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@@ -152,9 +159,12 @@ esp_err_t SpiSpinelInterface::ConductSPITransaction(bool reset, uint16_t tx_data
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transaction.length = data_size * CHAR_BIT;
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transaction.rxlength = (rx_data_size + kSPIFrameHeaderSize) * CHAR_BIT;
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transaction.tx_buffer = m_tx_buffer;
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transaction.rx_buffer = rx_buffer;
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// Use aligned DMA buffer: MultiFrameBuffer's internal array is not
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// cache-line-aligned, causing stale D-cache reads after DMA completes.
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transaction.rx_buffer = m_rx_dma_buf;
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ESP_RETURN_ON_ERROR(spi_device_polling_transmit(m_device, &transaction), OT_PLAT_LOG_TAG, "SPI transaction failed");
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memcpy(rx_buffer, m_rx_dma_buf, data_size);
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SpiFrame rx_frame(rx_buffer);
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if (!rx_frame.IsValid() || rx_frame.GetHeaderAcceptLen() > kSPIFrameSize ||
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@@ -162,17 +172,14 @@ esp_err_t SpiSpinelInterface::ConductSPITransaction(bool reset, uint16_t tx_data
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vTaskDelay(pdMS_TO_TICKS(15));
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ESP_RETURN_ON_ERROR(spi_device_polling_transmit(m_device, &transaction), OT_PLAT_LOG_TAG,
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"fail to retry SPI invalid transaction");
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memcpy(rx_buffer, m_rx_dma_buf, data_size);
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}
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if (rx_frame.IsResetFlagSet()) {
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ESP_LOGW(OT_PLAT_LOG_TAG, "RCP Reset");
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m_receive_frame_buffer->DiscardFrame();
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return ESP_OK;
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}
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if (rx_frame.GetHeaderDataLen() == 0 && rx_frame.GetHeaderAcceptLen() == 0) {
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vTaskDelay(pdMS_TO_TICKS(15));
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ESP_RETURN_ON_ERROR(spi_device_polling_transmit(m_device, &transaction), OT_PLAT_LOG_TAG,
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"fail to retry SPI empty transaction");
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memcpy(rx_buffer, m_rx_dma_buf, data_size);
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}
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if (rx_frame.GetHeaderDataLen() > 0 && rx_frame.GetHeaderDataLen() < tx_frame.GetHeaderAcceptLen()) {
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@@ -267,7 +274,20 @@ otError SpiSpinelInterface::HardwareReset(void)
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{
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if (mRcpFailureHandler) {
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mRcpFailureHandler();
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ConductSPITransaction(true, 0, 0); // clear
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ConductSPITransaction(true, 0, 0);
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// Drain stale GPIO interrupt events accumulated before reset, otherwise
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// WaitForFrame() would fire immediately on a stale event and fail.
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uint64_t event;
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struct timeval zero_timeout = {0, 0};
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fd_set read_fds;
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FD_ZERO(&read_fds);
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FD_SET(m_event_fd, &read_fds);
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if (select(m_event_fd + 1, &read_fds, NULL, NULL, &zero_timeout) > 0 &&
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FD_ISSET(m_event_fd, &read_fds)) {
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read(m_event_fd, &event, sizeof(event));
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}
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m_pending_data_len = 0;
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}
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return OT_ERROR_NONE;
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}
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@@ -97,6 +97,7 @@ void app_main(void)
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ESP_ERROR_CHECK(mdns_hostname_set("esp-ot-br"));
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#if CONFIG_OPENTHREAD_SUPPORT_HW_RESET_RCP
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esp_openthread_register_rcp_failure_handler(rcp_failure_hardware_reset_handler);
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esp_openthread_set_coprocessor_reset_failure_callback(rcp_failure_hardware_reset_handler);
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#endif
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#if CONFIG_OPENTHREAD_CLI
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