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ci(astyle): reformat the hal component by astyle_py

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This commit is contained in:
morris
2026-06-01 13:29:38 +08:00
parent ca4952594a
commit 494b2f8de1
124 changed files with 1221 additions and 1432 deletions
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components/hal/esp32s3/include/hal/cache_ll.h
+12 -25
View File
@@ -19,7 +19,6 @@
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
@@ -55,7 +54,6 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -109,8 +107,7 @@ static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cach
{
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
bool enabled = false;
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
enabled = cache_ll_l1_is_icache_autoload_enabled();
break;
@@ -307,8 +304,7 @@ static inline void cache_ll_l1_disable_dcache(void)
__attribute__((always_inline))
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_disable_icache();
break;
@@ -356,8 +352,7 @@ static inline void cache_ll_l1_enable_dcache(bool data_autoload_en)
__attribute__((always_inline))
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_enable_icache(inst_autoload_en);
break;
@@ -399,8 +394,7 @@ static inline void cache_ll_l1_suspend_dcache(void)
__attribute__((always_inline))
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_suspend_icache();
break;
@@ -448,8 +442,7 @@ static inline void cache_ll_l1_resume_dcache(bool data_autoload_en)
__attribute__((always_inline))
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_resume_icache(inst_autoload_en);
break;
@@ -502,8 +495,7 @@ __attribute__((always_inline))
static inline bool cache_ll_is_cache_enabled(cache_type_t type)
{
bool enabled = false;
switch (type)
{
switch (type) {
case CACHE_TYPE_DATA:
enabled = cache_ll_l1_is_dcache_enabled(0);
break;
@@ -544,8 +536,7 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
__attribute__((always_inline))
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_DATA:
Cache_Invalidate_DCache_All();
break;
@@ -559,7 +550,6 @@ static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t ty
}
}
/**
* @brief Writeback cache supported addr
*
@@ -605,8 +595,7 @@ static inline void cache_ll_l1_freeze_dcache(void)
__attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_freeze_icache();
break;
@@ -648,8 +637,7 @@ static inline void cache_ll_l1_unfreeze_dcache(void)
__attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_unfreeze_icache();
break;
@@ -702,8 +690,7 @@ __attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
uint32_t size = 0;
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
size = cache_ll_l1_icache_get_line_size();
break;
@@ -757,7 +744,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
if (bus_id == 0) {
@@ -817,7 +804,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
if (bus_id == 0) {
components/hal/esp32s3/include/hal/crosscore_int_ll.h
-2
View File
@@ -11,7 +11,6 @@
extern "C" {
#endif
/**
* @brief Clear the crosscore interrupt that just occurred on the current core
*/
@@ -24,7 +23,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
}
}
/**
* @brief Trigger a crosscore interrupt on the given core
*
components/hal/esp32s3/include/hal/memprot_ll.h
+480 -469
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File diff suppressed because it is too large Load Diff
components/hal/esp32s3/include/hal/mmu_ll.h
-1
View File
@@ -14,7 +14,6 @@
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
components/hal/esp32s3/include/hal/sar_ctrl_ll.h
-2
View File
@@ -30,7 +30,6 @@ extern "C" {
#define PWDET_SAR_POWER_FORCE BIT(7)
#define PWDET_SAR_POWER_CNTL BIT(6)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
@@ -78,7 +77,6 @@ static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mod
}
}
#ifdef __cplusplus
}
#endif