From 494b2f8de1e79c7914a9892b6082ddf642282e37 Mon Sep 17 00:00:00 2001 From: morris Date: Mon, 1 Jun 2026 13:23:09 +0800 Subject: [PATCH] ci(astyle): reformat the hal component by astyle_py --- components/hal/cache_hal.c | 2 - components/hal/efuse_hal.c | 3 - components/hal/esp32/cache_hal_esp32.c | 2 - components/hal/esp32/include/hal/cache_ll.h | 9 +- .../hal/esp32/include/hal/crosscore_int_ll.h | 4 - components/hal/esp32/include/hal/mmu_ll.h | 55 +- .../hal/esp32/include/hal/sar_ctrl_ll.h | 2 - .../hal/esp32c2/include/hal/assist_debug_ll.h | 6 +- components/hal/esp32c2/include/hal/cache_ll.h | 6 +- .../esp32c2/include/hal/crosscore_int_ll.h | 4 - components/hal/esp32c2/include/hal/mmu_ll.h | 89 +- .../hal/esp32c2/include/hal/sar_ctrl_ll.h | 1 - .../hal/esp32c3/include/hal/assist_debug_ll.h | 6 +- components/hal/esp32c3/include/hal/cache_ll.h | 6 +- .../esp32c3/include/hal/crosscore_int_ll.h | 4 - .../hal/esp32c3/include/hal/memprot_ll.h | 5 +- components/hal/esp32c3/include/hal/mmu_ll.h | 1 - .../hal/esp32c3/include/hal/sar_ctrl_ll.h | 2 - .../hal/esp32c5/include/hal/assist_debug_ll.h | 6 +- components/hal/esp32c5/include/hal/cache_ll.h | 1 - .../esp32c5/include/hal/crosscore_int_ll.h | 4 - components/hal/esp32c5/include/hal/efuse_ll.h | 2 +- .../hal/esp32c5/include/hal/lp_aon_ll.h | 2 - .../hal/esp32c5/include/hal/lp_core_ll.h | 1 - components/hal/esp32c5/include/hal/mmu_ll.h | 113 ++- .../hal/esp32c5/include/hal/modem_syscon_ll.h | 3 +- components/hal/esp32c5/include/hal/rng_ll.h | 1 - .../hal/esp32c5/include/hal/sar_ctrl_ll.h | 1 - components/hal/esp32c5/modem_clock_hal.c | 15 +- .../hal/esp32c6/include/hal/assist_debug_ll.h | 6 +- components/hal/esp32c6/include/hal/cache_ll.h | 1 - .../esp32c6/include/hal/crosscore_int_ll.h | 4 - .../hal/esp32c6/include/hal/lp_aon_ll.h | 2 - .../hal/esp32c6/include/hal/lp_core_ll.h | 1 - components/hal/esp32c6/include/hal/mmu_ll.h | 121 ++- .../hal/esp32c6/include/hal/modem_syscon_ll.h | 3 +- .../hal/esp32c6/include/hal/sar_ctrl_ll.h | 1 - components/hal/esp32c6/modem_clock_hal.c | 15 +- .../esp32c61/include/hal/assist_debug_ll.h | 6 +- .../hal/esp32c61/include/hal/cache_ll.h | 1 - .../esp32c61/include/hal/crosscore_int_ll.h | 4 - .../hal/esp32c61/include/hal/efuse_ll.h | 3 +- .../hal/esp32c61/include/hal/lp_aon_ll.h | 2 - components/hal/esp32c61/include/hal/mmu_ll.h | 120 +-- .../esp32c61/include/hal/modem_syscon_ll.h | 3 +- .../hal/esp32c61/include/hal/sar_ctrl_ll.h | 1 - components/hal/esp32c61/modem_clock_hal.c | 15 +- components/hal/esp32h2/efuse_hal.c | 2 +- .../hal/esp32h2/include/hal/assist_debug_ll.h | 6 +- components/hal/esp32h2/include/hal/cache_ll.h | 1 - .../esp32h2/include/hal/crosscore_int_ll.h | 4 - .../hal/esp32h2/include/hal/efuse_hal.h | 1 - components/hal/esp32h2/include/hal/efuse_ll.h | 2 +- .../hal/esp32h2/include/hal/lp_aon_ll.h | 2 - components/hal/esp32h2/include/hal/mmu_ll.h | 126 ++- .../hal/esp32h2/include/hal/modem_syscon_ll.h | 4 +- .../hal/esp32h2/include/hal/sar_ctrl_ll.h | 1 - components/hal/esp32h2/modem_clock_hal.c | 6 +- .../esp32h21/include/hal/assist_debug_ll.h | 6 +- .../hal/esp32h21/include/hal/cache_ll.h | 1 - .../esp32h21/include/hal/crosscore_int_ll.h | 4 - .../hal/esp32h21/include/hal/efuse_hal.h | 1 - .../hal/esp32h21/include/hal/lp_aon_ll.h | 2 - components/hal/esp32h21/include/hal/mmu_ll.h | 125 ++- .../esp32h21/include/hal/modem_syscon_ll.h | 4 +- components/hal/esp32h21/modem_clock_hal.c | 6 +- components/hal/esp32h4/include/hal/aes_ll.h | 6 +- .../hal/esp32h4/include/hal/assist_debug_ll.h | 16 +- components/hal/esp32h4/include/hal/cache_ll.h | 4 +- .../hal/esp32h4/include/hal/cpu_utility_ll.h | 4 +- .../esp32h4/include/hal/crosscore_int_ll.h | 3 - .../hal/esp32h4/include/hal/lp_aon_ll.h | 2 - components/hal/esp32h4/include/hal/mmu_ll.h | 120 +-- .../hal/esp32h4/include/hal/modem_etm_ll.h | 40 +- .../hal/esp32h4/include/hal/modem_syscon_ll.h | 4 +- .../hal/esp32h4/include/hal/sar_ctrl_ll.h | 1 - components/hal/esp32h4/include/hal/sha_ll.h | 1 - components/hal/esp32h4/modem_clock_hal.c | 12 +- .../hal/esp32p4/include/hal/assist_debug_ll.h | 4 +- components/hal/esp32p4/include/hal/cache_ll.h | 1 - .../hal/esp32p4/include/hal/cpu_utility_ll.h | 4 +- .../esp32p4/include/hal/crosscore_int_ll.h | 4 - .../hal/esp32p4/include/hal/lp_clkrst_ll.h | 1 - .../hal/esp32p4/include/hal/lp_core_ll.h | 3 - .../hal/esp32p4/include/hal/lp_mailbox_ll.h | 1 - .../hal/esp32p4/include/hal/lp_sys_ll.h | 1 - components/hal/esp32p4/include/hal/mmu_ll.h | 113 ++- .../hal/esp32p4/include/hal/sar_ctrl_ll.h | 1 - components/hal/esp32s2/efuse_hal.c | 2 +- components/hal/esp32s2/include/hal/cache_ll.h | 26 +- .../esp32s2/include/hal/crosscore_int_ll.h | 3 - .../hal/esp32s2/include/hal/memprot_ll.h | 5 +- components/hal/esp32s2/include/hal/mmu_ll.h | 1 - .../hal/esp32s2/include/hal/sar_ctrl_ll.h | 2 - components/hal/esp32s2/include/hal/trace_ll.h | 2 +- components/hal/esp32s3/efuse_hal.c | 1 - components/hal/esp32s3/include/hal/cache_ll.h | 37 +- .../esp32s3/include/hal/crosscore_int_ll.h | 2 - .../hal/esp32s3/include/hal/memprot_ll.h | 949 +++++++++--------- components/hal/esp32s3/include/hal/mmu_ll.h | 1 - .../hal/esp32s3/include/hal/sar_ctrl_ll.h | 2 - .../esp32s31/include/hal/assist_debug_ll.h | 16 +- .../hal/esp32s31/include/hal/cache_ll.h | 5 +- .../hal/esp32s31/include/hal/cpu_utility_ll.h | 4 +- .../esp32s31/include/hal/crosscore_int_ll.h | 3 - .../hal/esp32s31/include/hal/lp_core_ll.h | 2 - .../hal/esp32s31/include/hal/lp_sys_ll.h | 1 - components/hal/esp32s31/include/hal/mmu_ll.h | 149 ++- .../esp32s31/include/hal/modem_syscon_ll.h | 3 +- components/hal/esp32s31/modem_clock_hal.c | 15 +- components/hal/hal_utils.c | 4 +- components/hal/include/hal/assist_debug_hal.h | 1 - components/hal/include/hal/color_types.h | 1 - .../hal/include/hal/debug_probe_types.h | 1 - components/hal/include/hal/efuse_hal.h | 2 - .../hal/include/hal/interrupt_clic_ll.h | 6 - .../hal/include/hal/interrupt_intc_ll.h | 5 - .../hal/include/hal/interrupt_plic_ll.h | 6 - components/hal/include/hal/mmu_hal.h | 1 - components/hal/mmu_hal.c | 44 +- .../hal/platform_port/include/hal/log.h | 20 +- .../test_apps/hal_utils/main/test_app_main.c | 14 +- .../hal_utils/main/test_calc_clk_div.c | 1 - tools/ci/astyle-rules.yml | 1 - 124 files changed, 1221 insertions(+), 1432 deletions(-) diff --git a/components/hal/cache_hal.c b/components/hal/cache_hal.c index 73cec715594..b5bae5dc2a8 100644 --- a/components/hal/cache_hal.c +++ b/components/hal/cache_hal.c @@ -36,7 +36,6 @@ typedef struct { #endif } cache_hal_state_t; - typedef struct { cache_hal_state_t l1; cache_hal_state_t l2; @@ -44,7 +43,6 @@ typedef struct { static cache_hal_context_t ctx; - void s_cache_hal_init_ctx(void) { ctx.l1.d_autoload_en = cache_ll_is_cache_autoload_enabled(1, CACHE_TYPE_DATA, CACHE_LL_ID_ALL); diff --git a/components/hal/efuse_hal.c b/components/hal/efuse_hal.c index 548425c3ac4..c743996e8ef 100644 --- a/components/hal/efuse_hal.c +++ b/components/hal/efuse_hal.c @@ -13,7 +13,6 @@ #define FLASH_SECTOR_SIZE (4096) - void efuse_hal_get_mac(uint8_t *mac) { *((uint32_t*)&mac[0]) = efuse_ll_get_mac0(); @@ -58,8 +57,6 @@ IRAM_ATTR bool efuse_hal_flash_encryption_enabled(void) return enabled; } - - #if SOC_RECOVERY_BOOTLOADER_SUPPORTED uint32_t efuse_hal_get_recovery_bootloader_address(void) { diff --git a/components/hal/esp32/cache_hal_esp32.c b/components/hal/esp32/cache_hal_esp32.c index a64f6d8c897..37147e1f143 100644 --- a/components/hal/esp32/cache_hal_esp32.c +++ b/components/hal/esp32/cache_hal_esp32.c @@ -29,7 +29,6 @@ void cache_hal_suspend(uint32_t cache_level, cache_type_t type) #endif } - void cache_hal_resume(uint32_t cache_level, cache_type_t type) { cache_ll_l1_enable_cache(0); @@ -40,7 +39,6 @@ void cache_hal_resume(uint32_t cache_level, cache_type_t type) #endif } - bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type) { bool result = cache_ll_l1_is_cache_enabled(0, CACHE_TYPE_ALL); diff --git a/components/hal/esp32/include/hal/cache_ll.h b/components/hal/esp32/include/hal/cache_ll.h index c283cda52bc..84f6cfa49b4 100644 --- a/components/hal/esp32/include/hal/cache_ll.h +++ b/components/hal/esp32/include/hal/cache_ll.h @@ -14,7 +14,6 @@ #include "hal/cache_types.h" #include "hal/assert.h" - #ifdef __cplusplus extern "C" { #endif @@ -51,12 +50,12 @@ __attribute__((always_inline)) static inline void cache_ll_l1_disable_cache(uint32_t cache_id) { if (cache_id == 0) { - while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1){ + while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) { ; } DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE); } else { - while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1){ + while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) { ; } DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE); @@ -175,7 +174,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id) cache_bus_mask_t mask = (cache_bus_mask_t)0; HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); if (cache_id == 0) { - uint32_t bus_mask= DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG); + uint32_t bus_mask = DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG); mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0)); mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0)); mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0)); @@ -183,7 +182,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id) mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0)); mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0)); } else { - uint32_t bus_mask= DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG); + uint32_t bus_mask = DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG); mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0)); mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0)); mask = (cache_bus_mask_t)(mask | ((!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0)); diff --git a/components/hal/esp32/include/hal/crosscore_int_ll.h b/components/hal/esp32/include/hal/crosscore_int_ll.h index 3cff9d6e37e..9cd7fa412e4 100644 --- a/components/hal/esp32/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32/include/hal/crosscore_int_ll.h @@ -10,7 +10,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -23,7 +22,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) } } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -38,8 +36,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) } } - - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32/include/hal/mmu_ll.h b/components/hal/esp32/include/hal/mmu_ll.h index 7a0deab1e7d..a4e8fe7e256 100644 --- a/components/hal/esp32/include/hal/mmu_ll.h +++ b/components/hal/esp32/include/hal/mmu_ll.h @@ -23,7 +23,6 @@ extern "C" { #define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE) #define MMU_LL_END_DROM_ENTRY_ID (64 - 1) - /** * Convert MMU virtual address to linear address * @@ -106,13 +105,13 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t if (type & MMU_VADDR_DATA) { valid |= (SOC_ADDRESS_IN_DRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM1_CACHE(vaddr_end)) || - (SOC_ADDRESS_IN_DROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DROM0_CACHE(vaddr_end)); + (SOC_ADDRESS_IN_DROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DROM0_CACHE(vaddr_end)); } if (type & MMU_VADDR_INSTRUCTION) { valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || - (SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_end)) || - (SOC_ADDRESS_IN_IROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IROM0_CACHE(vaddr_end)); + (SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_end)) || + (SOC_ADDRESS_IN_IROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IROM0_CACHE(vaddr_end)); } return valid; @@ -223,14 +222,14 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32 DPORT_INTERRUPT_DISABLE(); switch (mmu_id) { - case MMU_TABLE_CORE0: - DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], mmu_val); - break; - case MMU_TABLE_CORE1: - DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], mmu_val); - break; - default: - HAL_ASSERT(false); + case MMU_TABLE_CORE0: + DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], mmu_val); + break; + case MMU_TABLE_CORE1: + DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], mmu_val); + break; + default: + HAL_ASSERT(false); } DPORT_INTERRUPT_RESTORE(); } @@ -249,14 +248,14 @@ static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id) DPORT_INTERRUPT_DISABLE(); switch (mmu_id) { - case MMU_TABLE_CORE0: - mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]); - break; - case MMU_TABLE_CORE1: - mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id]); - break; - default: - HAL_ASSERT(false); + case MMU_TABLE_CORE0: + mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]); + break; + case MMU_TABLE_CORE1: + mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id]); + break; + default: + HAL_ASSERT(false); } DPORT_INTERRUPT_RESTORE(); return mmu_value; @@ -274,14 +273,14 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM); DPORT_INTERRUPT_DISABLE(); switch (mmu_id) { - case MMU_TABLE_CORE0: - DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID); - break; - case MMU_TABLE_CORE1: - DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID); - break; - default: - HAL_ASSERT(false); + case MMU_TABLE_CORE0: + DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID); + break; + case MMU_TABLE_CORE1: + DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID); + break; + default: + HAL_ASSERT(false); } DPORT_INTERRUPT_RESTORE(); } diff --git a/components/hal/esp32/include/hal/sar_ctrl_ll.h b/components/hal/esp32/include/hal/sar_ctrl_ll.h index 2cfacff7836..bb7b3a2afe6 100644 --- a/components/hal/esp32/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32/include/hal/sar_ctrl_ll.h @@ -24,7 +24,6 @@ extern "C" { #endif - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on @@ -51,7 +50,6 @@ static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode) } } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/assist_debug_ll.h b/components/hal/esp32c2/include/hal/assist_debug_ll.h index 9f968b73e51..6e943c8f239 100644 --- a/components/hal/esp32c2/include/hal/assist_debug_ll.h +++ b/components/hal/esp32c2/include/hal/assist_debug_ll.h @@ -56,8 +56,8 @@ extern "C" { * interrupt, instead of "ENA". */ - /* These functions are optimized and designed for internal usage. - * So, the API may differ from general ll layer pattern */ +/* These functions are optimized and designed for internal usage. + * So, the API may differ from general ll layer pattern */ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { @@ -131,7 +131,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) { - return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); + return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } #ifdef __cplusplus diff --git a/components/hal/esp32c2/include/hal/cache_ll.h b/components/hal/esp32c2/include/hal/cache_ll.h index fb56816ba21..9d776450cf4 100644 --- a/components/hal/esp32c2/include/hal/cache_ll.h +++ b/components/hal/esp32c2/include/hal/cache_ll.h @@ -19,7 +19,6 @@ extern "C" { #endif - #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 @@ -53,7 +52,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ @@ -302,7 +300,7 @@ __attribute__((always_inline)) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask) { //On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0); @@ -323,7 +321,7 @@ __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask) { //On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0); diff --git a/components/hal/esp32c2/include/hal/crosscore_int_ll.h b/components/hal/esp32c2/include/hal/crosscore_int_ll.h index 71e3a532510..7b801f0f87d 100644 --- a/components/hal/esp32c2/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32c2/include/hal/crosscore_int_ll.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/mmu_ll.h b/components/hal/esp32c2/include/hal/mmu_ll.h index 094864a9349..c38144be02a 100644 --- a/components/hal/esp32c2/include/hal/mmu_ll.h +++ b/components/hal/esp32c2/include/hal/mmu_ll.h @@ -14,7 +14,6 @@ #include "hal/assert.h" #include "hal/mmu_types.h" - #ifdef __cplusplus extern "C" { #endif @@ -147,17 +146,17 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); @@ -182,17 +181,17 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; @@ -306,17 +305,17 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + default: + HAL_ASSERT(shift_code); } return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << shift_code; @@ -363,17 +362,17 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; diff --git a/components/hal/esp32c2/include/hal/sar_ctrl_ll.h b/components/hal/esp32c2/include/hal/sar_ctrl_ll.h index 447fca6dda2..11c4576de37 100644 --- a/components/hal/esp32c2/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32c2/include/hal/sar_ctrl_ll.h @@ -73,7 +73,6 @@ static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mod } } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/assist_debug_ll.h b/components/hal/esp32c3/include/hal/assist_debug_ll.h index 7a228205ca9..b5a5043c5dd 100644 --- a/components/hal/esp32c3/include/hal/assist_debug_ll.h +++ b/components/hal/esp32c3/include/hal/assist_debug_ll.h @@ -56,8 +56,8 @@ extern "C" { * interrupt, instead of "ENA". */ - /* These functions are optimized and designed for internal usage. - * So, the API may differ from general ll layer pattern */ +/* These functions are optimized and designed for internal usage. + * So, the API may differ from general ll layer pattern */ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { @@ -131,7 +131,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) { - return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); + return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } #ifdef __cplusplus diff --git a/components/hal/esp32c3/include/hal/cache_ll.h b/components/hal/esp32c3/include/hal/cache_ll.h index 2b917f31a66..60dd0a5e6c4 100644 --- a/components/hal/esp32c3/include/hal/cache_ll.h +++ b/components/hal/esp32c3/include/hal/cache_ll.h @@ -19,7 +19,6 @@ extern "C" { #endif - #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 @@ -52,7 +51,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ @@ -320,7 +318,7 @@ __attribute__((always_inline)) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask) { //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0); @@ -341,7 +339,7 @@ __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask) { //On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0); diff --git a/components/hal/esp32c3/include/hal/crosscore_int_ll.h b/components/hal/esp32c3/include/hal/crosscore_int_ll.h index 71e3a532510..7b801f0f87d 100644 --- a/components/hal/esp32c3/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32c3/include/hal/crosscore_int_ll.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/memprot_ll.h b/components/hal/esp32c3/include/hal/memprot_ll.h index 80ca7febf03..4c95f533dcb 100644 --- a/components/hal/esp32c3/include/hal/memprot_ll.h +++ b/components/hal/esp32c3/include/hal/memprot_ll.h @@ -228,7 +228,6 @@ static inline void memprot_ll_iram0_get_pms_area_3(bool *r, bool *w, bool *x) memprot_ll_iram0_get_permissions(permissions, r, w, x); } - /////////////////////////////////// // IRAM0 - MONITOR @@ -310,7 +309,6 @@ static inline uint32_t memprot_ll_iram0_get_monitor_status_register(void) return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG); } - /* ****************************************************************************************************** * *** RTC_FAST *** */ @@ -590,7 +588,6 @@ static inline uint32_t memprot_ll_rtcfast_get_monitor_status_fault_wr(void) return REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE); } - /* ****************************************************************************************************** * *** DRAM0 *** * ******************************************************************************************************/ @@ -719,7 +716,7 @@ static inline void memprot_ll_dram0_set_pms_area_3(bool r, bool w) REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_dram0_set_permissions(r, w)); } -static inline void memprot_ll_dram0_get_permissions(uint32_t perms, bool *r, bool *w ) +static inline void memprot_ll_dram0_get_permissions(uint32_t perms, bool *r, bool *w) { *r = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R; *w = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W; diff --git a/components/hal/esp32c3/include/hal/mmu_ll.h b/components/hal/esp32c3/include/hal/mmu_ll.h index 5fe5fb363c9..acbba51c106 100644 --- a/components/hal/esp32c3/include/hal/mmu_ll.h +++ b/components/hal/esp32c3/include/hal/mmu_ll.h @@ -14,7 +14,6 @@ #include "hal/assert.h" #include "hal/mmu_types.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/hal/esp32c3/include/hal/sar_ctrl_ll.h b/components/hal/esp32c3/include/hal/sar_ctrl_ll.h index c9e9a903329..e74e1d8f8fe 100644 --- a/components/hal/esp32c3/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32c3/include/hal/sar_ctrl_ll.h @@ -30,7 +30,6 @@ extern "C" { #define PWDET_SAR_POWER_FORCE BIT(7) #define PWDET_SAR_POWER_CNTL BIT(6) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on @@ -74,7 +73,6 @@ static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mod } } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/assist_debug_ll.h b/components/hal/esp32c5/include/hal/assist_debug_ll.h index 1745e1e7409..d4eda57f483 100644 --- a/components/hal/esp32c5/include/hal/assist_debug_ll.h +++ b/components/hal/esp32c5/include/hal/assist_debug_ll.h @@ -58,8 +58,8 @@ extern "C" { * actually triggering the interrupt. */ - /* These functions are optimized and designed for internal usage. - * So, the API may differ from general ll layer pattern */ +/* These functions are optimized and designed for internal usage. + * So, the API may differ from general ll layer pattern */ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { @@ -133,7 +133,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) { - return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); + return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } #ifdef __cplusplus diff --git a/components/hal/esp32c5/include/hal/cache_ll.h b/components/hal/esp32c5/include/hal/cache_ll.h index b8505523756..49a12436905 100644 --- a/components/hal/esp32c5/include/hal/cache_ll.h +++ b/components/hal/esp32c5/include/hal/cache_ll.h @@ -43,7 +43,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ diff --git a/components/hal/esp32c5/include/hal/crosscore_int_ll.h b/components/hal/esp32c5/include/hal/crosscore_int_ll.h index c76790d756b..92e045eaf32 100644 --- a/components/hal/esp32c5/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32c5/include/hal/crosscore_int_ll.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0); } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0); } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/efuse_ll.h b/components/hal/esp32c5/include/hal/efuse_ll.h index 9cabebc4d64..4418a29e79c 100644 --- a/components/hal/esp32c5/include/hal/efuse_ll.h +++ b/components/hal/esp32c5/include/hal/efuse_ll.h @@ -126,7 +126,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_dbg(void __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_lp_dbias(void) { - return (EFUSE.rd_mac_sys4.dslp_lp_dbias_1 << 4)|EFUSE.rd_mac_sys3.dslp_lp_dbias; + return (EFUSE.rd_mac_sys4.dslp_lp_dbias_1 << 4) | EFUSE.rd_mac_sys3.dslp_lp_dbias; } __attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void) diff --git a/components/hal/esp32c5/include/hal/lp_aon_ll.h b/components/hal/esp32c5/include/hal/lp_aon_ll.h index f077dc59c82..5ee6e581c57 100644 --- a/components/hal/esp32c5/include/hal/lp_aon_ll.h +++ b/components/hal/esp32c5/include/hal/lp_aon_ll.h @@ -14,7 +14,6 @@ #include "hal/misc.h" #include "esp32c5/rom/rtc.h" - #ifdef __cplusplus extern "C" { #endif @@ -69,7 +68,6 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel); } - /** * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. * Set the flag to inform diff --git a/components/hal/esp32c5/include/hal/lp_core_ll.h b/components/hal/esp32c5/include/hal/lp_core_ll.h index baecfb1f1ee..e4d1cb59281 100644 --- a/components/hal/esp32c5/include/hal/lp_core_ll.h +++ b/components/hal/esp32c5/include/hal/lp_core_ll.h @@ -20,7 +20,6 @@ extern "C" { #endif - #define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup) #define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(1) // Enable wake-up by a certain number of LP UART RX pulses #define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt diff --git a/components/hal/esp32c5/include/hal/mmu_ll.h b/components/hal/esp32c5/include/hal/mmu_ll.h index ccbd9c3ab9d..496a0ee3a1d 100644 --- a/components/hal/esp32c5/include/hal/mmu_ll.h +++ b/components/hal/esp32c5/include/hal/mmu_ll.h @@ -21,7 +21,6 @@ #include "hal/efuse_hal.h" #endif - #ifdef __cplusplus extern "C" { #endif @@ -151,20 +150,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); } @@ -186,20 +185,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; } @@ -349,20 +348,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); @@ -409,20 +408,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; diff --git a/components/hal/esp32c5/include/hal/modem_syscon_ll.h b/components/hal/esp32c5/include/hal/modem_syscon_ll.h index 719cf03279a..31961102ea3 100644 --- a/components/hal/esp32c5/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32c5/include/hal/modem_syscon_ll.h @@ -372,11 +372,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) hw->modem_rst_conf.val = 0; } - __attribute__((always_inline)) static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) { - if(en){ + if (en) { hw->clk_conf1.val = hw->clk_conf1.val | mask; } else { hw->clk_conf1.val = hw->clk_conf1.val & ~mask; diff --git a/components/hal/esp32c5/include/hal/rng_ll.h b/components/hal/esp32c5/include/hal/rng_ll.h index 15697da9b95..0d02b155351 100644 --- a/components/hal/esp32c5/include/hal/rng_ll.h +++ b/components/hal/esp32c5/include/hal/rng_ll.h @@ -95,7 +95,6 @@ static inline void rng_ll_disable(void) _lp_clkrst_ll_enable_rng_clock(false); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/sar_ctrl_ll.h b/components/hal/esp32c5/include/hal/sar_ctrl_ll.h index e46a2f3f1e6..d46e47554dc 100644 --- a/components/hal/esp32c5/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32c5/include/hal/sar_ctrl_ll.h @@ -29,7 +29,6 @@ extern "C" { #define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) #define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on diff --git a/components/hal/esp32c5/modem_clock_hal.c b/components/hal/esp32c5/modem_clock_hal.c index 776bd50e1ea..0fb8f397ca3 100644 --- a/components/hal/esp32c5/modem_clock_hal.c +++ b/components/hal/esp32c5/modem_clock_hal.c @@ -16,8 +16,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap) { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: modem_syscon_ll_set_modem_apb_icg_bitmap(hal->syscon_dev, bitmap); break; @@ -57,8 +56,7 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); uint32_t bitmap = 0; - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: bitmap = modem_syscon_ll_get_modem_apb_icg_bitmap(hal->syscon_dev); break; @@ -149,8 +147,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(hal->lpcon_dev, true); break; @@ -189,8 +186,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); break; @@ -229,8 +225,7 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_wifi_lpclk_slow_osc(hal->lpcon_dev, true); break; diff --git a/components/hal/esp32c6/include/hal/assist_debug_ll.h b/components/hal/esp32c6/include/hal/assist_debug_ll.h index 46238f41d82..9c559815cc4 100644 --- a/components/hal/esp32c6/include/hal/assist_debug_ll.h +++ b/components/hal/esp32c6/include/hal/assist_debug_ll.h @@ -56,8 +56,8 @@ extern "C" { * interrupt, instead of "ENA". */ - /* These functions are optimized and designed for internal usage. - * So, the API may differ from general ll layer pattern */ +/* These functions are optimized and designed for internal usage. + * So, the API may differ from general ll layer pattern */ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { @@ -131,7 +131,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) { - return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); + return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } #ifdef __cplusplus diff --git a/components/hal/esp32c6/include/hal/cache_ll.h b/components/hal/esp32c6/include/hal/cache_ll.h index a13e2709d1c..c13b5f69481 100644 --- a/components/hal/esp32c6/include/hal/cache_ll.h +++ b/components/hal/esp32c6/include/hal/cache_ll.h @@ -43,7 +43,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ diff --git a/components/hal/esp32c6/include/hal/crosscore_int_ll.h b/components/hal/esp32c6/include/hal/crosscore_int_ll.h index c76790d756b..92e045eaf32 100644 --- a/components/hal/esp32c6/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32c6/include/hal/crosscore_int_ll.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0); } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0); } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/lp_aon_ll.h b/components/hal/esp32c6/include/hal/lp_aon_ll.h index d2ce8514029..b50811bc74a 100644 --- a/components/hal/esp32c6/include/hal/lp_aon_ll.h +++ b/components/hal/esp32c6/include/hal/lp_aon_ll.h @@ -14,7 +14,6 @@ #include "hal/misc.h" #include "esp32c6/rom/rtc.h" - #ifdef __cplusplus extern "C" { #endif @@ -69,7 +68,6 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel); } - /** * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. * Set the flag to inform diff --git a/components/hal/esp32c6/include/hal/lp_core_ll.h b/components/hal/esp32c6/include/hal/lp_core_ll.h index 4b61d365630..fbec6d56e3a 100644 --- a/components/hal/esp32c6/include/hal/lp_core_ll.h +++ b/components/hal/esp32c6/include/hal/lp_core_ll.h @@ -21,7 +21,6 @@ extern "C" { #endif - #define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup) #define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(1) // Enable wake-up by a certain number of LP UART RX pulses #define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt diff --git a/components/hal/esp32c6/include/hal/mmu_ll.h b/components/hal/esp32c6/include/hal/mmu_ll.h index 5f005bf83f1..0e601fce8cf 100644 --- a/components/hal/esp32c6/include/hal/mmu_ll.h +++ b/components/hal/esp32c6/include/hal/mmu_ll.h @@ -14,7 +14,6 @@ #include "hal/mmu_types.h" #include "hal/efuse_ll.h" - #ifdef __cplusplus extern "C" { #endif @@ -71,10 +70,10 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) { (void)mmu_id; uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); - return (page_size_code == 0) ? MMU_PAGE_64KB : \ - (page_size_code == 1) ? MMU_PAGE_32KB : \ - (page_size_code == 2) ? MMU_PAGE_16KB : \ - MMU_PAGE_8KB; + return (page_size_code == 0) ? MMU_PAGE_64KB : \ + (page_size_code == 1) ? MMU_PAGE_32KB : \ + (page_size_code == 2) ? MMU_PAGE_16KB : \ + MMU_PAGE_8KB; } /** @@ -146,20 +145,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); } @@ -182,20 +181,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; } @@ -319,20 +318,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); @@ -381,20 +380,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; diff --git a/components/hal/esp32c6/include/hal/modem_syscon_ll.h b/components/hal/esp32c6/include/hal/modem_syscon_ll.h index f65bf6d4ce1..4cff140ff06 100644 --- a/components/hal/esp32c6/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32c6/include/hal/modem_syscon_ll.h @@ -328,11 +328,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) hw->modem_rst_conf.val = 0; } - __attribute__((always_inline)) static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) { - if(en){ + if (en) { hw->clk_conf1.val = hw->clk_conf1.val | mask; } else { hw->clk_conf1.val = hw->clk_conf1.val & ~mask; diff --git a/components/hal/esp32c6/include/hal/sar_ctrl_ll.h b/components/hal/esp32c6/include/hal/sar_ctrl_ll.h index 2a3ec6ca632..aca215286a7 100644 --- a/components/hal/esp32c6/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32c6/include/hal/sar_ctrl_ll.h @@ -29,7 +29,6 @@ extern "C" { #define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) #define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on diff --git a/components/hal/esp32c6/modem_clock_hal.c b/components/hal/esp32c6/modem_clock_hal.c index a1b5f589cdc..df09438e46c 100644 --- a/components/hal/esp32c6/modem_clock_hal.c +++ b/components/hal/esp32c6/modem_clock_hal.c @@ -16,8 +16,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap) { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: modem_syscon_ll_set_modem_apb_icg_bitmap(hal->syscon_dev, bitmap); break; @@ -57,8 +56,7 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); uint32_t bitmap = 0; - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: bitmap = modem_syscon_ll_get_modem_apb_icg_bitmap(hal->syscon_dev); break; @@ -145,8 +143,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(hal->lpcon_dev, true); break; @@ -185,8 +182,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); break; @@ -225,8 +221,7 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_wifi_lpclk_slow_osc(hal->lpcon_dev, true); break; diff --git a/components/hal/esp32c61/include/hal/assist_debug_ll.h b/components/hal/esp32c61/include/hal/assist_debug_ll.h index 213b339a62b..505fd716175 100644 --- a/components/hal/esp32c61/include/hal/assist_debug_ll.h +++ b/components/hal/esp32c61/include/hal/assist_debug_ll.h @@ -58,8 +58,8 @@ extern "C" { * actually triggering the interrupt. */ - /* These functions are optimized and designed for internal usage. - * So, the API may differ from general ll layer pattern */ +/* These functions are optimized and designed for internal usage. + * So, the API may differ from general ll layer pattern */ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { @@ -133,7 +133,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) { - return REG_GET_BIT(BUS_MONITOR_CORE_0_DEBUG_MODE_REG, BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE); + return REG_GET_BIT(BUS_MONITOR_CORE_0_DEBUG_MODE_REG, BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE); } #ifdef __cplusplus diff --git a/components/hal/esp32c61/include/hal/cache_ll.h b/components/hal/esp32c61/include/hal/cache_ll.h index b8252b2e344..e1df3a61c58 100644 --- a/components/hal/esp32c61/include/hal/cache_ll.h +++ b/components/hal/esp32c61/include/hal/cache_ll.h @@ -42,7 +42,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ diff --git a/components/hal/esp32c61/include/hal/crosscore_int_ll.h b/components/hal/esp32c61/include/hal/crosscore_int_ll.h index c76790d756b..92e045eaf32 100644 --- a/components/hal/esp32c61/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32c61/include/hal/crosscore_int_ll.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0); } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0); } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c61/include/hal/efuse_ll.h b/components/hal/esp32c61/include/hal/efuse_ll.h index 757ada89a4e..a920e21282f 100644 --- a/components/hal/esp32c61/include/hal/efuse_ll.h +++ b/components/hal/esp32c61/include/hal/efuse_ll.h @@ -64,7 +64,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) __attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_hp_dbias(void) { - return (EFUSE0.rd_mac_sys3.active_hp_dbias_1 << 3)|EFUSE0.rd_mac_sys2.active_hp_dbias; + return (EFUSE0.rd_mac_sys3.active_hp_dbias_1 << 3) | EFUSE0.rd_mac_sys2.active_hp_dbias; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_lp_dbias(void) @@ -139,7 +139,6 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return EFUSE0.conf.cfg_ecdsa_blk; } - __attribute__((always_inline)) static inline uint32_t efuse_ll_get_recovery_bootloader_sector(void) { return EFUSE0.rd_repeat_data3.recovery_bootloader_flash_sector; diff --git a/components/hal/esp32c61/include/hal/lp_aon_ll.h b/components/hal/esp32c61/include/hal/lp_aon_ll.h index 82702c90df7..c2d281f2e89 100644 --- a/components/hal/esp32c61/include/hal/lp_aon_ll.h +++ b/components/hal/esp32c61/include/hal/lp_aon_ll.h @@ -14,7 +14,6 @@ #include "hal/misc.h" #include "esp32c61/rom/rtc.h" - #ifdef __cplusplus extern "C" { #endif @@ -69,7 +68,6 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel); } - /** * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. * Set the flag to inform diff --git a/components/hal/esp32c61/include/hal/mmu_ll.h b/components/hal/esp32c61/include/hal/mmu_ll.h index 551baa6395c..384e8e999b9 100644 --- a/components/hal/esp32c61/include/hal/mmu_ll.h +++ b/components/hal/esp32c61/include/hal/mmu_ll.h @@ -75,10 +75,10 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) { (void)mmu_id; uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE); - return (page_size_code == 0) ? MMU_PAGE_64KB : \ - (page_size_code == 1) ? MMU_PAGE_32KB : \ - (page_size_code == 2) ? MMU_PAGE_16KB : \ - MMU_PAGE_8KB; + return (page_size_code == 0) ? MMU_PAGE_64KB : \ + (page_size_code == 1) ? MMU_PAGE_32KB : \ + (page_size_code == 2) ? MMU_PAGE_16KB : \ + MMU_PAGE_8KB; } /** @@ -150,20 +150,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); } @@ -186,20 +186,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; } @@ -353,20 +353,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); @@ -415,20 +415,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; diff --git a/components/hal/esp32c61/include/hal/modem_syscon_ll.h b/components/hal/esp32c61/include/hal/modem_syscon_ll.h index ae05fa95250..75db4271141 100644 --- a/components/hal/esp32c61/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32c61/include/hal/modem_syscon_ll.h @@ -372,11 +372,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) hw->modem_rst_conf.val = 0; } - __attribute__((always_inline)) static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) { - if(en){ + if (en) { hw->clk_conf1.val = hw->clk_conf1.val | mask; } else { hw->clk_conf1.val = hw->clk_conf1.val & ~mask; diff --git a/components/hal/esp32c61/include/hal/sar_ctrl_ll.h b/components/hal/esp32c61/include/hal/sar_ctrl_ll.h index 48d511dd3c0..3226fe63e50 100644 --- a/components/hal/esp32c61/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32c61/include/hal/sar_ctrl_ll.h @@ -29,7 +29,6 @@ extern "C" { #define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) #define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on diff --git a/components/hal/esp32c61/modem_clock_hal.c b/components/hal/esp32c61/modem_clock_hal.c index ccb8ac49b3c..21b42c25d6d 100644 --- a/components/hal/esp32c61/modem_clock_hal.c +++ b/components/hal/esp32c61/modem_clock_hal.c @@ -16,8 +16,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap) { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: modem_syscon_ll_set_modem_apb_icg_bitmap(hal->syscon_dev, bitmap); break; @@ -54,8 +53,7 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); uint32_t bitmap = 0; - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: bitmap = modem_syscon_ll_get_modem_apb_icg_bitmap(hal->syscon_dev); break; @@ -143,8 +141,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(hal->lpcon_dev, true); break; @@ -183,8 +180,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); break; @@ -223,8 +219,7 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_wifi_lpclk_slow_osc(hal->lpcon_dev, true); break; diff --git a/components/hal/esp32h2/efuse_hal.c b/components/hal/esp32h2/efuse_hal.c index a6a92728d1d..eee891dce77 100644 --- a/components/hal/esp32h2/efuse_hal.c +++ b/components/hal/esp32h2/efuse_hal.c @@ -81,7 +81,7 @@ void efuse_hal_rs_calculate(const void *data, void *rs_values) uint32_t efuse_hal_get_ecdsa_curve_mode(void) { - if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)) { + if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)) { return efuse_ll_get_ecdsa_curve_mode(); } else { // Curve mode is not configurable for previous versions diff --git a/components/hal/esp32h2/include/hal/assist_debug_ll.h b/components/hal/esp32h2/include/hal/assist_debug_ll.h index 46238f41d82..9c559815cc4 100644 --- a/components/hal/esp32h2/include/hal/assist_debug_ll.h +++ b/components/hal/esp32h2/include/hal/assist_debug_ll.h @@ -56,8 +56,8 @@ extern "C" { * interrupt, instead of "ENA". */ - /* These functions are optimized and designed for internal usage. - * So, the API may differ from general ll layer pattern */ +/* These functions are optimized and designed for internal usage. + * So, the API may differ from general ll layer pattern */ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { @@ -131,7 +131,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) { - return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); + return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } #ifdef __cplusplus diff --git a/components/hal/esp32h2/include/hal/cache_ll.h b/components/hal/esp32h2/include/hal/cache_ll.h index 318aade3482..9fc488a5e4c 100644 --- a/components/hal/esp32h2/include/hal/cache_ll.h +++ b/components/hal/esp32h2/include/hal/cache_ll.h @@ -42,7 +42,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ diff --git a/components/hal/esp32h2/include/hal/crosscore_int_ll.h b/components/hal/esp32h2/include/hal/crosscore_int_ll.h index c76790d756b..92e045eaf32 100644 --- a/components/hal/esp32h2/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32h2/include/hal/crosscore_int_ll.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0); } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0); } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/efuse_hal.h b/components/hal/esp32h2/include/hal/efuse_hal.h index f7be184ebcd..7a90f925114 100644 --- a/components/hal/esp32h2/include/hal/efuse_hal.h +++ b/components/hal/esp32h2/include/hal/efuse_hal.h @@ -16,7 +16,6 @@ extern "C" { #endif - /** * @brief set eFuse timings * diff --git a/components/hal/esp32h2/include/hal/efuse_ll.h b/components/hal/esp32h2/include/hal/efuse_ll.h index 78c66b18a63..e683551c7d2 100644 --- a/components/hal/esp32h2/include/hal/efuse_ll.h +++ b/components/hal/esp32h2/include/hal/efuse_ll.h @@ -63,7 +63,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_dbias(vo __attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void) { - return (EFUSE.rd_mac_sys_3.dbias_vol_gap_sign << 4)|(EFUSE.rd_mac_sys_3.dbias_vol_gap_value2 << 1)|EFUSE.rd_mac_sys_2.dbias_vol_gap_value1; + return (EFUSE.rd_mac_sys_3.dbias_vol_gap_sign << 4) | (EFUSE.rd_mac_sys_3.dbias_vol_gap_value2 << 1) | EFUSE.rd_mac_sys_2.dbias_vol_gap_value1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) diff --git a/components/hal/esp32h2/include/hal/lp_aon_ll.h b/components/hal/esp32h2/include/hal/lp_aon_ll.h index 50230e4229f..e298427a137 100644 --- a/components/hal/esp32h2/include/hal/lp_aon_ll.h +++ b/components/hal/esp32h2/include/hal/lp_aon_ll.h @@ -14,7 +14,6 @@ #include "hal/misc.h" #include "esp32h2/rom/rtc.h" - #ifdef __cplusplus extern "C" { #endif @@ -69,7 +68,6 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel); } - /** * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. * Set the flag to inform diff --git a/components/hal/esp32h2/include/hal/mmu_ll.h b/components/hal/esp32h2/include/hal/mmu_ll.h index 19a975d33bd..704be1fac98 100644 --- a/components/hal/esp32h2/include/hal/mmu_ll.h +++ b/components/hal/esp32h2/include/hal/mmu_ll.h @@ -14,7 +14,6 @@ #include "hal/mmu_types.h" #include "hal/efuse_ll.h" - #ifdef __cplusplus extern "C" { #endif @@ -51,7 +50,6 @@ static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_t return SOC_MMU_IBUS_VADDR_BASE | laddr; } - __attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void) { unsigned cnt = efuse_ll_get_flash_crypt_cnt(); @@ -60,7 +58,6 @@ __attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enable return (cnt == 1); } - /** * Get MMU page size * @@ -72,11 +69,11 @@ __attribute__((always_inline)) static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) { (void)mmu_id; - uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); - return (page_size_code == 0) ? MMU_PAGE_64KB : \ - (page_size_code == 1) ? MMU_PAGE_32KB : \ - (page_size_code == 2) ? MMU_PAGE_16KB : \ - MMU_PAGE_8KB; + uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); + return (page_size_code == 0) ? MMU_PAGE_64KB : \ + (page_size_code == 1) ? MMU_PAGE_32KB : \ + (page_size_code == 2) ? MMU_PAGE_16KB : \ + MMU_PAGE_8KB; } /** @@ -150,20 +147,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); @@ -187,20 +184,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; @@ -325,20 +322,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); @@ -387,20 +384,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; @@ -411,7 +408,6 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0); } - #ifdef __cplusplus } diff --git a/components/hal/esp32h2/include/hal/modem_syscon_ll.h b/components/hal/esp32h2/include/hal/modem_syscon_ll.h index d40b7380bd7..7f44bc820fd 100644 --- a/components/hal/esp32h2/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32h2/include/hal/modem_syscon_ll.h @@ -31,7 +31,6 @@ static inline bool modem_syscon_ll_test_clk_is_enabled(modem_syscon_dev_t *hw) return hw->test_conf.clk_en; } - __attribute__((always_inline)) static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) { @@ -239,11 +238,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) hw->modem_rst_conf.val = 0; } - __attribute__((always_inline)) static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) { - if(en){ + if (en) { hw->clk_conf1.val = hw->clk_conf1.val | mask; } else { hw->clk_conf1.val = hw->clk_conf1.val & ~mask; diff --git a/components/hal/esp32h2/include/hal/sar_ctrl_ll.h b/components/hal/esp32h2/include/hal/sar_ctrl_ll.h index 2a3ec6ca632..aca215286a7 100644 --- a/components/hal/esp32h2/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32h2/include/hal/sar_ctrl_ll.h @@ -29,7 +29,6 @@ extern "C" { #define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) #define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on diff --git a/components/hal/esp32h2/modem_clock_hal.c b/components/hal/esp32h2/modem_clock_hal.c index ac32fb798d0..d50be09922b 100644 --- a/components/hal/esp32h2/modem_clock_hal.c +++ b/components/hal/esp32h2/modem_clock_hal.c @@ -63,8 +63,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true); break; @@ -103,8 +102,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); break; diff --git a/components/hal/esp32h21/include/hal/assist_debug_ll.h b/components/hal/esp32h21/include/hal/assist_debug_ll.h index ea0049ec8ef..c67084881b0 100644 --- a/components/hal/esp32h21/include/hal/assist_debug_ll.h +++ b/components/hal/esp32h21/include/hal/assist_debug_ll.h @@ -56,8 +56,8 @@ extern "C" { * interrupt, instead of "ENA". */ - /* These functions are optimized and designed for internal usage. - * So, the API may differ from general ll layer pattern */ +/* These functions are optimized and designed for internal usage. + * So, the API may differ from general ll layer pattern */ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { @@ -131,7 +131,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) { - return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); + return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } #ifdef __cplusplus diff --git a/components/hal/esp32h21/include/hal/cache_ll.h b/components/hal/esp32h21/include/hal/cache_ll.h index 97a47336129..bea033c2c46 100644 --- a/components/hal/esp32h21/include/hal/cache_ll.h +++ b/components/hal/esp32h21/include/hal/cache_ll.h @@ -43,7 +43,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ diff --git a/components/hal/esp32h21/include/hal/crosscore_int_ll.h b/components/hal/esp32h21/include/hal/crosscore_int_ll.h index c76790d756b..92e045eaf32 100644 --- a/components/hal/esp32h21/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32h21/include/hal/crosscore_int_ll.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0); } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0); } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h21/include/hal/efuse_hal.h b/components/hal/esp32h21/include/hal/efuse_hal.h index 9a442ac47cc..1ffef44c50c 100644 --- a/components/hal/esp32h21/include/hal/efuse_hal.h +++ b/components/hal/esp32h21/include/hal/efuse_hal.h @@ -16,7 +16,6 @@ extern "C" { #endif - /** * @brief set eFuse timings * diff --git a/components/hal/esp32h21/include/hal/lp_aon_ll.h b/components/hal/esp32h21/include/hal/lp_aon_ll.h index 55d890825a2..e42a535aeef 100644 --- a/components/hal/esp32h21/include/hal/lp_aon_ll.h +++ b/components/hal/esp32h21/include/hal/lp_aon_ll.h @@ -14,7 +14,6 @@ #include "hal/misc.h" #include "esp32h21/rom/rtc.h" - #ifdef __cplusplus extern "C" { #endif @@ -69,7 +68,6 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel); } - /** * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. * Set the flag to inform diff --git a/components/hal/esp32h21/include/hal/mmu_ll.h b/components/hal/esp32h21/include/hal/mmu_ll.h index cc4e484f925..3d660734f2a 100644 --- a/components/hal/esp32h21/include/hal/mmu_ll.h +++ b/components/hal/esp32h21/include/hal/mmu_ll.h @@ -50,7 +50,6 @@ static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_t return SOC_MMU_IBUS_VADDR_BASE | laddr; } - __attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void) { unsigned cnt = efuse_ll_get_flash_crypt_cnt(); @@ -59,7 +58,6 @@ __attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enable return (cnt == 1); } - /** * Get MMU page size * @@ -71,11 +69,11 @@ __attribute__((always_inline)) static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) { (void)mmu_id; - uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); - return (page_size_code == 0) ? MMU_PAGE_64KB : \ - (page_size_code == 1) ? MMU_PAGE_32KB : \ - (page_size_code == 2) ? MMU_PAGE_16KB : \ - MMU_PAGE_8KB; + uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE); + return (page_size_code == 0) ? MMU_PAGE_64KB : \ + (page_size_code == 1) ? MMU_PAGE_32KB : \ + (page_size_code == 2) ? MMU_PAGE_16KB : \ + MMU_PAGE_8KB; } /** @@ -149,20 +147,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); @@ -186,20 +184,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; @@ -324,20 +322,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); @@ -386,20 +384,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; @@ -410,7 +408,6 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e return mmu_ll_laddr_to_vaddr(laddr, type, MMU_TARGET_FLASH0); } - #ifdef __cplusplus } diff --git a/components/hal/esp32h21/include/hal/modem_syscon_ll.h b/components/hal/esp32h21/include/hal/modem_syscon_ll.h index 3e81d227516..88b0ae20d47 100644 --- a/components/hal/esp32h21/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32h21/include/hal/modem_syscon_ll.h @@ -31,7 +31,6 @@ static inline bool modem_syscon_ll_test_clk_is_enabled(modem_syscon_dev_t *hw) return hw->test_conf.clk_en; } - __attribute__((always_inline)) static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) { @@ -253,11 +252,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) hw->modem_rst_conf.val = 0; } - __attribute__((always_inline)) static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) { - if(en){ + if (en) { hw->clk_conf1.val = hw->clk_conf1.val | mask; } else { hw->clk_conf1.val = hw->clk_conf1.val & ~mask; diff --git a/components/hal/esp32h21/modem_clock_hal.c b/components/hal/esp32h21/modem_clock_hal.c index 1d276031852..d2a25ab235b 100644 --- a/components/hal/esp32h21/modem_clock_hal.c +++ b/components/hal/esp32h21/modem_clock_hal.c @@ -65,8 +65,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true); break; @@ -105,8 +104,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); break; diff --git a/components/hal/esp32h4/include/hal/aes_ll.h b/components/hal/esp32h4/include/hal/aes_ll.h index a065b078d33..afb9c663625 100644 --- a/components/hal/esp32h4/include/hal/aes_ll.h +++ b/components/hal/esp32h4/include/hal/aes_ll.h @@ -110,7 +110,7 @@ static inline void aes_ll_read_block(void *output) for (size_t i = 0; i < AES_BLOCK_WORDS; i++) { output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH)); /* Memcpy to avoid potential unaligned access */ - memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word)); + memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word)); } } @@ -123,7 +123,6 @@ static inline void aes_ll_start_transform(void) REG_WRITE(AES_TRIGGER_REG, 1); } - /** * @brief Read state of AES accelerator * @@ -134,7 +133,6 @@ static inline esp_aes_state_t aes_ll_get_state(void) return (esp_aes_state_t)REG_READ(AES_STATE_REG); } - /** * @brief Set mode of operation * @@ -187,7 +185,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv) uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM); uint32_t iv_word; - for (int i = 0; i < IV_WORDS; i++ ) { + for (int i = 0; i < IV_WORDS; i++) { /* Memcpy to avoid potential unaligned access */ memcpy(&iv_word, iv + 4 * i, sizeof(iv_word)); REG_WRITE(®_addr_buf[i], iv_word); diff --git a/components/hal/esp32h4/include/hal/assist_debug_ll.h b/components/hal/esp32h4/include/hal/assist_debug_ll.h index 33c3aa9adb2..8d55b9ba2a5 100644 --- a/components/hal/esp32h4/include/hal/assist_debug_ll.h +++ b/components/hal/esp32h4/include/hal/assist_debug_ll.h @@ -188,10 +188,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, in { if (core_id) { return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_cause_1.monitor_core_1_trace_lockup_recording_cause_1 - : BUS_MONITOR.monitor_core_1_trace_lockup_cause_0.monitor_core_1_trace_lockup_recording_cause_0; + : BUS_MONITOR.monitor_core_1_trace_lockup_cause_0.monitor_core_1_trace_lockup_recording_cause_0; } else { return trap_idx ? BUS_MONITOR.monitor_core_0_trace_lockup_cause_1.monitor_core_0_trace_lockup_recording_cause_1 - : BUS_MONITOR.monitor_core_0_trace_lockup_cause_0.monitor_core_0_trace_lockup_recording_cause_0; + : BUS_MONITOR.monitor_core_0_trace_lockup_cause_0.monitor_core_0_trace_lockup_recording_cause_0; } } @@ -199,10 +199,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int { if (core_id) { return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_tval_1.monitor_core_1_trace_lockup_recording_tval_1 - : BUS_MONITOR.monitor_core_1_trace_lockup_tval_0.monitor_core_1_trace_lockup_recording_tval_0; + : BUS_MONITOR.monitor_core_1_trace_lockup_tval_0.monitor_core_1_trace_lockup_recording_tval_0; } else { return trap_idx ? BUS_MONITOR.monitor_core_0_trace_lockup_tval_1.monitor_core_0_trace_lockup_recording_tval_1 - : BUS_MONITOR.monitor_core_0_trace_lockup_tval_0.monitor_core_0_trace_lockup_recording_tval_0; + : BUS_MONITOR.monitor_core_0_trace_lockup_tval_0.monitor_core_0_trace_lockup_recording_tval_0; } } @@ -210,10 +210,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, in { if (core_id) { return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_iaddr_1.monitor_core_1_trace_lockup_recording_iaddr_1 - : BUS_MONITOR.monitor_core_1_trace_lockup_iaddr_0.monitor_core_1_trace_lockup_recording_iaddr_0; + : BUS_MONITOR.monitor_core_1_trace_lockup_iaddr_0.monitor_core_1_trace_lockup_recording_iaddr_0; } else { return trap_idx ? BUS_MONITOR.monitor_core_0_trace_lockup_iaddr_1.monitor_core_0_trace_lockup_recording_iaddr_1 - : BUS_MONITOR.monitor_core_0_trace_lockup_iaddr_0.monitor_core_0_trace_lockup_recording_iaddr_0; + : BUS_MONITOR.monitor_core_0_trace_lockup_iaddr_0.monitor_core_0_trace_lockup_recording_iaddr_0; } } @@ -221,10 +221,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int { if (core_id) { return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_priv_1.monitor_core_1_trace_lockup_recording_priv_1 - : BUS_MONITOR.monitor_core_1_trace_lockup_priv_0.monitor_core_1_trace_lockup_recording_priv_0; + : BUS_MONITOR.monitor_core_1_trace_lockup_priv_0.monitor_core_1_trace_lockup_recording_priv_0; } else { return trap_idx ? BUS_MONITOR.monitor_core_0_trace_lockup_priv_1.monitor_core_0_trace_lockup_recording_priv_1 - : BUS_MONITOR.monitor_core_0_trace_lockup_priv_0.monitor_core_0_trace_lockup_recording_priv_0; + : BUS_MONITOR.monitor_core_0_trace_lockup_priv_0.monitor_core_0_trace_lockup_recording_priv_0; } } diff --git a/components/hal/esp32h4/include/hal/cache_ll.h b/components/hal/esp32h4/include/hal/cache_ll.h index 360fdc3622c..af6806edccb 100644 --- a/components/hal/esp32h4/include/hal/cache_ll.h +++ b/components/hal/esp32h4/include/hal/cache_ll.h @@ -43,7 +43,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ @@ -578,7 +577,6 @@ static inline void cache_ll_writeback_all(uint32_t cache_level, cache_type_t typ } } - /*------------------------------------------------------------------------------ * Freeze *----------------------------------------------------------------------------*/ @@ -889,7 +887,7 @@ __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask) { //On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; if (bus_id == 0) { diff --git a/components/hal/esp32h4/include/hal/cpu_utility_ll.h b/components/hal/esp32h4/include/hal/cpu_utility_ll.h index 10a2fed2e88..1b55d5107a9 100644 --- a/components/hal/esp32h4/include/hal/cpu_utility_ll.h +++ b/components/hal/esp32h4/include/hal/cpu_utility_ll.h @@ -44,10 +44,10 @@ FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no) { if (cpu_no == 0) { HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.cpucore_cfg, aon_cpu_core0_sw_stall, 0xFF); - while(REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE0_RUNSTALLED)); + while (REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE0_RUNSTALLED)); } else { HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.cpucore_cfg, aon_cpu_core1_sw_stall, 0xFF); - while(REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE1_RUNSTALLED)); + while (REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE1_RUNSTALLED)); } } diff --git a/components/hal/esp32h4/include/hal/crosscore_int_ll.h b/components/hal/esp32h4/include/hal/crosscore_int_ll.h index 779e75f0035..a1ee48cfdc6 100644 --- a/components/hal/esp32h4/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32h4/include/hal/crosscore_int_ll.h @@ -24,7 +24,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) } } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -40,7 +39,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) } } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -62,7 +60,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return reg; } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h4/include/hal/lp_aon_ll.h b/components/hal/esp32h4/include/hal/lp_aon_ll.h index 5a00458d3dc..ea08be18793 100644 --- a/components/hal/esp32h4/include/hal/lp_aon_ll.h +++ b/components/hal/esp32h4/include/hal/lp_aon_ll.h @@ -14,7 +14,6 @@ #include "hal/misc.h" #include "esp32h4/rom/rtc.h" - #ifdef __cplusplus extern "C" { #endif @@ -76,7 +75,6 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel); } - /** * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. * Set the flag to inform diff --git a/components/hal/esp32h4/include/hal/mmu_ll.h b/components/hal/esp32h4/include/hal/mmu_ll.h index e214f23a668..b86e11d322f 100644 --- a/components/hal/esp32h4/include/hal/mmu_ll.h +++ b/components/hal/esp32h4/include/hal/mmu_ll.h @@ -74,10 +74,10 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) { (void)mmu_id; uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE); - return (page_size_code == 0) ? MMU_PAGE_64KB : \ - (page_size_code == 1) ? MMU_PAGE_32KB : \ - (page_size_code == 2) ? MMU_PAGE_16KB : \ - MMU_PAGE_8KB; + return (page_size_code == 0) ? MMU_PAGE_64KB : \ + (page_size_code == 1) ? MMU_PAGE_32KB : \ + (page_size_code == 2) ? MMU_PAGE_16KB : \ + MMU_PAGE_8KB; } /** @@ -149,20 +149,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); } @@ -185,20 +185,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; } @@ -325,20 +325,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); @@ -387,20 +387,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; diff --git a/components/hal/esp32h4/include/hal/modem_etm_ll.h b/components/hal/esp32h4/include/hal/modem_etm_ll.h index 45790ebd03d..f6dee8fe2dc 100644 --- a/components/hal/esp32h4/include/hal/modem_etm_ll.h +++ b/components/hal/esp32h4/include/hal/modem_etm_ll.h @@ -37,16 +37,16 @@ extern "C" { static inline bool modem_etm_ll_get_group_event_status(int group_id) { switch (group_id) { - case 0: - return SOC_ETM.etm_evt_st6.etm_modem_evt_g0_st; - case 1: - return SOC_ETM.etm_evt_st6.etm_modem_evt_g1_st; - case 2: - return SOC_ETM.etm_evt_st6.etm_modem_evt_g2_st; - case 3: - return SOC_ETM.etm_evt_st6.etm_modem_evt_g3_st; - default: - HAL_ASSERT(false); + case 0: + return SOC_ETM.etm_evt_st6.etm_modem_evt_g0_st; + case 1: + return SOC_ETM.etm_evt_st6.etm_modem_evt_g1_st; + case 2: + return SOC_ETM.etm_evt_st6.etm_modem_evt_g2_st; + case 3: + return SOC_ETM.etm_evt_st6.etm_modem_evt_g3_st; + default: + HAL_ASSERT(false); } return false; } @@ -54,16 +54,16 @@ static inline bool modem_etm_ll_get_group_event_status(int group_id) static inline bool modem_etm_ll_get_group_task_status(int group_id) { switch (group_id) { - case 0: - return SOC_ETM.etm_task_st5.etm_modem_task_g0_st; - case 1: - return SOC_ETM.etm_task_st5.etm_modem_task_g1_st; - case 2: - return SOC_ETM.etm_task_st5.etm_modem_task_g2_st; - case 3: - return SOC_ETM.etm_task_st5.etm_modem_task_g3_st; - default: - HAL_ASSERT(false); + case 0: + return SOC_ETM.etm_task_st5.etm_modem_task_g0_st; + case 1: + return SOC_ETM.etm_task_st5.etm_modem_task_g1_st; + case 2: + return SOC_ETM.etm_task_st5.etm_modem_task_g2_st; + case 3: + return SOC_ETM.etm_task_st5.etm_modem_task_g3_st; + default: + HAL_ASSERT(false); } return false; } diff --git a/components/hal/esp32h4/include/hal/modem_syscon_ll.h b/components/hal/esp32h4/include/hal/modem_syscon_ll.h index a97fa5f2c23..1cbcaa4cbc6 100644 --- a/components/hal/esp32h4/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32h4/include/hal/modem_syscon_ll.h @@ -345,11 +345,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) hw->modem_rst_conf.val = 0; } - __attribute__((always_inline)) static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) { - if(en){ + if (en) { hw->clk_conf1.val = hw->clk_conf1.val | mask; } else { hw->clk_conf1.val = hw->clk_conf1.val & ~mask; @@ -398,7 +397,6 @@ static inline bool modem_syscon_ll_fe_32m_clock_is_enabled(modem_syscon_dev_t *h return hw->clk_conf1.clk_fe_32m_en; } - __attribute__((always_inline)) static inline void modem_syscon_ll_enable_fe_sdm_clock(modem_syscon_dev_t *hw, bool en) { diff --git a/components/hal/esp32h4/include/hal/sar_ctrl_ll.h b/components/hal/esp32h4/include/hal/sar_ctrl_ll.h index dfd5786b2da..b6955606fa8 100644 --- a/components/hal/esp32h4/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32h4/include/hal/sar_ctrl_ll.h @@ -29,7 +29,6 @@ extern "C" { #define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) #define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on diff --git a/components/hal/esp32h4/include/hal/sha_ll.h b/components/hal/esp32h4/include/hal/sha_ll.h index e2bdba36944..53fd27b8eeb 100644 --- a/components/hal/esp32h4/include/hal/sha_ll.h +++ b/components/hal/esp32h4/include/hal/sha_ll.h @@ -14,7 +14,6 @@ extern "C" { #endif - /** * @brief Enable the bus clock for SHA peripheral module * diff --git a/components/hal/esp32h4/modem_clock_hal.c b/components/hal/esp32h4/modem_clock_hal.c index f80de7ce92c..c767064fda6 100644 --- a/components/hal/esp32h4/modem_clock_hal.c +++ b/components/hal/esp32h4/modem_clock_hal.c @@ -22,8 +22,7 @@ typedef enum { void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap) { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: modem_syscon_ll_set_modem_apb_icg_bitmap(hal->syscon_dev, bitmap); break; @@ -58,8 +57,7 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); uint32_t bitmap = 0; - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: bitmap = modem_syscon_ll_get_modem_apb_icg_bitmap(hal->syscon_dev); break; @@ -140,8 +138,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true); break; @@ -180,8 +177,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); break; diff --git a/components/hal/esp32p4/include/hal/assist_debug_ll.h b/components/hal/esp32p4/include/hal/assist_debug_ll.h index bd201c6d72d..bc7cf57ea27 100644 --- a/components/hal/esp32p4/include/hal/assist_debug_ll.h +++ b/components/hal/esp32p4/include/hal/assist_debug_ll.h @@ -58,8 +58,8 @@ extern "C" { * interrupt, instead of "ENA". */ - /* These functions are optimized and designed for internal usage. - * So, the API may differ from general ll layer pattern */ +/* These functions are optimized and designed for internal usage. + * So, the API may differ from general ll layer pattern */ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) { diff --git a/components/hal/esp32p4/include/hal/cache_ll.h b/components/hal/esp32p4/include/hal/cache_ll.h index ea2ddf56735..e112bf3cc20 100644 --- a/components/hal/esp32p4/include/hal/cache_ll.h +++ b/components/hal/esp32p4/include/hal/cache_ll.h @@ -63,7 +63,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ diff --git a/components/hal/esp32p4/include/hal/cpu_utility_ll.h b/components/hal/esp32p4/include/hal/cpu_utility_ll.h index 4c7b9d490f8..2b7a0a2bc24 100644 --- a/components/hal/esp32p4/include/hal/cpu_utility_ll.h +++ b/components/hal/esp32p4/include/hal/cpu_utility_ll.h @@ -46,10 +46,10 @@ FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no) { if (cpu_no == 0) { HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore0_stall_code, 0xFF); - while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST)); + while (REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST)); } else { HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore1_stall_code, 0xFF); - while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST)); + while (REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST)); } } diff --git a/components/hal/esp32p4/include/hal/crosscore_int_ll.h b/components/hal/esp32p4/include/hal/crosscore_int_ll.h index 41ebccc75c3..a5d46d04e5f 100644 --- a/components/hal/esp32p4/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32p4/include/hal/crosscore_int_ll.h @@ -12,7 +12,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -25,7 +24,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) } } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -40,7 +38,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) } } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -62,7 +59,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return reg; } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/lp_clkrst_ll.h b/components/hal/esp32p4/include/hal/lp_clkrst_ll.h index b9dc1a4f000..1e27646bc95 100644 --- a/components/hal/esp32p4/include/hal/lp_clkrst_ll.h +++ b/components/hal/esp32p4/include/hal/lp_clkrst_ll.h @@ -17,7 +17,6 @@ extern "C" { #endif - /** * Select CPU reset vector * @param boot_from_lp_ram diff --git a/components/hal/esp32p4/include/hal/lp_core_ll.h b/components/hal/esp32p4/include/hal/lp_core_ll.h index d8f8e994519..b767575b565 100644 --- a/components/hal/esp32p4/include/hal/lp_core_ll.h +++ b/components/hal/esp32p4/include/hal/lp_core_ll.h @@ -21,7 +21,6 @@ extern "C" { #endif - #define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(9) #define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(10) #define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_0 BIT(13) @@ -68,7 +67,6 @@ static inline void lp_core_ll_reset_register(void) lp_core_ll_reset_register(__VA_ARGS__); \ } while(0) - /** * @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the lp core * @@ -136,7 +134,6 @@ static inline void lp_core_ll_set_boot_address(intptr_t boot_address) LP_SYS.lp_core_boot_addr.lp_cpu_boot_addr = boot_address; } - /** * @brief Set address LP-ROM bootloader will jump to after initialization * diff --git a/components/hal/esp32p4/include/hal/lp_mailbox_ll.h b/components/hal/esp32p4/include/hal/lp_mailbox_ll.h index e9eed3f09c9..7ef63150869 100644 --- a/components/hal/esp32p4/include/hal/lp_mailbox_ll.h +++ b/components/hal/esp32p4/include/hal/lp_mailbox_ll.h @@ -42,7 +42,6 @@ FORCE_INLINE_ATTR void lp_mailbox_ll_reset_register(lp_mb_dev_t *dev) (void) dev; } - /** * @brief Get a message (32-bit value) from the LP mailbox. * diff --git a/components/hal/esp32p4/include/hal/lp_sys_ll.h b/components/hal/esp32p4/include/hal/lp_sys_ll.h index 0f630c658fa..2f50d5e9392 100644 --- a/components/hal/esp32p4/include/hal/lp_sys_ll.h +++ b/components/hal/esp32p4/include/hal/lp_sys_ll.h @@ -16,7 +16,6 @@ #include "hal/config.h" #include "esp32p4/rom/rtc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/hal/esp32p4/include/hal/mmu_ll.h b/components/hal/esp32p4/include/hal/mmu_ll.h index aeebe6eed86..8828ac86b05 100644 --- a/components/hal/esp32p4/include/hal/mmu_ll.h +++ b/components/hal/esp32p4/include/hal/mmu_ll.h @@ -17,7 +17,6 @@ #include "hal/efuse_ll.h" #include "esp_fault.h" - #ifdef __cplusplus extern "C" { #endif @@ -202,20 +201,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); } @@ -237,20 +236,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; } @@ -470,20 +469,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } if (mmu_id == MMU_LL_FLASH_MMU_ID) { REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, entry_id); @@ -554,20 +553,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; return mmu_ll_laddr_to_vaddr(laddr, type, (mmu_id == MMU_LL_FLASH_MMU_ID) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0); diff --git a/components/hal/esp32p4/include/hal/sar_ctrl_ll.h b/components/hal/esp32p4/include/hal/sar_ctrl_ll.h index 8c0b02bc6d2..8759b640d7e 100644 --- a/components/hal/esp32p4/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32p4/include/hal/sar_ctrl_ll.h @@ -30,7 +30,6 @@ extern "C" { #define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) #define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on diff --git a/components/hal/esp32s2/efuse_hal.c b/components/hal/esp32s2/efuse_hal.c index eefeb88a5d4..8eb9ee75048 100644 --- a/components/hal/esp32s2/efuse_hal.c +++ b/components/hal/esp32s2/efuse_hal.c @@ -45,7 +45,7 @@ void efuse_hal_set_timing(uint32_t apb_freq_hz) tpgm_inact = 0x4; clk_div = 0xA0; power_on = 0xA200; - power_off = 0x100; + power_off = 0x100; tsur_a = 0x2; trd = 0x4; thr_a = 0x2; diff --git a/components/hal/esp32s2/include/hal/cache_ll.h b/components/hal/esp32s2/include/hal/cache_ll.h index 6b17ec498f9..66079b17ed8 100644 --- a/components/hal/esp32s2/include/hal/cache_ll.h +++ b/components/hal/esp32s2/include/hal/cache_ll.h @@ -19,7 +19,6 @@ extern "C" { #endif - #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2 @@ -40,7 +39,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ @@ -94,8 +92,7 @@ static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cach { HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); bool enabled = false; - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: enabled = cache_ll_l1_is_icache_autoload_enabled(); break; @@ -206,8 +203,7 @@ static inline void cache_ll_l1_disable_dcache(void) __attribute__((always_inline)) static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_disable_icache(); break; @@ -255,8 +251,7 @@ static inline void cache_ll_l1_enable_dcache(bool data_autoload_en) __attribute__((always_inline)) static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_enable_icache(inst_autoload_en); break; @@ -298,8 +293,7 @@ static inline void cache_ll_l1_suspend_dcache(void) __attribute__((always_inline)) static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_suspend_icache(); break; @@ -347,8 +341,7 @@ static inline void cache_ll_l1_resume_dcache(bool data_autoload_en) __attribute__((always_inline)) static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_resume_icache(inst_autoload_en); break; @@ -407,8 +400,7 @@ __attribute__((always_inline)) static inline bool cache_ll_is_cache_enabled(cache_type_t type) { bool enabled = false; - switch (type) - { + switch (type) { case CACHE_TYPE_DATA: enabled = cache_ll_l1_is_dcache_enabled(0); break; @@ -449,8 +441,7 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t __attribute__((always_inline)) static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { - switch (type) - { + switch (type) { case CACHE_TYPE_DATA: Cache_Invalidate_DCache_All(); break; @@ -520,8 +511,7 @@ __attribute__((always_inline)) static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { uint32_t size = 0; - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: size = cache_ll_l1_icache_get_line_size(); break; diff --git a/components/hal/esp32s2/include/hal/crosscore_int_ll.h b/components/hal/esp32s2/include/hal/crosscore_int_ll.h index bf79b5f90d4..417ab060c08 100644 --- a/components/hal/esp32s2/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32s2/include/hal/crosscore_int_ll.h @@ -11,7 +11,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -20,7 +19,6 @@ static inline void crosscore_int_ll_clear_interrupt(int core_id) DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0); } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -31,7 +29,6 @@ static inline void crosscore_int_ll_trigger_interrupt(int core_id) DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0); } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/memprot_ll.h b/components/hal/esp32s2/include/hal/memprot_ll.h index 191a49e56bb..15de377325e 100644 --- a/components/hal/esp32s2/include/hal/memprot_ll.h +++ b/components/hal/esp32s2/include/hal/memprot_ll.h @@ -82,7 +82,7 @@ static inline uint32_t memprot_ll_iram0_get_intr_clr_bit(void) //resets automatically on CPU restart static inline void memprot_ll_iram0_set_lock(void) { - DPORT_WRITE_PERI_REG( DPORT_PMS_PRO_IRAM0_0_REG, DPORT_PMS_PRO_IRAM0_LOCK); + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_0_REG, DPORT_PMS_PRO_IRAM0_LOCK); } static inline uint32_t memprot_ll_iram0_get_lock_reg(void) @@ -393,7 +393,6 @@ static inline void memprot_ll_iram0_sram_set_exec_perm(bool lx, bool hx) DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_F, hx ? 1 : 0); } - /** * ======================================================================================== * === IRAM0 RTC FAST @@ -489,7 +488,6 @@ static inline void memprot_ll_iram0_rtcfast_set_exec_perm(bool lx, bool hx) DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_F, hx ? 1 : 0); } - /** * ======================================================================================== * === DRAM0 common @@ -782,7 +780,6 @@ static inline void memprot_ll_dram0_sram_set_write_perm(bool lw, bool hw) DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_W, hw ? 1 : 0); } - /** * ======================================================================================== * === DRAM0 RTC FAST diff --git a/components/hal/esp32s2/include/hal/mmu_ll.h b/components/hal/esp32s2/include/hal/mmu_ll.h index 2b2b6182975..9e1663028cf 100644 --- a/components/hal/esp32s2/include/hal/mmu_ll.h +++ b/components/hal/esp32s2/include/hal/mmu_ll.h @@ -15,7 +15,6 @@ #include "hal/assert.h" #include "hal/mmu_types.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/hal/esp32s2/include/hal/sar_ctrl_ll.h b/components/hal/esp32s2/include/hal/sar_ctrl_ll.h index e4e239731e3..37e5514e096 100644 --- a/components/hal/esp32s2/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32s2/include/hal/sar_ctrl_ll.h @@ -30,7 +30,6 @@ extern "C" { #define PWDET_SAR_POWER_FORCE BIT(7) #define PWDET_SAR_POWER_CNTL BIT(6) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on @@ -77,7 +76,6 @@ static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mod } } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/trace_ll.h b/components/hal/esp32s2/include/hal/trace_ll.h index 5b2031e7087..46dd051af92 100644 --- a/components/hal/esp32s2/include/hal/trace_ll.h +++ b/components/hal/esp32s2/include/hal/trace_ll.h @@ -15,7 +15,7 @@ extern "C" { static inline void trace_ll_set_mem_block(int block) { - DPORT_WRITE_PERI_REG(DPORT_PMS_OCCUPY_3_REG, BIT(block-4)); + DPORT_WRITE_PERI_REG(DPORT_PMS_OCCUPY_3_REG, BIT(block - 4)); } #ifdef __cplusplus diff --git a/components/hal/esp32s3/efuse_hal.c b/components/hal/esp32s3/efuse_hal.c index 1ebbfddb6fa..02aab574655 100644 --- a/components/hal/esp32s3/efuse_hal.c +++ b/components/hal/esp32s3/efuse_hal.c @@ -14,7 +14,6 @@ #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block)))) - //The wafer_major and MSB of wafer_minor fields was allocated to other purposes when block version is v1.1. //Luckily only chip v0.0 have this kind of block version and efuse usage. //This workaround fixes the issue. diff --git a/components/hal/esp32s3/include/hal/cache_ll.h b/components/hal/esp32s3/include/hal/cache_ll.h index 1006360bd32..e5f4f4a1c3f 100644 --- a/components/hal/esp32s3/include/hal/cache_ll.h +++ b/components/hal/esp32s3/include/hal/cache_ll.h @@ -19,7 +19,6 @@ extern "C" { #endif - #define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 @@ -55,7 +54,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ @@ -109,8 +107,7 @@ static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cach { HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); bool enabled = false; - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: enabled = cache_ll_l1_is_icache_autoload_enabled(); break; @@ -307,8 +304,7 @@ static inline void cache_ll_l1_disable_dcache(void) __attribute__((always_inline)) static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_disable_icache(); break; @@ -356,8 +352,7 @@ static inline void cache_ll_l1_enable_dcache(bool data_autoload_en) __attribute__((always_inline)) static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_enable_icache(inst_autoload_en); break; @@ -399,8 +394,7 @@ static inline void cache_ll_l1_suspend_dcache(void) __attribute__((always_inline)) static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_suspend_icache(); break; @@ -448,8 +442,7 @@ static inline void cache_ll_l1_resume_dcache(bool data_autoload_en) __attribute__((always_inline)) static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_resume_icache(inst_autoload_en); break; @@ -502,8 +495,7 @@ __attribute__((always_inline)) static inline bool cache_ll_is_cache_enabled(cache_type_t type) { bool enabled = false; - switch (type) - { + switch (type) { case CACHE_TYPE_DATA: enabled = cache_ll_l1_is_dcache_enabled(0); break; @@ -544,8 +536,7 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t __attribute__((always_inline)) static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { - switch (type) - { + switch (type) { case CACHE_TYPE_DATA: Cache_Invalidate_DCache_All(); break; @@ -559,7 +550,6 @@ static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t ty } } - /** * @brief Writeback cache supported addr * @@ -605,8 +595,7 @@ static inline void cache_ll_l1_freeze_dcache(void) __attribute__((always_inline)) static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_freeze_icache(); break; @@ -648,8 +637,7 @@ static inline void cache_ll_l1_unfreeze_dcache(void) __attribute__((always_inline)) static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: cache_ll_l1_unfreeze_icache(); break; @@ -702,8 +690,7 @@ __attribute__((always_inline)) static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id) { uint32_t size = 0; - switch (type) - { + switch (type) { case CACHE_TYPE_INSTRUCTION: size = cache_ll_l1_icache_get_line_size(); break; @@ -757,7 +744,7 @@ __attribute__((always_inline)) static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask) { //On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; if (bus_id == 0) { @@ -817,7 +804,7 @@ __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask) { //On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; if (bus_id == 0) { diff --git a/components/hal/esp32s3/include/hal/crosscore_int_ll.h b/components/hal/esp32s3/include/hal/crosscore_int_ll.h index 5ce6e34e1d5..512786c665e 100644 --- a/components/hal/esp32s3/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32s3/include/hal/crosscore_int_ll.h @@ -11,7 +11,6 @@ extern "C" { #endif - /** * @brief Clear the crosscore interrupt that just occurred on the current core */ @@ -24,7 +23,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) } } - /** * @brief Trigger a crosscore interrupt on the given core * diff --git a/components/hal/esp32s3/include/hal/memprot_ll.h b/components/hal/esp32s3/include/hal/memprot_ll.h index a38ed8036c2..f08e13f68bc 100644 --- a/components/hal/esp32s3/include/hal/memprot_ll.h +++ b/components/hal/esp32s3/include/hal/memprot_ll.h @@ -63,21 +63,35 @@ static inline void *memprot_ll_get_split_addr_from_reg(const uint32_t regval, co uint32_t level_off = 0; do { - if (reg_val.cat0 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; - level_off += I_D_SRAM_SEGMENT_SIZE/2; - if (reg_val.cat1 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat0 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) { + break; + } + level_off += I_D_SRAM_SEGMENT_SIZE / 2; + if (reg_val.cat1 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) { + break; + } level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat2 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat2 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) { + break; + } level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat3 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat3 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) { + break; + } level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat4 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat4 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) { + break; + } level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat5 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat5 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) { + break; + } level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat6 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat6 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) { + break; + } return NULL; //wrong configuration - } while(0); + } while (0); return (void *)(base + level_off + off); } @@ -144,14 +158,14 @@ static inline void memprot_ll_icache_get_pms_area_1(bool *r, bool *w, bool *x) static inline memprot_hal_err_t memprot_ll_iram0_get_intr_source_num(const int core, uint32_t* src_num) { switch (core) { - case PRO_CPU_NUM: - *src_num = ETS_CORE0_IRAM0_PMS_INTR_SOURCE; - break; - case APP_CPU_NUM: - *src_num = ETS_CORE1_IRAM0_PMS_INTR_SOURCE; - break; - default: - return MEMP_HAL_FAIL; + case PRO_CPU_NUM: + *src_num = ETS_CORE0_IRAM0_PMS_INTR_SOURCE; + break; + case APP_CPU_NUM: + *src_num = ETS_CORE1_IRAM0_PMS_INTR_SOURCE; + break; + default: + return MEMP_HAL_FAIL; } return MEMP_HAL_OK; @@ -183,8 +197,9 @@ static inline void memprot_ll_prepare_iram0_split_line_regval(const uint32_t add MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA, MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA, MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA, - MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA }; - for (size_t x=0; x<7; x++) { + MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA + }; + for (size_t x = 0; x < 7; x++) { if (addr <= SRAM_RG3_LEVEL_HLIMITS(x)) { cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA; break; @@ -198,15 +213,15 @@ static inline void memprot_ll_prepare_iram0_split_line_regval(const uint32_t add //write values to required configuration-register constrain_reg_fields_t cfg_reg_val = { - .cat0 = cat[0], - .cat1 = cat[1], - .cat2 = cat[2], - .cat3 = cat[3], - .cat4 = cat[4], - .cat5 = cat[5], - .cat6 = cat[6], - .splitaddr = conf_add, - .reserved = 0 + .cat0 = cat[0], + .cat1 = cat[1], + .cat2 = cat[2], + .cat3 = cat[3], + .cat4 = cat[4], + .cat5 = cat[5], + .cat6 = cat[6], + .splitaddr = conf_add, + .reserved = 0 }; *regval = cfg_reg_val.val; @@ -382,7 +397,6 @@ static inline void memprot_ll_iram0_get_pms_area_3(bool *r, bool *w, bool *x) memprot_ll_iram0_get_permissions(permissions, r, w, x); } - /////////////////////////////////// // IRAM0 - MONITOR @@ -390,20 +404,20 @@ static inline void memprot_ll_iram0_get_pms_area_3(bool *r, bool *w, bool *x) static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_lock(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_WRITE(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG, 1); + case PRO_CPU_NUM: + REG_WRITE(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG, 1); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); + HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_WRITE(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG, 1); + break; + case APP_CPU_NUM: + REG_WRITE(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG, 1); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); + HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -412,14 +426,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_lock(const int core static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_lock(const int core, bool* locked) { switch (core) { - case PRO_CPU_NUM: - *locked = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1; - break; - case APP_CPU_NUM: - *locked = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG) == 1; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *locked = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1; + break; + case APP_CPU_NUM: + *locked = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG) == 1; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -429,34 +443,34 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_lock(const int core static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_en(const int core, const bool enable) { switch (core) { - case PRO_CPU_NUM: - if (enable) { - REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN); + case PRO_CPU_NUM: + if (enable) { + REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); #endif - } else { - REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN); + } else { + REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); #endif - } - break; - case APP_CPU_NUM: - if (enable) { - REG_SET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN); + } + break; + case APP_CPU_NUM: + if (enable) { + REG_SET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); #endif - } else { - REG_CLR_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN); + } else { + REG_CLR_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); #endif - } - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + } + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -465,14 +479,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_en(const int core, static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_en(const int core, bool* enabled) { switch (core) { - case PRO_CPU_NUM: - *enabled = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) == 1; - break; - case APP_CPU_NUM: - *enabled = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) == 1; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *enabled = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) == 1; + break; + case APP_CPU_NUM: + *enabled = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) == 1; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -481,20 +495,20 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_en(const int core, static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_intrclr(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR); + case PRO_CPU_NUM: + REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_SET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR); + break; + case APP_CPU_NUM: + REG_SET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -503,20 +517,20 @@ static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_intrclr(const int c static inline memprot_hal_err_t memprot_ll_iram0_reset_monitor_intrclr(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR); + case PRO_CPU_NUM: + REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_CLR_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR); + break; + case APP_CPU_NUM: + REG_CLR_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -525,14 +539,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_reset_monitor_intrclr(const int static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_intrclr(const int core, bool* cleared) { switch (core) { - case PRO_CPU_NUM: - *cleared = REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; - break; - case APP_CPU_NUM: - *cleared = REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *cleared = REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; + break; + case APP_CPU_NUM: + *cleared = REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -541,14 +555,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_intrclr(const int c static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_enable_register(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG); - break; - case APP_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG); + break; + case APP_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -558,14 +572,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_enable_register(con static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_intr(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -574,14 +588,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_intr(const i static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_wr(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -590,14 +604,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_wr(con static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_loadstore(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -606,14 +620,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_loadst static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_world(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -624,14 +638,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_addr(c uint32_t reg_off; switch (core) { - case PRO_CPU_NUM: - reg_off = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); - break; - case APP_CPU_NUM: - reg_off = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + reg_off = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); + break; + case APP_CPU_NUM: + reg_off = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } *addr = (void*)(reg_off > 0 ? (reg_off << I_FAULT_ADDR_SHIFT) + IRAM0_VIOLATE_STATUS_ADDR_OFFSET : 0); @@ -642,20 +656,19 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_addr(c static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_register(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG); - break; - case APP_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG); + break; + case APP_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; } - /* ****************************************************************************************************** * *** RTC_FAST *** */ @@ -663,14 +676,14 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_register(con static inline memprot_hal_err_t memprot_ll_rtcfast_get_intr_source_num(const int core, uint32_t* src_num) { switch (core) { - case PRO_CPU_NUM: - *src_num = ETS_CORE0_PIF_PMS_INTR_SOURCE; - break; - case APP_CPU_NUM: - *src_num = ETS_CORE1_PIF_PMS_INTR_SOURCE; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *src_num = ETS_CORE0_PIF_PMS_INTR_SOURCE; + break; + case APP_CPU_NUM: + *src_num = ETS_CORE1_PIF_PMS_INTR_SOURCE; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -681,20 +694,20 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_intr_source_num(const int static inline memprot_hal_err_t memprot_ll_set_pif_constraint_lock(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_WRITE(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG, 1); + case PRO_CPU_NUM: + REG_WRITE(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG, 1); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to required register"); + HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_WRITE(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG, 1); + break; + case APP_CPU_NUM: + REG_WRITE(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG, 1); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to required register"); + HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -703,14 +716,14 @@ static inline memprot_hal_err_t memprot_ll_set_pif_constraint_lock(const int cor static inline memprot_hal_err_t memprot_ll_get_pif_constraint_lock(const int core, bool* locked) { switch (core) { - case PRO_CPU_NUM: - *locked = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG) == 1; - break; - case APP_CPU_NUM: - *locked = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG) == 1; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *locked = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG) == 1; + break; + case APP_CPU_NUM: + *locked = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG) == 1; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -719,14 +732,14 @@ static inline memprot_hal_err_t memprot_ll_get_pif_constraint_lock(const int cor static inline memprot_hal_err_t memprot_ll_rtcfast_get_splitaddr_register(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG); - break; - case APP_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG); + break; + case APP_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -956,14 +969,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_pms_area(const int core, static inline memprot_hal_err_t memprot_ll_rtcfast_get_permission_register(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG); - break; - case APP_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG); + break; + case APP_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -976,20 +989,20 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_permission_register(const static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_lock(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_WRITE(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG, 1); + case PRO_CPU_NUM: + REG_WRITE(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG, 1); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); + HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_WRITE(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG, 1); + break; + case APP_CPU_NUM: + REG_WRITE(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG, 1); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); + HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -998,14 +1011,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_lock(const int co static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_lock(const int core, bool* locked) { switch (core) { - case PRO_CPU_NUM: - *locked = REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG) == 1; - break; - case APP_CPU_NUM: - *locked = REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG) == 1; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *locked = REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG) == 1; + break; + case APP_CPU_NUM: + *locked = REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG) == 1; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1015,34 +1028,34 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_lock(const int co static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_en(const int core, const bool enable) { switch (core) { - case PRO_CPU_NUM: - if (enable) { - REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN); + case PRO_CPU_NUM: + if (enable) { + REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); #endif - } else { - REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN); + } else { + REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); #endif - } - break; - case APP_CPU_NUM: - if (enable) { - REG_SET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN); + } + break; + case APP_CPU_NUM: + if (enable) { + REG_SET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); #endif - } else { - REG_CLR_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN); + } else { + REG_CLR_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); #endif - } - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + } + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1051,14 +1064,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_en(const int core static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_en(const int core, bool* enabled) { switch (core) { - case PRO_CPU_NUM: - *enabled = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) > 0; - break; - case APP_CPU_NUM: - *enabled = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) > 0; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *enabled = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) > 0; + break; + case APP_CPU_NUM: + *enabled = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) > 0; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1067,14 +1080,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_en(const int core static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_intrclr(const int core, bool* cleared) { switch (core) { - case PRO_CPU_NUM: - *cleared = REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) > 0; - break; - case APP_CPU_NUM: - *cleared = REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) > 0; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *cleared = REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) > 0; + break; + case APP_CPU_NUM: + *cleared = REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) > 0; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1083,20 +1096,20 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_intrclr(const int static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_intrclr(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR); + case PRO_CPU_NUM: + REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_SET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR); + break; + case APP_CPU_NUM: + REG_SET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1105,20 +1118,20 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_intrclr(const int static inline memprot_hal_err_t memprot_ll_rtcfast_reset_monitor_intrclr(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR); + case PRO_CPU_NUM: + REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_CLR_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR); + break; + case APP_CPU_NUM: + REG_CLR_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1127,14 +1140,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_reset_monitor_intrclr(const i static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_register(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG); - break; - case APP_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG); + break; + case APP_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1144,14 +1157,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_register(const in static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_intr(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1160,14 +1173,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_intr(const static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_addr(const int core, void** addr) { switch (core) { - case PRO_CPU_NUM: - *addr = (void*)REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG); - break; - case APP_CPU_NUM: - *addr = (void*)REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *addr = (void*)REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG); + break; + case APP_CPU_NUM: + *addr = (void*)REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1176,14 +1189,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_addr static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_world(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1192,14 +1205,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_worl static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_loadstore(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1208,20 +1221,19 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_load static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_wr(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; } - /* ****************************************************************************************************** * *** DRAM0 *** * ******************************************************************************************************/ @@ -1229,14 +1241,14 @@ static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_wr(c static inline memprot_hal_err_t memprot_ll_dram0_get_intr_source_num(const int core, uint32_t* src_num) { switch (core) { - case PRO_CPU_NUM: - *src_num = ETS_CORE0_DRAM0_PMS_INTR_SOURCE; - break; - case APP_CPU_NUM: - *src_num = ETS_CORE1_DRAM0_PMS_INTR_SOURCE; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *src_num = ETS_CORE0_DRAM0_PMS_INTR_SOURCE; + break; + case APP_CPU_NUM: + *src_num = ETS_CORE1_DRAM0_PMS_INTR_SOURCE; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1263,9 +1275,10 @@ static inline void memprot_ll_prepare_dram0_split_line_regval(const uint32_t add MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA, MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA, MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA, - MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA }; + MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA + }; - for (size_t x=0; x<7; x++) { + for (size_t x = 0; x < 7; x++) { if (addr <= MAP_IRAM_TO_DRAM(SRAM_RG3_LEVEL_HLIMITS(x))) { cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA; break; @@ -1279,18 +1292,17 @@ static inline void memprot_ll_prepare_dram0_split_line_regval(const uint32_t add //write values to required configuration-register constrain_reg_fields_t cfg_reg_val = { - .cat0 = cat[0], - .cat1 = cat[1], - .cat2 = cat[2], - .cat3 = cat[3], - .cat4 = cat[4], - .cat5 = cat[5], - .cat6 = cat[6], - .splitaddr = conf_add, - .reserved = 0 + .cat0 = cat[0], + .cat1 = cat[1], + .cat2 = cat[2], + .cat3 = cat[3], + .cat4 = cat[4], + .cat5 = cat[5], + .cat6 = cat[6], + .splitaddr = conf_add, + .reserved = 0 }; - *regval = cfg_reg_val.val; } @@ -1410,7 +1422,7 @@ static inline void memprot_ll_dram0_set_pms_area_3(const bool r, const bool w) #endif } -static inline void memprot_ll_dram0_get_permissions(const uint32_t perms, bool *r, bool *w ) +static inline void memprot_ll_dram0_get_permissions(const uint32_t perms, bool *r, bool *w) { *r = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R; *w = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W; @@ -1440,7 +1452,6 @@ static inline void memprot_ll_dram0_get_pms_area_3(bool *r, bool *w) memprot_ll_dram0_get_permissions(permissions, r, w); } - /////////////////////////////////// // DRAM0 - MONITOR @@ -1448,20 +1459,20 @@ static inline void memprot_ll_dram0_get_pms_area_3(bool *r, bool *w) static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_lock(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_WRITE(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG, 1); + case PRO_CPU_NUM: + REG_WRITE(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG, 1); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); + HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_WRITE(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG, 1); + break; + case APP_CPU_NUM: + REG_WRITE(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG, 1); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); + HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1470,14 +1481,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_lock(const int core static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_lock(const int core, bool* locked) { switch (core) { - case PRO_CPU_NUM: - *locked = REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1; - break; - case APP_CPU_NUM: - *locked = REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG) == 1; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *locked = REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1; + break; + case APP_CPU_NUM: + *locked = REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG) == 1; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1487,34 +1498,34 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_lock(const int core static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_en(const int core, const bool enable) { switch (core) { - case PRO_CPU_NUM: - if (enable) { - REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN); + case PRO_CPU_NUM: + if (enable) { + REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); #endif - } else { - REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN); + } else { + REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); #endif - } - break; - case APP_CPU_NUM: - if (enable) { - REG_SET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN); + } + break; + case APP_CPU_NUM: + if (enable) { + REG_SET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register"); #endif - } else { - REG_CLR_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN); + } else { + REG_CLR_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register"); #endif - } - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + } + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1523,14 +1534,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_en(const int core, static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_en(const int core, bool* enabled) { switch (core) { - case PRO_CPU_NUM: - *enabled = REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0; - break; - case APP_CPU_NUM: - *enabled = REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *enabled = REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0; + break; + case APP_CPU_NUM: + *enabled = REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1539,20 +1550,20 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_en(const int core, static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_intrclr(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR); + case PRO_CPU_NUM: + REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_SET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR); + break; + case APP_CPU_NUM: + REG_SET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1561,20 +1572,20 @@ static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_intrclr(const int c static inline memprot_hal_err_t memprot_ll_dram0_reset_monitor_intrclr(const int core) { switch (core) { - case PRO_CPU_NUM: - REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR); + case PRO_CPU_NUM: + REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); #endif - break; - case APP_CPU_NUM: - REG_CLR_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR); + break; + case APP_CPU_NUM: + REG_CLR_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR); #ifdef PMS_DEBUG_ASSERTIONS - HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); + HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register"); #endif - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1583,14 +1594,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_reset_monitor_intrclr(const int static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_intrclr(const int core, bool* cleared) { switch (core) { - case PRO_CPU_NUM: - *cleared = REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; - break; - case APP_CPU_NUM: - *cleared = REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *cleared = REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; + break; + case APP_CPU_NUM: + *cleared = REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1599,14 +1610,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_intrclr(const int c static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_enable_register(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG); - break; - case APP_CPU_NUM: - *regval = REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG); + break; + case APP_CPU_NUM: + *regval = REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1616,14 +1627,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_enable_register(con static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_intr(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1632,14 +1643,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_intr(const i static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_world(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1650,14 +1661,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_addr(c uint32_t reg_off; switch (core) { - case PRO_CPU_NUM: - reg_off = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); - break; - case APP_CPU_NUM: - reg_off = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + reg_off = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); + break; + case APP_CPU_NUM: + reg_off = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } *addr = (void*)(reg_off > 0 ? (reg_off << D_FAULT_ADDR_SHIFT) + DRAM0_VIOLATE_STATUS_ADDR_OFFSET : 0); @@ -1668,14 +1679,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_addr(c static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_wr(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; @@ -1684,14 +1695,14 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_wr(con static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_byte_en(const int core, uint32_t* regval) { switch (core) { - case PRO_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN); - break; - case APP_CPU_NUM: - *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN); - break; - default: - return MEMP_HAL_ERR_CORE_INVALID; + case PRO_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN); + break; + case APP_CPU_NUM: + *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN); + break; + default: + return MEMP_HAL_ERR_CORE_INVALID; } return MEMP_HAL_OK; diff --git a/components/hal/esp32s3/include/hal/mmu_ll.h b/components/hal/esp32s3/include/hal/mmu_ll.h index 8877c31402a..50bdc557557 100644 --- a/components/hal/esp32s3/include/hal/mmu_ll.h +++ b/components/hal/esp32s3/include/hal/mmu_ll.h @@ -14,7 +14,6 @@ #include "hal/assert.h" #include "hal/mmu_types.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/hal/esp32s3/include/hal/sar_ctrl_ll.h b/components/hal/esp32s3/include/hal/sar_ctrl_ll.h index 66a9954fa96..8a04a7aced0 100644 --- a/components/hal/esp32s3/include/hal/sar_ctrl_ll.h +++ b/components/hal/esp32s3/include/hal/sar_ctrl_ll.h @@ -30,7 +30,6 @@ extern "C" { #define PWDET_SAR_POWER_FORCE BIT(7) #define PWDET_SAR_POWER_CNTL BIT(6) - typedef enum { SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM SAR_CTRL_LL_POWER_ON, //SAR power on @@ -78,7 +77,6 @@ static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mod } } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s31/include/hal/assist_debug_ll.h b/components/hal/esp32s31/include/hal/assist_debug_ll.h index 9ce6201762b..23c7e91e77c 100644 --- a/components/hal/esp32s31/include/hal/assist_debug_ll.h +++ b/components/hal/esp32s31/include/hal/assist_debug_ll.h @@ -188,10 +188,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, in { if (core_id) { return trap_idx ? BUS_MONITOR.core_1_trace_lockup_cause_1.core_1_trace_lockup_recording_cause_1 - : BUS_MONITOR.core_1_trace_lockup_cause_0.core_1_trace_lockup_recording_cause_0; + : BUS_MONITOR.core_1_trace_lockup_cause_0.core_1_trace_lockup_recording_cause_0; } else { return trap_idx ? BUS_MONITOR.core_0_trace_lockup_cause_1.core_0_trace_lockup_recording_cause_1 - : BUS_MONITOR.core_0_trace_lockup_cause_0.core_0_trace_lockup_recording_cause_0; + : BUS_MONITOR.core_0_trace_lockup_cause_0.core_0_trace_lockup_recording_cause_0; } } @@ -199,10 +199,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int { if (core_id) { return trap_idx ? BUS_MONITOR.core_1_trace_lockup_tval_1.core_1_trace_lockup_recording_tval_1 - : BUS_MONITOR.core_1_trace_lockup_tval_0.core_1_trace_lockup_recording_tval_0; + : BUS_MONITOR.core_1_trace_lockup_tval_0.core_1_trace_lockup_recording_tval_0; } else { return trap_idx ? BUS_MONITOR.core_0_trace_lockup_tval_1.core_0_trace_lockup_recording_tval_1 - : BUS_MONITOR.core_0_trace_lockup_tval_0.core_0_trace_lockup_recording_tval_0; + : BUS_MONITOR.core_0_trace_lockup_tval_0.core_0_trace_lockup_recording_tval_0; } } @@ -210,10 +210,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, in { if (core_id) { return trap_idx ? BUS_MONITOR.core_1_trace_lockup_iaddr_1.core_1_trace_lockup_recording_iaddr_1 - : BUS_MONITOR.core_1_trace_lockup_iaddr_0.core_1_trace_lockup_recording_iaddr_0; + : BUS_MONITOR.core_1_trace_lockup_iaddr_0.core_1_trace_lockup_recording_iaddr_0; } else { return trap_idx ? BUS_MONITOR.core_0_trace_lockup_iaddr_1.core_0_trace_lockup_recording_iaddr_1 - : BUS_MONITOR.core_0_trace_lockup_iaddr_0.core_0_trace_lockup_recording_iaddr_0; + : BUS_MONITOR.core_0_trace_lockup_iaddr_0.core_0_trace_lockup_recording_iaddr_0; } } @@ -221,10 +221,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int { if (core_id) { return trap_idx ? BUS_MONITOR.core_1_trace_lockup_priv_1.core_1_trace_lockup_recording_priv_1 - : BUS_MONITOR.core_1_trace_lockup_priv_0.core_1_trace_lockup_recording_priv_0; + : BUS_MONITOR.core_1_trace_lockup_priv_0.core_1_trace_lockup_recording_priv_0; } else { return trap_idx ? BUS_MONITOR.core_0_trace_lockup_priv_1.core_0_trace_lockup_recording_priv_1 - : BUS_MONITOR.core_0_trace_lockup_priv_0.core_0_trace_lockup_recording_priv_0; + : BUS_MONITOR.core_0_trace_lockup_priv_0.core_0_trace_lockup_recording_priv_0; } } diff --git a/components/hal/esp32s31/include/hal/cache_ll.h b/components/hal/esp32s31/include/hal/cache_ll.h index ea4100ea1c0..12a564af874 100644 --- a/components/hal/esp32s31/include/hal/cache_ll.h +++ b/components/hal/esp32s31/include/hal/cache_ll.h @@ -50,7 +50,6 @@ typedef enum { CACHE_LL_PRELOAD_ARBITRARY = 2, } cache_ll_preload_strategy_t; - /** * @brief Initialize the cache clock */ @@ -999,7 +998,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id) __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask) { - HAL_ASSERT((mask & (CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); + HAL_ASSERT((mask & (CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; if (bus_id == 0) { @@ -1031,7 +1030,7 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32 uint32_t vaddr_end = vaddr_start + len - 1; if (((vaddr_start >= SOC_DRAM_FLASH_ADDRESS_LOW) && (vaddr_end < SOC_DRAM_FLASH_ADDRESS_HIGH)) || - ((vaddr_start >= SOC_DRAM_PSRAM_ADDRESS_LOW) && (vaddr_end < SOC_DRAM_PSRAM_ADDRESS_HIGH))) { + ((vaddr_start >= SOC_DRAM_PSRAM_ADDRESS_LOW) && (vaddr_end < SOC_DRAM_PSRAM_ADDRESS_HIGH))) { *out_level = 1; *out_id = CACHE_LL_ID_ALL; valid = true; diff --git a/components/hal/esp32s31/include/hal/cpu_utility_ll.h b/components/hal/esp32s31/include/hal/cpu_utility_ll.h index d4eb5cd4045..0b3b606afdb 100644 --- a/components/hal/esp32s31/include/hal/cpu_utility_ll.h +++ b/components/hal/esp32s31/include/hal/cpu_utility_ll.h @@ -41,10 +41,10 @@ FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no) { if (cpu_no == 0) { HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore0_sw_stall_code, 0xFF); - while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST)); + while (REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST)); } else { HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore1_sw_stall_code, 0xFF); - while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST)); + while (REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST)); } } diff --git a/components/hal/esp32s31/include/hal/crosscore_int_ll.h b/components/hal/esp32s31/include/hal/crosscore_int_ll.h index 967f217bbf1..efd6215f4be 100644 --- a/components/hal/esp32s31/include/hal/crosscore_int_ll.h +++ b/components/hal/esp32s31/include/hal/crosscore_int_ll.h @@ -24,7 +24,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) } } - /** * @brief Trigger a crosscore interrupt on the given core * @@ -39,7 +38,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) } } - /** * @brief Get the state of the crosscore interrupt register for the given core * @@ -61,7 +59,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) return reg; } - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s31/include/hal/lp_core_ll.h b/components/hal/esp32s31/include/hal/lp_core_ll.h index e60e09c87c2..351e28a2900 100644 --- a/components/hal/esp32s31/include/hal/lp_core_ll.h +++ b/components/hal/esp32s31/include/hal/lp_core_ll.h @@ -21,7 +21,6 @@ extern "C" { #endif - #define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(1) // SW_WAKEUP_HP #define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(9) // LP_GPIO_WAKEUP #define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(10) // LP_UART_WAKEUP @@ -29,7 +28,6 @@ extern "C" { #define LP_CORE_LL_WAKEUP_SOURCE_ETM BIT(17) // REG_ETM_LPCORE_WAKEUP #define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_1 BIT(18) - /* Use lp timer 1 as the normal wakeup timer, timer 0 is used by deep sleep */ #define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_1 diff --git a/components/hal/esp32s31/include/hal/lp_sys_ll.h b/components/hal/esp32s31/include/hal/lp_sys_ll.h index 3b78f818eb8..8b87fac2d75 100644 --- a/components/hal/esp32s31/include/hal/lp_sys_ll.h +++ b/components/hal/esp32s31/include/hal/lp_sys_ll.h @@ -15,7 +15,6 @@ #include "hal/misc.h" #include "esp32s31/rom/rtc.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/hal/esp32s31/include/hal/mmu_ll.h b/components/hal/esp32s31/include/hal/mmu_ll.h index 75b9bd55365..2d2da4ed516 100644 --- a/components/hal/esp32s31/include/hal/mmu_ll.h +++ b/components/hal/esp32s31/include/hal/mmu_ll.h @@ -15,7 +15,6 @@ #include "hal/mmu_types.h" #include "hal/efuse_ll.h" - #ifdef __cplusplus extern "C" { #endif @@ -158,15 +157,15 @@ static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size) uint8_t reg_val = 0; if (mmu_id == MMU_LL_FLASH_MMU_ID) { reg_val = (size == MMU_PAGE_256KB) ? 0 : \ - (size == MMU_PAGE_128KB) ? 1 : \ - (size == MMU_PAGE_64KB) ? 2 : \ - (size == MMU_PAGE_32KB) ? 3 : 0; + (size == MMU_PAGE_128KB) ? 1 : \ + (size == MMU_PAGE_64KB) ? 2 : \ + (size == MMU_PAGE_32KB) ? 3 : 0; REG_SET_FIELD(SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MMU_PAGE_SIZE, reg_val); } else if (mmu_id == MMU_LL_PSRAM_MMU_ID) { reg_val = (size == MMU_PAGE_64KB) ? 0 : \ - (size == MMU_PAGE_32KB) ? 1 : \ - (size == MMU_PAGE_16KB) ? 2 : \ - (size == MMU_PAGE_8KB) ? 3 : 0; + (size == MMU_PAGE_32KB) ? 1 : \ + (size == MMU_PAGE_16KB) ? 2 : \ + (size == MMU_PAGE_8KB) ? 3 : 0; REG_SET_FIELD(SPI_MEM_S_MMU_POWER_CTRL_REG, SPI_MMU_PAGE_SIZE, reg_val); } else { HAL_ASSERT(false); @@ -234,26 +233,26 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_256KB: - shift_code = 18; - break; - case MMU_PAGE_128KB: - shift_code = 17; - break; - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_256KB: + shift_code = 18; + break; + case MMU_PAGE_128KB: + shift_code = 17; + break; + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code); } @@ -275,26 +274,26 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_ mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_256KB: - shift_code = 18; - break; - case MMU_PAGE_128KB: - shift_code = 17; - break; - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_256KB: + shift_code = 18; + break; + case MMU_PAGE_128KB: + shift_code = 17; + break; + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } return paddr >> shift_code; } @@ -485,20 +484,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } if (mmu_id == MMU_LL_FLASH_MMU_ID) { REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, entry_id); @@ -569,20 +568,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - case MMU_PAGE_8KB: - shift_code = 13; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + case MMU_PAGE_8KB: + shift_code = 13; + break; + default: + HAL_ASSERT(shift_code); } uint32_t laddr = entry_id << shift_code; return mmu_ll_laddr_to_vaddr(laddr, type, (mmu_id == MMU_LL_FLASH_MMU_ID) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0); diff --git a/components/hal/esp32s31/include/hal/modem_syscon_ll.h b/components/hal/esp32s31/include/hal/modem_syscon_ll.h index 11fe5f0ef88..99cc9a21843 100644 --- a/components/hal/esp32s31/include/hal/modem_syscon_ll.h +++ b/components/hal/esp32s31/include/hal/modem_syscon_ll.h @@ -371,11 +371,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) hw->modem_rst_conf.val = 0; } - __attribute__((always_inline)) static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) { - if(en){ + if (en) { hw->clk_conf1.val = hw->clk_conf1.val | mask; } else { hw->clk_conf1.val = hw->clk_conf1.val & ~mask; diff --git a/components/hal/esp32s31/modem_clock_hal.c b/components/hal/esp32s31/modem_clock_hal.c index 381bbb95890..6a69cadd4b5 100644 --- a/components/hal/esp32s31/modem_clock_hal.c +++ b/components/hal/esp32s31/modem_clock_hal.c @@ -23,8 +23,7 @@ typedef enum { void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap) { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: modem_syscon_ll_set_modem_apb_icg_bitmap(hal->syscon_dev, bitmap); break; @@ -73,8 +72,7 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c { HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); uint32_t bitmap = 0; - switch (domain) - { + switch (domain) { case MODEM_CLOCK_DOMAIN_MODEM_APB: bitmap = modem_syscon_ll_get_modem_apb_icg_bitmap(hal->syscon_dev); break; @@ -185,8 +183,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(hal->lpcon_dev, true); break; @@ -225,8 +222,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); break; @@ -265,8 +261,7 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); - switch (src) - { + switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: modem_lpcon_ll_enable_wifi_lpclk_slow_osc(hal->lpcon_dev, true); break; diff --git a/components/hal/hal_utils.c b/components/hal/hal_utils.c index 9e4aa794ce6..c1e153532b6 100644 --- a/components/hal/hal_utils.c +++ b/components/hal/hal_utils.c @@ -119,7 +119,7 @@ uint32_t hal_utils_calc_clk_div_integer(const hal_utils_clk_info_t *clk_info, ui Or, do the normal rounding and error >= (src/n + src/(n+1)) / 2, then carry the bit */ if ((freq_error && clk_info->round_opt == HAL_DIV_ROUND_UP) || (clk_info->round_opt == HAL_DIV_ROUND && - (freq_error >= clk_info->src_freq_hz / (2 * div_integ * (div_integ + 1))))) { + (freq_error >= clk_info->src_freq_hz / (2 * div_integ * (div_integ + 1))))) { div_integ++; } /* Check the integral division whether in range [min_integ, max_integ) */ @@ -186,7 +186,7 @@ int hal_utils_float_to_fixed_point_32b(float flt, const hal_utils_fixed_point_t if (ret != 0 && fp_cfg->saturation) { *fp_out = (f->sign << (fp_cfg->int_bit + fp_cfg->frac_bit)) | - (BIT_MASK(fp_cfg->int_bit + fp_cfg->frac_bit)); + (BIT_MASK(fp_cfg->int_bit + fp_cfg->frac_bit)); } else { *fp_out = output; } diff --git a/components/hal/include/hal/assist_debug_hal.h b/components/hal/include/hal/assist_debug_hal.h index cdbfcb7a630..6eceee751f7 100644 --- a/components/hal/include/hal/assist_debug_hal.h +++ b/components/hal/include/hal/assist_debug_hal.h @@ -17,7 +17,6 @@ extern "C" { #endif - #if SOC_ASSIST_DEBUG_SUPPORTED FORCE_INLINE_ATTR void assist_debug_hal_sp_int_enable(uint32_t core_id) { diff --git a/components/hal/include/hal/color_types.h b/components/hal/include/hal/color_types.h index a17dc7af3a9..44757cda65e 100644 --- a/components/hal/include/hal/color_types.h +++ b/components/hal/include/hal/color_types.h @@ -184,7 +184,6 @@ typedef uint32_t esp_color_fourcc_t; */ #define ESP_COLOR_FOURCC_RAW16 ESP_COLOR_FOURCC('R', 'A', 'W', 'G') /* 16 bpp, raw16 */ - /*--------------------------------------------------------------- Color Conversion ---------------------------------------------------------------*/ diff --git a/components/hal/include/hal/debug_probe_types.h b/components/hal/include/hal/debug_probe_types.h index 0eddc341153..27c9e34720e 100644 --- a/components/hal/include/hal/debug_probe_types.h +++ b/components/hal/include/hal/debug_probe_types.h @@ -10,7 +10,6 @@ extern "C" { #endif - /** * @brief Debug probe unit identifier (HP vs LP) */ diff --git a/components/hal/include/hal/efuse_hal.h b/components/hal/include/hal/efuse_hal.h index d688675508a..0278ebd6b6a 100644 --- a/components/hal/include/hal/efuse_hal.h +++ b/components/hal/include/hal/efuse_hal.h @@ -14,7 +14,6 @@ extern "C" { #endif - /** * @brief get factory mac address */ @@ -74,7 +73,6 @@ uint32_t efuse_hal_get_minor_chip_version(void); */ uint32_t efuse_hal_get_chip_ver_pkg(void); - #if SOC_RECOVERY_BOOTLOADER_SUPPORTED #define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LEN (12) diff --git a/components/hal/include/hal/interrupt_clic_ll.h b/components/hal/include/hal/interrupt_clic_ll.h index e76c421143f..4ee2971a3b5 100644 --- a/components/hal/include/hal/interrupt_clic_ll.h +++ b/components/hal/include/hal/interrupt_clic_ll.h @@ -10,7 +10,6 @@ #include "soc/soc_caps.h" #include "soc/reg_base.h" - #if SOC_INT_CLIC_SUPPORTED #include "soc/clic_reg.h" @@ -24,7 +23,6 @@ extern "C" { /* Use the closest upper power of two (minus 1) as a mask for the interrupts mapping */ #define RV_INT_MASK 63 - /** * @brief Route any interrupt source to any CPU interrupt, including internal ones * @@ -47,7 +45,6 @@ FORCE_INLINE_ATTR void interrupt_clic_ll_route(uint32_t core_id, int intr_src, i #endif // SOC_CPU_CORES_NUM > 1 } - /** * @brief Get the type for the given interrupt * @@ -60,7 +57,6 @@ FORCE_INLINE_ATTR int interrupt_clic_ll_get_type(int rv_int_num) return REG_GET_FIELD(CLIC_INT_CTRL_REG(rv_int_num), CLIC_INT_ATTR_TRIG) & 1; } - /** * @brief Get the priority for the given interrupt * @@ -74,7 +70,6 @@ FORCE_INLINE_ATTR int interrupt_clic_ll_get_priority(int rv_int_num) return (priority >> (8 - NLBITS)); } - /** * @brief Check if an interrupt is vectored * @@ -88,7 +83,6 @@ FORCE_INLINE_ATTR bool interrupt_clic_ll_is_vectored(int rv_int_num) return shv != 0; } - /** * @brief Set an interrupt to vectored or non-vectored * diff --git a/components/hal/include/hal/interrupt_intc_ll.h b/components/hal/include/hal/interrupt_intc_ll.h index dceeb1c14a4..389ae94f58f 100644 --- a/components/hal/include/hal/interrupt_intc_ll.h +++ b/components/hal/include/hal/interrupt_intc_ll.h @@ -17,7 +17,6 @@ extern "C" { #endif - /** * @brief Route any interrupt source to any CPU interrupt, including internal ones * @@ -29,7 +28,6 @@ FORCE_INLINE_ATTR void interrupt_intc_ll_route(int intr_src, int intr_num) REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num); } - /** * @brief Get interrupt enable mask * @@ -40,7 +38,6 @@ FORCE_INLINE_ATTR uint32_t interrupt_intc_ll_get_unmask(void) return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG); } - /** * @brief Get the type for the given interrupt * @@ -54,7 +51,6 @@ FORCE_INLINE_ATTR int interrupt_intc_ll_get_type(int rv_int_num) return (intr_type_reg & (1 << rv_int_num)); } - /** * @brief Get the priority for the given interrupt * @@ -67,7 +63,6 @@ FORCE_INLINE_ATTR int interrupt_intc_ll_get_priority(int rv_int_num) return REG_READ(INTERRUPT_PRIO_REG(rv_int_num)); } - #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/interrupt_plic_ll.h b/components/hal/include/hal/interrupt_plic_ll.h index ab6993c1d17..29626b4d4c2 100644 --- a/components/hal/include/hal/interrupt_plic_ll.h +++ b/components/hal/include/hal/interrupt_plic_ll.h @@ -13,12 +13,10 @@ #include "soc/interrupt_reg.h" #include "soc/plic_reg.h" - #ifdef __cplusplus extern "C" { #endif - /** * @brief Route any interrupt source to any CPU interrupt, including internal ones * @@ -30,7 +28,6 @@ FORCE_INLINE_ATTR void interrupt_plic_ll_route(int intr_src, int intr_num) REG_WRITE(DR_REG_INTMTX_BASE + 4 * intr_src, intr_num); } - /** * @brief Get interrupt enable mask * @@ -41,7 +38,6 @@ FORCE_INLINE_ATTR uint32_t interrupt_plic_ll_get_unmask(void) return REG_READ(PLIC_MXINT_ENABLE_REG); } - /** * @brief Get the type for the given interrupt * @@ -55,7 +51,6 @@ FORCE_INLINE_ATTR int interrupt_plic_ll_get_type(int rv_int_num) return (intr_type_reg & (1 << rv_int_num)); } - /** * @brief Get the priority for the given interrupt * @@ -68,7 +63,6 @@ FORCE_INLINE_ATTR int interrupt_plic_ll_get_priority(int rv_int_num) return REG_READ(INTERRUPT_PRIO_REG(rv_int_num)); } - #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/mmu_hal.h b/components/hal/include/hal/mmu_hal.h index 779af2d068e..4a014983299 100644 --- a/components/hal/include/hal/mmu_hal.h +++ b/components/hal/include/hal/mmu_hal.h @@ -135,7 +135,6 @@ bool mmu_hal_vaddr_to_paddr(uint32_t mmu_id, uint32_t vaddr, uint32_t *out_paddr */ bool mmu_hal_paddr_to_vaddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target, mmu_vaddr_t type, uint32_t *out_vaddr); - /** * Check if the vaddr region is valid * diff --git a/components/hal/mmu_hal.c b/components/hal/mmu_hal.c index 5c83a9681fd..eb709301484 100644 --- a/components/hal/mmu_hal.c +++ b/components/hal/mmu_hal.c @@ -54,17 +54,17 @@ uint32_t mmu_hal_pages_to_bytes(uint32_t mmu_id, uint32_t page_num) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + default: + HAL_ASSERT(shift_code); } return page_num << shift_code; } @@ -74,17 +74,17 @@ uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t bytes) mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id); uint32_t shift_code = 0; switch (page_size) { - case MMU_PAGE_64KB: - shift_code = 16; - break; - case MMU_PAGE_32KB: - shift_code = 15; - break; - case MMU_PAGE_16KB: - shift_code = 14; - break; - default: - HAL_ASSERT(shift_code); + case MMU_PAGE_64KB: + shift_code = 16; + break; + case MMU_PAGE_32KB: + shift_code = 15; + break; + case MMU_PAGE_16KB: + shift_code = 14; + break; + default: + HAL_ASSERT(shift_code); } return bytes >> shift_code; } diff --git a/components/hal/platform_port/include/hal/log.h b/components/hal/platform_port/include/hal/log.h index 0d42fe9bb92..6a0bbdb5e33 100644 --- a/components/hal/platform_port/include/hal/log.h +++ b/components/hal/platform_port/include/hal/log.h @@ -44,33 +44,33 @@ #define HAL_LOG_ATTR_TAG_DRAM(tag, str) static __attribute__((unused)) DRAM_ATTR const char tag[] = str #if CONFIG_HAL_LOG_LEVEL >= HAL_LOG_ERROR - #define HAL_LOGE(tag, fmt, ...) esp_rom_printf("%s(err): " fmt, tag, ##__VA_ARGS__) +#define HAL_LOGE(tag, fmt, ...) esp_rom_printf("%s(err): " fmt, tag, ##__VA_ARGS__) #else - #define HAL_LOGE(tag, fmt, ...) +#define HAL_LOGE(tag, fmt, ...) #endif #if CONFIG_HAL_LOG_LEVEL >= HAL_LOG_WARN - #define HAL_LOGW(tag, fmt, ...) esp_rom_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) +#define HAL_LOGW(tag, fmt, ...) esp_rom_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) #else - #define HAL_LOGW(tag, fmt, ...) +#define HAL_LOGW(tag, fmt, ...) #endif #if CONFIG_HAL_LOG_LEVEL >= HAL_LOG_INFO - #define HAL_LOGI(tag, fmt, ...) esp_rom_printf("%s(info): " fmt, tag, ##__VA_ARGS__) +#define HAL_LOGI(tag, fmt, ...) esp_rom_printf("%s(info): " fmt, tag, ##__VA_ARGS__) #else - #define HAL_LOGI(tag, fmt, ...) +#define HAL_LOGI(tag, fmt, ...) #endif #if CONFIG_HAL_LOG_LEVEL >= HAL_LOG_DEBUG - #define HAL_LOGD(tag, fmt, ...) esp_rom_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) +#define HAL_LOGD(tag, fmt, ...) esp_rom_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) #else - #define HAL_LOGD(tag, fmt, ...) +#define HAL_LOGD(tag, fmt, ...) #endif #if CONFIG_HAL_LOG_LEVEL >= HAL_LOG_VERBOSE - #define HAL_LOGV(tag, fmt, ...) esp_rom_printf("%s: " fmt, tag, ##__VA_ARGS__) +#define HAL_LOGV(tag, fmt, ...) esp_rom_printf("%s: " fmt, tag, ##__VA_ARGS__) #else - #define HAL_LOGV(tag, fmt, ...) +#define HAL_LOGV(tag, fmt, ...) #endif #define HAL_EARLY_LOGE(...) HAL_LOGE(__VA_ARGS__) diff --git a/components/hal/test_apps/hal_utils/main/test_app_main.c b/components/hal/test_apps/hal_utils/main/test_app_main.c index be6b1a087c6..dcd09cc2fa8 100644 --- a/components/hal/test_apps/hal_utils/main/test_app_main.c +++ b/components/hal/test_apps/hal_utils/main/test_app_main.c @@ -10,13 +10,13 @@ void app_main(void) { -/** - * _ _ _ _ _ _ _____ ___ _ ____ - * | | | | / \ | | | | | |_ _|_ _| | / ___| - * | |_| | / _ \ | | | | | | | | | || | \___ \ - * | _ |/ ___ \| |___ | |_| | | | | || |___ ___) | - * |_| |_/_/ \_\_____| \___/ |_| |___|_____|____/ - */ + /** + * _ _ _ _ _ _ _____ ___ _ ____ + * | | | | / \ | | | | | |_ _|_ _| | / ___| + * | |_| | / _ \ | | | | | | | | | || | \___ \ + * | _ |/ ___ \| |___ | |_| | | | | || |___ ___) | + * |_| |_/_/ \_\_____| \___/ |_| |___|_____|____/ + */ printf(" _ _ _ _ _ _ _____ ___ _ ____ \r\n"); printf(" | | | | / \\ | | | | | |_ _|_ _| | / ___| \r\n"); printf(" | |_| | / _ \\ | | | | | | | | | || | \\___ \\ \r\n"); diff --git a/components/hal/test_apps/hal_utils/main/test_calc_clk_div.c b/components/hal/test_apps/hal_utils/main/test_calc_clk_div.c index f332cb22697..c1ab968b69f 100644 --- a/components/hal/test_apps/hal_utils/main/test_calc_clk_div.c +++ b/components/hal/test_apps/hal_utils/main/test_calc_clk_div.c @@ -8,7 +8,6 @@ #include "unity.h" #include "hal/hal_utils.h" - TEST_CASE("test_integral_division", "[clk_div]") { uint32_t int_div = 0; diff --git a/tools/ci/astyle-rules.yml b/tools/ci/astyle-rules.yml index 2f089794fdd..b9529804555 100644 --- a/tools/ci/astyle-rules.yml +++ b/tools/ci/astyle-rules.yml @@ -65,7 +65,6 @@ components_not_formatted_temporary: - "/components/esp-tls/" - "/components/esptool_py/" - "/components/fatfs/" - - "/components/hal/" - "/components/heap/" - "/components/idf_test/" - "/components/ieee802154/"