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ci(astyle): reformat the hal component by astyle_py

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This commit is contained in:
morris
2026-06-01 13:29:38 +08:00
parent ca4952594a
commit 494b2f8de1
124 changed files with 1221 additions and 1432 deletions
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components/hal/esp32s2/include/hal/cache_ll.h
+8 -18
View File
@@ -19,7 +19,6 @@
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2
@@ -40,7 +39,6 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -94,8 +92,7 @@ static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cach
{
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
bool enabled = false;
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
enabled = cache_ll_l1_is_icache_autoload_enabled();
break;
@@ -206,8 +203,7 @@ static inline void cache_ll_l1_disable_dcache(void)
__attribute__((always_inline))
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_disable_icache();
break;
@@ -255,8 +251,7 @@ static inline void cache_ll_l1_enable_dcache(bool data_autoload_en)
__attribute__((always_inline))
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_enable_icache(inst_autoload_en);
break;
@@ -298,8 +293,7 @@ static inline void cache_ll_l1_suspend_dcache(void)
__attribute__((always_inline))
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_suspend_icache();
break;
@@ -347,8 +341,7 @@ static inline void cache_ll_l1_resume_dcache(bool data_autoload_en)
__attribute__((always_inline))
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
cache_ll_l1_resume_icache(inst_autoload_en);
break;
@@ -407,8 +400,7 @@ __attribute__((always_inline))
static inline bool cache_ll_is_cache_enabled(cache_type_t type)
{
bool enabled = false;
switch (type)
{
switch (type) {
case CACHE_TYPE_DATA:
enabled = cache_ll_l1_is_dcache_enabled(0);
break;
@@ -449,8 +441,7 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
__attribute__((always_inline))
static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
switch (type)
{
switch (type) {
case CACHE_TYPE_DATA:
Cache_Invalidate_DCache_All();
break;
@@ -520,8 +511,7 @@ __attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
uint32_t size = 0;
switch (type)
{
switch (type) {
case CACHE_TYPE_INSTRUCTION:
size = cache_ll_l1_icache_get_line_size();
break;
components/hal/esp32s2/include/hal/crosscore_int_ll.h
-3
View File
@@ -11,7 +11,6 @@
extern "C" {
#endif
/**
* @brief Clear the crosscore interrupt that just occurred on the current core
*/
@@ -20,7 +19,6 @@ static inline void crosscore_int_ll_clear_interrupt(int core_id)
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
}
/**
* @brief Trigger a crosscore interrupt on the given core
*
@@ -31,7 +29,6 @@ static inline void crosscore_int_ll_trigger_interrupt(int core_id)
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
}
#ifdef __cplusplus
}
#endif
components/hal/esp32s2/include/hal/memprot_ll.h
+1 -4
View File
@@ -82,7 +82,7 @@ static inline uint32_t memprot_ll_iram0_get_intr_clr_bit(void)
//resets automatically on CPU restart
static inline void memprot_ll_iram0_set_lock(void)
{
DPORT_WRITE_PERI_REG( DPORT_PMS_PRO_IRAM0_0_REG, DPORT_PMS_PRO_IRAM0_LOCK);
DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_0_REG, DPORT_PMS_PRO_IRAM0_LOCK);
}
static inline uint32_t memprot_ll_iram0_get_lock_reg(void)
@@ -393,7 +393,6 @@ static inline void memprot_ll_iram0_sram_set_exec_perm(bool lx, bool hx)
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_F, hx ? 1 : 0);
}
/**
* ========================================================================================
* === IRAM0 RTC FAST
@@ -489,7 +488,6 @@ static inline void memprot_ll_iram0_rtcfast_set_exec_perm(bool lx, bool hx)
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_F, hx ? 1 : 0);
}
/**
* ========================================================================================
* === DRAM0 common
@@ -782,7 +780,6 @@ static inline void memprot_ll_dram0_sram_set_write_perm(bool lw, bool hw)
DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_W, hw ? 1 : 0);
}
/**
* ========================================================================================
* === DRAM0 RTC FAST
components/hal/esp32s2/include/hal/mmu_ll.h
-1
View File
@@ -15,7 +15,6 @@
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
components/hal/esp32s2/include/hal/sar_ctrl_ll.h
-2
View File
@@ -30,7 +30,6 @@ extern "C" {
#define PWDET_SAR_POWER_FORCE BIT(7)
#define PWDET_SAR_POWER_CNTL BIT(6)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
@@ -77,7 +76,6 @@ static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mod
}
}
#ifdef __cplusplus
}
#endif
components/hal/esp32s2/include/hal/trace_ll.h
+1 -1
View File
@@ -15,7 +15,7 @@ extern "C" {
static inline void trace_ll_set_mem_block(int block)
{
DPORT_WRITE_PERI_REG(DPORT_PMS_OCCUPY_3_REG, BIT(block-4));
DPORT_WRITE_PERI_REG(DPORT_PMS_OCCUPY_3_REG, BIT(block - 4));
}
#ifdef __cplusplus