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ci(astyle): reformat the hal component by astyle_py

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This commit is contained in:
morris
2026-06-01 13:29:38 +08:00
parent ca4952594a
commit 494b2f8de1
124 changed files with 1221 additions and 1432 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/hal/esp32p4/include/hal/assist_debug_ll.h
+2 -2
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@@ -58,8 +58,8 @@ extern "C" {
* interrupt, instead of "ENA".
*/
/* These functions are optimized and designed for internal usage.
* So, the API may differ from general ll layer pattern */
/* These functions are optimized and designed for internal usage.
* So, the API may differ from general ll layer pattern */
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id)
{
components/hal/esp32p4/include/hal/cache_ll.h
-1
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@@ -63,7 +63,6 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
components/hal/esp32p4/include/hal/cpu_utility_ll.h
+2 -2
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@@ -46,10 +46,10 @@ FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
{
if (cpu_no == 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore0_stall_code, 0xFF);
while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST));
while (REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_sw_stall, hpcore1_stall_code, 0xFF);
while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST));
while (REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST));
}
}
components/hal/esp32p4/include/hal/crosscore_int_ll.h
-4
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@@ -12,7 +12,6 @@
extern "C" {
#endif
/**
* @brief Clear the crosscore interrupt that just occurred on the current core
*/
@@ -25,7 +24,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
}
}
/**
* @brief Trigger a crosscore interrupt on the given core
*
@@ -40,7 +38,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
}
}
/**
* @brief Get the state of the crosscore interrupt register for the given core
*
@@ -62,7 +59,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
return reg;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32p4/include/hal/lp_clkrst_ll.h
-1
View File
@@ -17,7 +17,6 @@
extern "C" {
#endif
/**
* Select CPU reset vector
* @param boot_from_lp_ram
components/hal/esp32p4/include/hal/lp_core_ll.h
-3
View File
@@ -21,7 +21,6 @@
extern "C" {
#endif
#define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(9)
#define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(10)
#define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_0 BIT(13)
@@ -68,7 +67,6 @@ static inline void lp_core_ll_reset_register(void)
lp_core_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* @brief Trigger a LP_CORE_LL_WAKEUP_SOURCE_HP_CPU wake-up on the lp core
*
@@ -136,7 +134,6 @@ static inline void lp_core_ll_set_boot_address(intptr_t boot_address)
LP_SYS.lp_core_boot_addr.lp_cpu_boot_addr = boot_address;
}
/**
* @brief Set address LP-ROM bootloader will jump to after initialization
*
components/hal/esp32p4/include/hal/lp_mailbox_ll.h
-1
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@@ -42,7 +42,6 @@ FORCE_INLINE_ATTR void lp_mailbox_ll_reset_register(lp_mb_dev_t *dev)
(void) dev;
}
/**
* @brief Get a message (32-bit value) from the LP mailbox.
*
components/hal/esp32p4/include/hal/lp_sys_ll.h
-1
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@@ -16,7 +16,6 @@
#include "hal/config.h"
#include "esp32p4/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
components/hal/esp32p4/include/hal/mmu_ll.h
+56 -57
View File
@@ -17,7 +17,6 @@
#include "hal/efuse_ll.h"
#include "esp_fault.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -202,20 +201,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
}
@@ -237,20 +236,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
return paddr >> shift_code;
}
@@ -470,20 +469,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
if (mmu_id == MMU_LL_FLASH_MMU_ID) {
REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, entry_id);
@@ -554,20 +553,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
uint32_t laddr = entry_id << shift_code;
return mmu_ll_laddr_to_vaddr(laddr, type, (mmu_id == MMU_LL_FLASH_MMU_ID) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0);
components/hal/esp32p4/include/hal/sar_ctrl_ll.h
-1
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@@ -30,7 +30,6 @@ extern "C" {
#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on