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ci(astyle): reformat the hal component by astyle_py

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This commit is contained in:
morris
2026-06-01 13:29:38 +08:00
parent ca4952594a
commit 494b2f8de1
124 changed files with 1221 additions and 1432 deletions
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components/hal/esp32h4/include/hal/aes_ll.h
+2 -4
View File
@@ -110,7 +110,7 @@ static inline void aes_ll_read_block(void *output)
for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH));
/* Memcpy to avoid potential unaligned access */
memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
}
}
@@ -123,7 +123,6 @@ static inline void aes_ll_start_transform(void)
REG_WRITE(AES_TRIGGER_REG, 1);
}
/**
* @brief Read state of AES accelerator
*
@@ -134,7 +133,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
return (esp_aes_state_t)REG_READ(AES_STATE_REG);
}
/**
* @brief Set mode of operation
*
@@ -187,7 +185,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM);
uint32_t iv_word;
for (int i = 0; i < IV_WORDS; i++ ) {
for (int i = 0; i < IV_WORDS; i++) {
/* Memcpy to avoid potential unaligned access */
memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
REG_WRITE(&reg_addr_buf[i], iv_word);
components/hal/esp32h4/include/hal/assist_debug_ll.h
+8 -8
View File
@@ -188,10 +188,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, in
{
if (core_id) {
return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_cause_1.monitor_core_1_trace_lockup_recording_cause_1
: BUS_MONITOR.monitor_core_1_trace_lockup_cause_0.monitor_core_1_trace_lockup_recording_cause_0;
: BUS_MONITOR.monitor_core_1_trace_lockup_cause_0.monitor_core_1_trace_lockup_recording_cause_0;
} else {
return trap_idx ? BUS_MONITOR.monitor_core_0_trace_lockup_cause_1.monitor_core_0_trace_lockup_recording_cause_1
: BUS_MONITOR.monitor_core_0_trace_lockup_cause_0.monitor_core_0_trace_lockup_recording_cause_0;
: BUS_MONITOR.monitor_core_0_trace_lockup_cause_0.monitor_core_0_trace_lockup_recording_cause_0;
}
}
@@ -199,10 +199,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int
{
if (core_id) {
return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_tval_1.monitor_core_1_trace_lockup_recording_tval_1
: BUS_MONITOR.monitor_core_1_trace_lockup_tval_0.monitor_core_1_trace_lockup_recording_tval_0;
: BUS_MONITOR.monitor_core_1_trace_lockup_tval_0.monitor_core_1_trace_lockup_recording_tval_0;
} else {
return trap_idx ? BUS_MONITOR.monitor_core_0_trace_lockup_tval_1.monitor_core_0_trace_lockup_recording_tval_1
: BUS_MONITOR.monitor_core_0_trace_lockup_tval_0.monitor_core_0_trace_lockup_recording_tval_0;
: BUS_MONITOR.monitor_core_0_trace_lockup_tval_0.monitor_core_0_trace_lockup_recording_tval_0;
}
}
@@ -210,10 +210,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, in
{
if (core_id) {
return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_iaddr_1.monitor_core_1_trace_lockup_recording_iaddr_1
: BUS_MONITOR.monitor_core_1_trace_lockup_iaddr_0.monitor_core_1_trace_lockup_recording_iaddr_0;
: BUS_MONITOR.monitor_core_1_trace_lockup_iaddr_0.monitor_core_1_trace_lockup_recording_iaddr_0;
} else {
return trap_idx ? BUS_MONITOR.monitor_core_0_trace_lockup_iaddr_1.monitor_core_0_trace_lockup_recording_iaddr_1
: BUS_MONITOR.monitor_core_0_trace_lockup_iaddr_0.monitor_core_0_trace_lockup_recording_iaddr_0;
: BUS_MONITOR.monitor_core_0_trace_lockup_iaddr_0.monitor_core_0_trace_lockup_recording_iaddr_0;
}
}
@@ -221,10 +221,10 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int
{
if (core_id) {
return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_priv_1.monitor_core_1_trace_lockup_recording_priv_1
: BUS_MONITOR.monitor_core_1_trace_lockup_priv_0.monitor_core_1_trace_lockup_recording_priv_0;
: BUS_MONITOR.monitor_core_1_trace_lockup_priv_0.monitor_core_1_trace_lockup_recording_priv_0;
} else {
return trap_idx ? BUS_MONITOR.monitor_core_0_trace_lockup_priv_1.monitor_core_0_trace_lockup_recording_priv_1
: BUS_MONITOR.monitor_core_0_trace_lockup_priv_0.monitor_core_0_trace_lockup_recording_priv_0;
: BUS_MONITOR.monitor_core_0_trace_lockup_priv_0.monitor_core_0_trace_lockup_recording_priv_0;
}
}
components/hal/esp32h4/include/hal/cache_ll.h
+1 -3
View File
@@ -43,7 +43,6 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -578,7 +577,6 @@ static inline void cache_ll_writeback_all(uint32_t cache_level, cache_type_t typ
}
}
/*------------------------------------------------------------------------------
* Freeze
*----------------------------------------------------------------------------*/
@@ -889,7 +887,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{
//On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
if (bus_id == 0) {
components/hal/esp32h4/include/hal/cpu_utility_ll.h
+2 -2
View File
@@ -44,10 +44,10 @@ FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
{
if (cpu_no == 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.cpucore_cfg, aon_cpu_core0_sw_stall, 0xFF);
while(REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE0_RUNSTALLED));
while (REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE0_RUNSTALLED));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.cpucore_cfg, aon_cpu_core1_sw_stall, 0xFF);
while(REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE1_RUNSTALLED));
while (REG_GET_BIT(HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG, HP_SYSTEM_CORE1_RUNSTALLED));
}
}
components/hal/esp32h4/include/hal/crosscore_int_ll.h
-3
View File
@@ -24,7 +24,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
}
}
/**
* @brief Trigger a crosscore interrupt on the given core
*
@@ -40,7 +39,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
}
}
/**
* @brief Get the state of the crosscore interrupt register for the given core
*
@@ -62,7 +60,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
return reg;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32h4/include/hal/lp_aon_ll.h
-2
View File
@@ -14,7 +14,6 @@
#include "hal/misc.h"
#include "esp32h4/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -76,7 +75,6 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel);
}
/**
* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
* Set the flag to inform
components/hal/esp32h4/include/hal/mmu_ll.h
+60 -60
View File
@@ -74,10 +74,10 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
(void)mmu_id;
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE);
return (page_size_code == 0) ? MMU_PAGE_64KB : \
(page_size_code == 1) ? MMU_PAGE_32KB : \
(page_size_code == 2) ? MMU_PAGE_16KB : \
MMU_PAGE_8KB;
return (page_size_code == 0) ? MMU_PAGE_64KB : \
(page_size_code == 1) ? MMU_PAGE_32KB : \
(page_size_code == 2) ? MMU_PAGE_16KB : \
MMU_PAGE_8KB;
}
/**
@@ -149,20 +149,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
}
@@ -185,20 +185,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
return paddr >> shift_code;
}
@@ -325,20 +325,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
@@ -387,20 +387,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
uint32_t laddr = entry_id << shift_code;
components/hal/esp32h4/include/hal/modem_etm_ll.h
+20 -20
View File
@@ -37,16 +37,16 @@ extern "C" {
static inline bool modem_etm_ll_get_group_event_status(int group_id)
{
switch (group_id) {
case 0:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g0_st;
case 1:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g1_st;
case 2:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g2_st;
case 3:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g3_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g0_st;
case 1:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g1_st;
case 2:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g2_st;
case 3:
return SOC_ETM.etm_evt_st6.etm_modem_evt_g3_st;
default:
HAL_ASSERT(false);
}
return false;
}
@@ -54,16 +54,16 @@ static inline bool modem_etm_ll_get_group_event_status(int group_id)
static inline bool modem_etm_ll_get_group_task_status(int group_id)
{
switch (group_id) {
case 0:
return SOC_ETM.etm_task_st5.etm_modem_task_g0_st;
case 1:
return SOC_ETM.etm_task_st5.etm_modem_task_g1_st;
case 2:
return SOC_ETM.etm_task_st5.etm_modem_task_g2_st;
case 3:
return SOC_ETM.etm_task_st5.etm_modem_task_g3_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.etm_task_st5.etm_modem_task_g0_st;
case 1:
return SOC_ETM.etm_task_st5.etm_modem_task_g1_st;
case 2:
return SOC_ETM.etm_task_st5.etm_modem_task_g2_st;
case 3:
return SOC_ETM.etm_task_st5.etm_modem_task_g3_st;
default:
HAL_ASSERT(false);
}
return false;
}
components/hal/esp32h4/include/hal/modem_syscon_ll.h
+1 -3
View File
@@ -345,11 +345,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
hw->modem_rst_conf.val = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
{
if(en){
if (en) {
hw->clk_conf1.val = hw->clk_conf1.val | mask;
} else {
hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
@@ -398,7 +397,6 @@ static inline bool modem_syscon_ll_fe_32m_clock_is_enabled(modem_syscon_dev_t *h
return hw->clk_conf1.clk_fe_32m_en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_sdm_clock(modem_syscon_dev_t *hw, bool en)
{
components/hal/esp32h4/include/hal/sar_ctrl_ll.h
-1
View File
@@ -29,7 +29,6 @@ extern "C" {
#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on
components/hal/esp32h4/include/hal/sha_ll.h
-1
View File
@@ -14,7 +14,6 @@
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*