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ci(astyle): reformat the hal component by astyle_py

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This commit is contained in:
morris
2026-06-01 13:29:38 +08:00
parent ca4952594a
commit 494b2f8de1
124 changed files with 1221 additions and 1432 deletions
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components/hal/esp32c5/include/hal/assist_debug_ll.h
+3 -3
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@@ -58,8 +58,8 @@ extern "C" {
* actually triggering the interrupt.
*/
/* These functions are optimized and designed for internal usage.
* So, the API may differ from general ll layer pattern */
/* These functions are optimized and designed for internal usage.
* So, the API may differ from general ll layer pattern */
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id)
{
@@ -133,7 +133,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui
FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void)
{
return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
}
#ifdef __cplusplus
components/hal/esp32c5/include/hal/cache_ll.h
-1
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@@ -43,7 +43,6 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
components/hal/esp32c5/include/hal/crosscore_int_ll.h
-4
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@@ -12,7 +12,6 @@
extern "C" {
#endif
/**
* @brief Clear the crosscore interrupt that just occurred on the current core
*/
@@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0);
}
/**
* @brief Trigger a crosscore interrupt on the given core
*
@@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0);
}
/**
* @brief Get the state of the crosscore interrupt register for the given core
*
@@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG);
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c5/include/hal/efuse_ll.h
+1 -1
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@@ -126,7 +126,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_dbg(void
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_lp_dbias(void)
{
return (EFUSE.rd_mac_sys4.dslp_lp_dbias_1 << 4)|EFUSE.rd_mac_sys3.dslp_lp_dbias;
return (EFUSE.rd_mac_sys4.dslp_lp_dbias_1 << 4) | EFUSE.rd_mac_sys3.dslp_lp_dbias;
}
__attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void)
components/hal/esp32c5/include/hal/lp_aon_ll.h
-2
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@@ -14,7 +14,6 @@
#include "hal/misc.h"
#include "esp32c5/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -69,7 +68,6 @@ static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
}
/**
* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
* Set the flag to inform
components/hal/esp32c5/include/hal/lp_core_ll.h
-1
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@@ -20,7 +20,6 @@
extern "C" {
#endif
#define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup)
#define LP_CORE_LL_WAKEUP_SOURCE_LP_UART BIT(1) // Enable wake-up by a certain number of LP UART RX pulses
#define LP_CORE_LL_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt
components/hal/esp32c5/include/hal/mmu_ll.h
+56 -57
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@@ -21,7 +21,6 @@
#include "hal/efuse_hal.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
@@ -151,20 +150,20 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
}
@@ -186,20 +185,20 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
return paddr >> shift_code;
}
@@ -349,20 +348,20 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
@@ -409,20 +408,20 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
case MMU_PAGE_8KB:
shift_code = 13;
break;
default:
HAL_ASSERT(shift_code);
}
uint32_t laddr = entry_id << shift_code;
components/hal/esp32c5/include/hal/modem_syscon_ll.h
+1 -2
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@@ -372,11 +372,10 @@ static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
hw->modem_rst_conf.val = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
{
if(en){
if (en) {
hw->clk_conf1.val = hw->clk_conf1.val | mask;
} else {
hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
components/hal/esp32c5/include/hal/rng_ll.h
-1
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@@ -95,7 +95,6 @@ static inline void rng_ll_disable(void)
_lp_clkrst_ll_enable_rng_clock(false);
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c5/include/hal/sar_ctrl_ll.h
-1
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@@ -29,7 +29,6 @@ extern "C" {
#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23)
typedef enum {
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
SAR_CTRL_LL_POWER_ON, //SAR power on