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ci(astyle): reformat the hal component by astyle_py

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This commit is contained in:
morris
2026-06-01 13:29:38 +08:00
parent ca4952594a
commit 494b2f8de1
124 changed files with 1221 additions and 1432 deletions
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components/hal/esp32c2/include/hal/assist_debug_ll.h
+3 -3
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@@ -56,8 +56,8 @@ extern "C" {
* interrupt, instead of "ENA".
*/
/* These functions are optimized and designed for internal usage.
* So, the API may differ from general ll layer pattern */
/* These functions are optimized and designed for internal usage.
* So, the API may differ from general ll layer pattern */
FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id)
{
@@ -131,7 +131,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) ui
FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void)
{
return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
}
#ifdef __cplusplus
components/hal/esp32c2/include/hal/cache_ll.h
+2 -4
View File
@@ -19,7 +19,6 @@
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
@@ -53,7 +52,6 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
@@ -302,7 +300,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
@@ -323,7 +321,7 @@ __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0);
components/hal/esp32c2/include/hal/crosscore_int_ll.h
-4
View File
@@ -12,7 +12,6 @@
extern "C" {
#endif
/**
* @brief Clear the crosscore interrupt that just occurred on the current core
*/
@@ -21,7 +20,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
}
/**
* @brief Trigger a crosscore interrupt on the given core
*
@@ -32,7 +30,6 @@ FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
}
/**
* @brief Get the state of the crosscore interrupt register for the given core
*
@@ -46,7 +43,6 @@ FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
return REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG);
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c2/include/hal/mmu_ll.h
+44 -45
View File
@@ -14,7 +14,6 @@
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -147,17 +146,17 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
}
return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
@@ -182,17 +181,17 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
}
return paddr >> shift_code;
@@ -306,17 +305,17 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
}
return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
@@ -363,17 +362,17 @@ static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t e
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
}
uint32_t laddr = entry_id << shift_code;
components/hal/esp32c2/include/hal/sar_ctrl_ll.h
-1
View File
@@ -73,7 +73,6 @@ static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mod
}
}
#ifdef __cplusplus
}
#endif