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change(esp_hw_support): esp32p4 rev3.0 dummy read workaround refactor

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This commit is contained in:
wuzhenghui
2025-10-27 20:43:25 +08:00
parent e9da2e3606
commit 487f9204dd
7 changed files with 58 additions and 24 deletions
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1
components/esp_hw_support/CMakeLists.txt
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@@ -64,6 +64,7 @@ if(NOT non_os_build)
list(APPEND srcs "sleep_modem.c"
"sleep_modes.c"
"sleep_console.c"
"sleep_mspi.c"
"sleep_usb.c"
"sleep_gpio.c"
"sleep_event.c"

5
components/esp_hw_support/include/esp_private/esp_pmu.h
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@@ -348,11 +348,6 @@ void pmu_init(void);
*/
uint32_t pmu_sleep_get_wakup_retention_cost(void);
/**
* Workaround for esp32p4 v3 MPSI access failure after power up.
*/
void pmu_sleep_p4_rev3_workaround(void);
#endif //#if SOC_PMU_SUPPORTED
#ifdef __cplusplus

25
components/esp_hw_support/include/esp_private/sleep_flash.h Normal file
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@@ -0,0 +1,25 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
/**
* Workaround for esp32p4 v3 MPSI access failure after power up.
*/
void sleep_flash_p4_rev3_workaround(void);
#endif
#ifdef __cplusplus
}
#endif

1
components/esp_hw_support/linker.lf
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@@ -40,6 +40,7 @@ entries:
rtc_sleep:rtc_sleep_pu (noflash)
if SOC_PMU_SUPPORTED = y && SOC_LIGHT_SLEEP_SUPPORTED = y:
pmu_sleep (noflash)
sleep_mspi (noflash)
if SPIRAM_FLASH_LOAD_TO_PSRAM = y:
pmu_init (noflash)
pmu_param (noflash)

18
components/esp_hw_support/port/esp32p4/pmu_sleep.c
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@@ -506,21 +506,3 @@ uint32_t pmu_sleep_get_wakup_retention_cost(void)
{
return PMU_REGDMA_S2A_WORK_TIME_US;
}
#if (CONFIG_ESP_REV_MIN_FULL == 300)
void pmu_sleep_p4_rev3_workaround(void)
{
REG_CLR_BIT(SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_CLOSE_AXI_INF_EN);
REG_SET_BIT(SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_AXI_REQ_EN);
REG_SET_FIELD(HP_SYSTEM_CORE_ERR_RESP_DIS_REG, HP_SYSTEM_CORE_ERR_RESP_DIS, 0x7);
REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, 0);
uint32_t mmu_backup = mmu_ll_read_entry(MMU_LL_FLASH_MMU_ID, 0);
mmu_ll_write_entry(MMU_LL_FLASH_MMU_ID, 0, 0, MMU_TARGET_FLASH0);
__attribute__((unused)) volatile uint32_t val = 0;
val = *(uint32_t *)(0x80000000);
val = *(uint32_t *)(0x80000080);
mmu_ll_write_entry(MMU_LL_FLASH_MMU_ID, 0, mmu_backup, MMU_TARGET_FLASH0);
_mspi_timing_ll_reset_mspi();
_mspi_timing_ll_reset_mspi_apb();
}
#endif

3
components/esp_hw_support/sleep_modes.c
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@@ -79,6 +79,7 @@
#include "esp_private/sleep_console.h"
#include "esp_private/sleep_cpu.h"
#include "esp_private/sleep_modem.h"
#include "esp_private/sleep_flash.h"
#include "esp_private/sleep_usb.h"
#include "esp_private/esp_clk.h"
#include "esp_private/esp_task_wdt.h"
@@ -966,7 +967,7 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
esp_sleep_mmu_retention(false);
#endif
#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
pmu_sleep_p4_rev3_workaround();
sleep_flash_p4_rev3_workaround();
sleep_retention_do_extra_retention(false);
#endif
}

29
components/esp_hw_support/sleep_mspi.c Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
#include "soc/hp_system_reg.h"
#include "hal/mmu_ll.h"
#include "hal/mspi_ll.h"
void sleep_flash_p4_rev3_workaround(void)
{
REG_CLR_BIT(SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_CLOSE_AXI_INF_EN);
REG_SET_BIT(SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_AXI_REQ_EN);
REG_SET_FIELD(HP_SYSTEM_CORE_ERR_RESP_DIS_REG, HP_SYSTEM_CORE_ERR_RESP_DIS, 0x7);
REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, 0);
uint32_t mmu_backup = mmu_ll_read_entry(MMU_LL_FLASH_MMU_ID, 0);
mmu_ll_write_entry(MMU_LL_FLASH_MMU_ID, 0, 0, MMU_TARGET_FLASH0);
__attribute__((unused)) volatile uint32_t val = 0;
val = REG_READ(0x80000000);
val = REG_READ(0x80000080);
mmu_ll_write_entry(MMU_LL_FLASH_MMU_ID, 0, mmu_backup, MMU_TARGET_FLASH0);
_mspi_timing_ll_reset_mspi();
_mspi_timing_ll_reset_mspi_apb();
REG_SET_FIELD(HP_SYSTEM_CORE_ERR_RESP_DIS_REG, HP_SYSTEM_CORE_ERR_RESP_DIS, 0);
}
#endif