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Merge branch 'bugfix/fixed_parlio_rx_sample_edge_swap_issue_v5.4' into 'release/v5.4'

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fix(parlio_rx): fixed opposite sample edge issue (v5.4)

See merge request espressif/esp-idf!45133
This commit is contained in:
morris
2026-01-15 18:59:29 +08:00
parent f40ec1c990 5fc86507f3
commit 46a38e245e
4 changed files with 19 additions and 13 deletions
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components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
+1 -1
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@@ -368,7 +368,7 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
{
parlio_rx_pulse_delimiter_config_t pls_deli_cfg = {
.valid_sig_line_id = TEST_VALID_SIG,
.sample_edge = PARLIO_SAMPLE_EDGE_NEG,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.eof_data_len = TEST_EOF_DATA_LEN,
.timeout_ticks = 0,
components/hal/esp32c5/include/hal/parlio_ll.h
+6 -4
View File
@@ -258,8 +258,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
__attribute__((always_inline))
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->rx_clk_cfg.rx_clk_i_inv = edge;
dev->rx_clk_cfg.rx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->rx_clk_cfg.rx_clk_i_inv = invert;
dev->rx_clk_cfg.rx_clk_o_inv = invert;
}
/**
@@ -522,8 +523,9 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
}
/**
components/hal/esp32h2/include/hal/parlio_ll.h
+6 -4
View File
@@ -253,8 +253,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
__attribute__((always_inline))
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->rx_clk_cfg.rx_clk_i_inv = edge;
dev->rx_clk_cfg.rx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->rx_clk_cfg.rx_clk_i_inv = invert;
dev->rx_clk_cfg.rx_clk_o_inv = invert;
}
/**
@@ -506,8 +507,9 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
}
/**
components/hal/esp32p4/include/hal/parlio_ll.h
+6 -4
View File
@@ -285,8 +285,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en)
__attribute__((always_inline))
static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->rx_clk_cfg.rx_clk_i_inv = edge;
dev->rx_clk_cfg.rx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->rx_clk_cfg.rx_clk_i_inv = invert;
dev->rx_clk_cfg.rx_clk_o_inv = invert;
}
/**
@@ -571,8 +572,9 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
}
/**