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fix(esp_security): don't reset DS peripheral in esp_hmac_calculate

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esp_hmac_calculate() enabled and reset the Digital Signature (DS)
peripheral, but HMAC has no dependency on DS (the dependency runs the
other way: a DS operation uses HMAC/SHA).

The DS peripheral drives the RSA (MPI) accelerator internally, so pulsing
the DS reset also resets the RSA datapath. This coupling exists on every
target that has the DS peripheral: the MPI reset routine itself clears the
DS reset "otherwise RSA is held in reset".

esp_hmac_calculate() holds only the HMAC and SHA/AES locks, not the MPI
lock, so it can corrupt a concurrent RSA/MPI operation. On multi-core
targets (e.g. ESP32-P4, ESP32-S31, ESP32-S3) an HMAC on one core resets an
RSA op running on another core; on single-core targets (e.g. ESP32-C5) the
same corruption happens when an HMAC preempts an in-flight RSA op. The
result is a wrong RSA result or a crash in the computation.

Remove the DS peripheral enable/reset from the HMAC path. SHA, which HMAC
depends on, is enabled independently, so the HMAC output is unchanged.
This also drops a few redundant register writes.
This commit is contained in:
Ashish Sharma
2026-08-20 17:34:34 +08:00
parent fe465ae1fe
commit 34799be7b9
1 changed files with 1 additions and 12 deletions
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13
components/esp_security/src/esp_hmac.c
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@@ -70,15 +70,11 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
esp_crypto_hmac_lock_acquire();
// We also enable SHA and DS here. SHA is used by HMAC, DS will otherwise hold SHA in reset state.
// SHA is used by HMAC, so enable it here.
esp_crypto_hmac_enable_periph_clk(true);
esp_crypto_sha_enable_periph_clk(true);
#if SOC_DIG_SIGN_SUPPORTED
esp_crypto_ds_enable_periph_clk(true);
#endif
#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
/* Key Manager holds the key usage selector register(efuse vs own key).
Thus, we need to enable the Key Manager peripheral clock to ensure
@@ -93,9 +89,6 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
if (conf_error) {
esp_crypto_sha_enable_periph_clk(false);
esp_crypto_hmac_enable_periph_clk(false);
#if SOC_DIG_SIGN_SUPPORTED
esp_crypto_ds_enable_periph_clk(false);
#endif // SOC_DIG_SIGN_SUPPORTED
#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
esp_crypto_key_mgr_enable_periph_clk(false);
#endif // SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
@@ -159,10 +152,6 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
esp_crypto_key_mgr_enable_periph_clk(false);
#endif /* SOC_KEY_MANAGER_HMAC_KEY_DEPLOY */
#if SOC_DIG_SIGN_SUPPORTED
esp_crypto_ds_enable_periph_clk(false);
#endif
esp_crypto_sha_enable_periph_clk(false);
esp_crypto_hmac_enable_periph_clk(false);